309 struct pci_dev {  struct
310 	struct list_head bus_list;	/* Node in per-bus list */
311 	struct pci_bus	*bus;		/* Bus this device is on */
312 	struct pci_bus	*subordinate;	/* Bus this device bridges to */
314 	void		*sysdata;	/* Hook for sys-specific extension */
315 	struct proc_dir_entry *procent;	/* Device entry in /proc/bus/pci */
316 	struct pci_slot	*slot;		/* Physical slot this device is in */
318 	unsigned int	devfn;		/* Encoded device & function index */
319 	unsigned short	vendor;
320 	unsigned short	device;
321 	unsigned short	subsystem_vendor;
322 	unsigned short	subsystem_device;
323 	unsigned int	class;		/* 3 bytes: (base,sub,prog-if) */
324 	u8		revision;	/* PCI revision, low byte of class word */
325 	u8		hdr_type;	/* PCI header type (`multi' flag masked out) */
327 	u16		aer_cap;	/* AER capability offset */
328 	struct aer_stats *aer_stats;	/* AER stats for this device */
330 	u8		pcie_cap;	/* PCIe capability offset */
331 	u8		msi_cap;	/* MSI capability offset */
332 	u8		msix_cap;	/* MSI-X capability offset */
333 	u8		pcie_mpss:3;	/* PCIe Max Payload Size Supported */
334 	u8		rom_base_reg;	/* Config register controlling ROM */
335 	u8		pin;		/* Interrupt pin this device uses */
336 	u16		pcie_flags_reg;	/* Cached PCIe Capabilities Register */
337 	unsigned long	*dma_alias_mask;/* Mask of enabled devfn aliases */
339 	struct pci_driver *driver;	/* Driver bound to this device */
340 	u64		dma_mask;	/* Mask of the bits of bus address this
346 	struct device_dma_parameters dma_parms;
348 	pci_power_t	current_state;	/* Current operating state. In ACPI,
351 	unsigned int	imm_ready:1;	/* Supports Immediate Readiness */
352 	u8		pm_cap;		/* PM capability offset */
353 	unsigned int	pme_support:5;	/* Bitmask of states from which PME#
355 	unsigned int	pme_poll:1;	/* Poll device's PME status bit */
356 	unsigned int	d1_support:1;	/* Low power state D1 is supported */
357 	unsigned int	d2_support:1;	/* Low power state D2 is supported */
358 	unsigned int	no_d1d2:1;	/* D1 and D2 are forbidden */
359 	unsigned int	no_d3cold:1;	/* D3cold is forbidden */
360 	unsigned int	bridge_d3:1;	/* Allow D3 for bridge */
361 	unsigned int	d3cold_allowed:1;	/* D3cold is allowed by user */
362 	unsigned int	mmio_always_on:1;	/* Disallow turning off io/mem
364 	unsigned int	wakeup_prepared:1;
365 	unsigned int	runtime_d3cold:1;	/* Whether go through runtime
369 	unsigned int	skip_bus_pm:1;	/* Internal: Skip bus-level PM */
370 	unsigned int	ignore_hotplug:1;	/* Ignore hotplug events */
371 	unsigned int	hotplug_user_indicators:1; /* SlotCtl indicators
374 	unsigned int	clear_retrain_link:1;	/* Need to clear Retrain Link
376 	unsigned int	d3hot_delay;	/* D3hot->D0 transition time in ms */
377 	unsigned int	d3cold_delay;	/* D3cold->D0 transition time in ms */
380 	struct pcie_link_state	*link_state;	/* ASPM link state */
381 	unsigned int	ltr_path:1;	/* Latency Tolerance Reporting
383 	int		l1ss;		/* L1SS Capability pointer */
385 	unsigned int	eetlp_prefix_path:1;	/* End-to-End TLP Prefix */
387 	pci_channel_state_t error_state;	/* Current connectivity state */
388 	struct device	dev;			/* Generic device interface */
390 	int		cfg_size;		/* Size of config space */
396 	unsigned int	irq;
397 	struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */
399 	bool		match_driver;		/* Skip attaching driver */
401 	unsigned int	transparent:1;		/* Subtractive decode bridge */
402 	unsigned int	io_window:1;		/* Bridge has I/O window */
403 	unsigned int	pref_window:1;		/* Bridge has pref mem window */
404 	unsigned int	pref_64_window:1;	/* Pref mem window is 64-bit */
405 	unsigned int	multifunction:1;	/* Multi-function device */
407 	unsigned int	is_busmaster:1;		/* Is busmaster */
408 	unsigned int	no_msi:1;		/* May not use MSI */
409 	unsigned int	no_64bit_msi:1;		/* May only use 32-bit MSIs */
410 	unsigned int	block_cfg_access:1;	/* Config space access blocked */
411 	unsigned int	broken_parity_status:1;	/* Generates false positive parity */
412 	unsigned int	irq_reroute_variant:2;	/* Needs IRQ rerouting variant */
413 	unsigned int	msi_enabled:1;
414 	unsigned int	msix_enabled:1;
415 	unsigned int	ari_enabled:1;		/* ARI forwarding */
416 	unsigned int	ats_enabled:1;		/* Address Translation Svc */
417 	unsigned int	pasid_enabled:1;	/* Process Address Space ID */
418 	unsigned int	pri_enabled:1;		/* Page Request Interface */
419 	unsigned int	is_managed:1;
420 	unsigned int	needs_freset:1;		/* Requires fundamental reset */
421 	unsigned int	state_saved:1;
422 	unsigned int	is_physfn:1;
423 	unsigned int	is_virtfn:1;
424 	unsigned int	reset_fn:1;
425 	unsigned int	is_hotplug_bridge:1;
426 	unsigned int	shpc_managed:1;		/* SHPC owned by shpchp */
450 	pci_dev_flags_t dev_flags;  argument
451 	atomic_t	enable_cnt;	/* pci_enable_device has been called */
453 	u32		saved_config_space[16]; /* Config space saved at suspend time */
454 	struct hlist_head saved_cap_space;
455 	struct bin_attribute *rom_attr;		/* Attribute descriptor for sysfs ROM entry */
456 	int		rom_attr_enabled;	/* Display of ROM attribute enabled? */
480 		struct pci_dev		*physfn;	/* VF: related PF */  argument
505 static inline struct pci_dev *pci_physfn(struct pci_dev *dev)  in pci_physfn()  argument
688 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev)  in pci_dev_msi_enabled()
693 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; }  in pci_dev_msi_enabled()