Lines Matching +full:0 +full:x20
38 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0,
39 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1,
40 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2,
41 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3,
42 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13,
43 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14,
44 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c,
45 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d,
46 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4,
47 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5,
48 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7,
49 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc,
50 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10,
51 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11,
52 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12,
53 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8,
54 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9,
55 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15,
56 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19,
57 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a,
58 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b,
59 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f,
60 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa,
61 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb,
62 MLX5_EVENT_TYPE_CODING_FPGA_ERROR = 0x20,
63 MLX5_EVENT_TYPE_CODING_FPGA_QP_ERROR = 0x21
67 MLX5_MODIFY_TIR_BITMASK_LRO = 0x0,
68 MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE = 0x1,
69 MLX5_MODIFY_TIR_BITMASK_HASH = 0x2,
70 MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN = 0x3
74 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0,
75 MLX5_SET_HCA_CAP_OP_MOD_ODP = 0x2,
76 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3,
77 MLX5_SET_HCA_CAP_OP_MOD_ROCE = 0x4,
81 MLX5_SHARED_RESOURCE_UID = 0xffff,
85 MLX5_OBJ_TYPE_SW_ICM = 0x0008,
95 MLX5_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b,
96 MLX5_OBJ_TYPE_VIRTIO_NET_Q = 0x000d,
97 MLX5_OBJ_TYPE_MKEY = 0xff01,
98 MLX5_OBJ_TYPE_QP = 0xff02,
99 MLX5_OBJ_TYPE_PSV = 0xff03,
100 MLX5_OBJ_TYPE_RMP = 0xff04,
101 MLX5_OBJ_TYPE_XRC_SRQ = 0xff05,
102 MLX5_OBJ_TYPE_RQ = 0xff06,
103 MLX5_OBJ_TYPE_SQ = 0xff07,
104 MLX5_OBJ_TYPE_TIR = 0xff08,
105 MLX5_OBJ_TYPE_TIS = 0xff09,
106 MLX5_OBJ_TYPE_DCT = 0xff0a,
107 MLX5_OBJ_TYPE_XRQ = 0xff0b,
108 MLX5_OBJ_TYPE_RQT = 0xff0e,
109 MLX5_OBJ_TYPE_FLOW_COUNTER = 0xff0f,
110 MLX5_OBJ_TYPE_CQ = 0xff10,
114 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100,
115 MLX5_CMD_OP_QUERY_ADAPTER = 0x101,
116 MLX5_CMD_OP_INIT_HCA = 0x102,
117 MLX5_CMD_OP_TEARDOWN_HCA = 0x103,
118 MLX5_CMD_OP_ENABLE_HCA = 0x104,
119 MLX5_CMD_OP_DISABLE_HCA = 0x105,
120 MLX5_CMD_OP_QUERY_PAGES = 0x107,
121 MLX5_CMD_OP_MANAGE_PAGES = 0x108,
122 MLX5_CMD_OP_SET_HCA_CAP = 0x109,
123 MLX5_CMD_OP_QUERY_ISSI = 0x10a,
124 MLX5_CMD_OP_SET_ISSI = 0x10b,
125 MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d,
126 MLX5_CMD_OP_QUERY_SF_PARTITION = 0x111,
127 MLX5_CMD_OP_ALLOC_SF = 0x113,
128 MLX5_CMD_OP_DEALLOC_SF = 0x114,
129 MLX5_CMD_OP_CREATE_MKEY = 0x200,
130 MLX5_CMD_OP_QUERY_MKEY = 0x201,
131 MLX5_CMD_OP_DESTROY_MKEY = 0x202,
132 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203,
133 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204,
134 MLX5_CMD_OP_ALLOC_MEMIC = 0x205,
135 MLX5_CMD_OP_DEALLOC_MEMIC = 0x206,
136 MLX5_CMD_OP_CREATE_EQ = 0x301,
137 MLX5_CMD_OP_DESTROY_EQ = 0x302,
138 MLX5_CMD_OP_QUERY_EQ = 0x303,
139 MLX5_CMD_OP_GEN_EQE = 0x304,
140 MLX5_CMD_OP_CREATE_CQ = 0x400,
141 MLX5_CMD_OP_DESTROY_CQ = 0x401,
142 MLX5_CMD_OP_QUERY_CQ = 0x402,
143 MLX5_CMD_OP_MODIFY_CQ = 0x403,
144 MLX5_CMD_OP_CREATE_QP = 0x500,
145 MLX5_CMD_OP_DESTROY_QP = 0x501,
146 MLX5_CMD_OP_RST2INIT_QP = 0x502,
147 MLX5_CMD_OP_INIT2RTR_QP = 0x503,
148 MLX5_CMD_OP_RTR2RTS_QP = 0x504,
149 MLX5_CMD_OP_RTS2RTS_QP = 0x505,
150 MLX5_CMD_OP_SQERR2RTS_QP = 0x506,
151 MLX5_CMD_OP_2ERR_QP = 0x507,
152 MLX5_CMD_OP_2RST_QP = 0x50a,
153 MLX5_CMD_OP_QUERY_QP = 0x50b,
154 MLX5_CMD_OP_SQD_RTS_QP = 0x50c,
155 MLX5_CMD_OP_INIT2INIT_QP = 0x50e,
156 MLX5_CMD_OP_CREATE_PSV = 0x600,
157 MLX5_CMD_OP_DESTROY_PSV = 0x601,
158 MLX5_CMD_OP_CREATE_SRQ = 0x700,
159 MLX5_CMD_OP_DESTROY_SRQ = 0x701,
160 MLX5_CMD_OP_QUERY_SRQ = 0x702,
161 MLX5_CMD_OP_ARM_RQ = 0x703,
162 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705,
163 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706,
164 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707,
165 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708,
166 MLX5_CMD_OP_CREATE_DCT = 0x710,
167 MLX5_CMD_OP_DESTROY_DCT = 0x711,
168 MLX5_CMD_OP_DRAIN_DCT = 0x712,
169 MLX5_CMD_OP_QUERY_DCT = 0x713,
170 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714,
171 MLX5_CMD_OP_CREATE_XRQ = 0x717,
172 MLX5_CMD_OP_DESTROY_XRQ = 0x718,
173 MLX5_CMD_OP_QUERY_XRQ = 0x719,
174 MLX5_CMD_OP_ARM_XRQ = 0x71a,
175 MLX5_CMD_OP_QUERY_XRQ_DC_PARAMS_ENTRY = 0x725,
176 MLX5_CMD_OP_SET_XRQ_DC_PARAMS_ENTRY = 0x726,
177 MLX5_CMD_OP_QUERY_XRQ_ERROR_PARAMS = 0x727,
178 MLX5_CMD_OP_RELEASE_XRQ_ERROR = 0x729,
179 MLX5_CMD_OP_MODIFY_XRQ = 0x72a,
180 MLX5_CMD_OP_QUERY_ESW_FUNCTIONS = 0x740,
181 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750,
182 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751,
183 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752,
184 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753,
185 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754,
186 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755,
187 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760,
188 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761,
189 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762,
190 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763,
191 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764,
192 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765,
193 MLX5_CMD_OP_QUERY_VNIC_ENV = 0x76f,
194 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770,
195 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771,
196 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772,
197 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773,
198 MLX5_CMD_OP_SET_MONITOR_COUNTER = 0x774,
199 MLX5_CMD_OP_ARM_MONITOR_COUNTER = 0x775,
200 MLX5_CMD_OP_SET_PP_RATE_LIMIT = 0x780,
201 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781,
202 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782,
203 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783,
204 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784,
205 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785,
206 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786,
207 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787,
208 MLX5_CMD_OP_ALLOC_PD = 0x800,
209 MLX5_CMD_OP_DEALLOC_PD = 0x801,
210 MLX5_CMD_OP_ALLOC_UAR = 0x802,
211 MLX5_CMD_OP_DEALLOC_UAR = 0x803,
212 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804,
213 MLX5_CMD_OP_ACCESS_REG = 0x805,
214 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806,
215 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807,
216 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a,
217 MLX5_CMD_OP_MAD_IFC = 0x50d,
218 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b,
219 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c,
220 MLX5_CMD_OP_NOP = 0x80d,
221 MLX5_CMD_OP_ALLOC_XRCD = 0x80e,
222 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f,
223 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816,
224 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817,
225 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822,
226 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823,
227 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824,
228 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825,
229 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826,
230 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827,
231 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828,
232 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829,
233 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a,
234 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b,
235 MLX5_CMD_OP_SET_WOL_ROL = 0x830,
236 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831,
237 MLX5_CMD_OP_CREATE_LAG = 0x840,
238 MLX5_CMD_OP_MODIFY_LAG = 0x841,
239 MLX5_CMD_OP_QUERY_LAG = 0x842,
240 MLX5_CMD_OP_DESTROY_LAG = 0x843,
241 MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844,
242 MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845,
243 MLX5_CMD_OP_CREATE_TIR = 0x900,
244 MLX5_CMD_OP_MODIFY_TIR = 0x901,
245 MLX5_CMD_OP_DESTROY_TIR = 0x902,
246 MLX5_CMD_OP_QUERY_TIR = 0x903,
247 MLX5_CMD_OP_CREATE_SQ = 0x904,
248 MLX5_CMD_OP_MODIFY_SQ = 0x905,
249 MLX5_CMD_OP_DESTROY_SQ = 0x906,
250 MLX5_CMD_OP_QUERY_SQ = 0x907,
251 MLX5_CMD_OP_CREATE_RQ = 0x908,
252 MLX5_CMD_OP_MODIFY_RQ = 0x909,
253 MLX5_CMD_OP_SET_DELAY_DROP_PARAMS = 0x910,
254 MLX5_CMD_OP_DESTROY_RQ = 0x90a,
255 MLX5_CMD_OP_QUERY_RQ = 0x90b,
256 MLX5_CMD_OP_CREATE_RMP = 0x90c,
257 MLX5_CMD_OP_MODIFY_RMP = 0x90d,
258 MLX5_CMD_OP_DESTROY_RMP = 0x90e,
259 MLX5_CMD_OP_QUERY_RMP = 0x90f,
260 MLX5_CMD_OP_CREATE_TIS = 0x912,
261 MLX5_CMD_OP_MODIFY_TIS = 0x913,
262 MLX5_CMD_OP_DESTROY_TIS = 0x914,
263 MLX5_CMD_OP_QUERY_TIS = 0x915,
264 MLX5_CMD_OP_CREATE_RQT = 0x916,
265 MLX5_CMD_OP_MODIFY_RQT = 0x917,
266 MLX5_CMD_OP_DESTROY_RQT = 0x918,
267 MLX5_CMD_OP_QUERY_RQT = 0x919,
268 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f,
269 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930,
270 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931,
271 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932,
272 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933,
273 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934,
274 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935,
275 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936,
276 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937,
277 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938,
278 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939,
279 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a,
280 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b,
281 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c,
282 MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT = 0x93d,
283 MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT = 0x93e,
284 MLX5_CMD_OP_QUERY_PACKET_REFORMAT_CONTEXT = 0x93f,
285 MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT = 0x940,
286 MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941,
287 MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT = 0x942,
288 MLX5_CMD_OP_FPGA_CREATE_QP = 0x960,
289 MLX5_CMD_OP_FPGA_MODIFY_QP = 0x961,
290 MLX5_CMD_OP_FPGA_QUERY_QP = 0x962,
291 MLX5_CMD_OP_FPGA_DESTROY_QP = 0x963,
292 MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS = 0x964,
293 MLX5_CMD_OP_CREATE_GENERAL_OBJECT = 0xa00,
294 MLX5_CMD_OP_MODIFY_GENERAL_OBJECT = 0xa01,
295 MLX5_CMD_OP_QUERY_GENERAL_OBJECT = 0xa02,
296 MLX5_CMD_OP_DESTROY_GENERAL_OBJECT = 0xa03,
297 MLX5_CMD_OP_CREATE_UCTX = 0xa04,
298 MLX5_CMD_OP_DESTROY_UCTX = 0xa06,
299 MLX5_CMD_OP_CREATE_UMEM = 0xa08,
300 MLX5_CMD_OP_DESTROY_UMEM = 0xa0a,
301 MLX5_CMD_OP_SYNC_STEERING = 0xb00,
307 MLX5_CMD_OP_GENERAL_START = 0xb00,
308 MLX5_CMD_OP_GENERAL_END = 0xd00,
312 u8 outer_dmac[0x1];
313 u8 outer_smac[0x1];
314 u8 outer_ether_type[0x1];
315 u8 outer_ip_version[0x1];
316 u8 outer_first_prio[0x1];
317 u8 outer_first_cfi[0x1];
318 u8 outer_first_vid[0x1];
319 u8 outer_ipv4_ttl[0x1];
320 u8 outer_second_prio[0x1];
321 u8 outer_second_cfi[0x1];
322 u8 outer_second_vid[0x1];
323 u8 reserved_at_b[0x1];
324 u8 outer_sip[0x1];
325 u8 outer_dip[0x1];
326 u8 outer_frag[0x1];
327 u8 outer_ip_protocol[0x1];
328 u8 outer_ip_ecn[0x1];
329 u8 outer_ip_dscp[0x1];
330 u8 outer_udp_sport[0x1];
331 u8 outer_udp_dport[0x1];
332 u8 outer_tcp_sport[0x1];
333 u8 outer_tcp_dport[0x1];
334 u8 outer_tcp_flags[0x1];
335 u8 outer_gre_protocol[0x1];
336 u8 outer_gre_key[0x1];
337 u8 outer_vxlan_vni[0x1];
338 u8 outer_geneve_vni[0x1];
339 u8 outer_geneve_oam[0x1];
340 u8 outer_geneve_protocol_type[0x1];
341 u8 outer_geneve_opt_len[0x1];
342 u8 reserved_at_1e[0x1];
343 u8 source_eswitch_port[0x1];
345 u8 inner_dmac[0x1];
346 u8 inner_smac[0x1];
347 u8 inner_ether_type[0x1];
348 u8 inner_ip_version[0x1];
349 u8 inner_first_prio[0x1];
350 u8 inner_first_cfi[0x1];
351 u8 inner_first_vid[0x1];
352 u8 reserved_at_27[0x1];
353 u8 inner_second_prio[0x1];
354 u8 inner_second_cfi[0x1];
355 u8 inner_second_vid[0x1];
356 u8 reserved_at_2b[0x1];
357 u8 inner_sip[0x1];
358 u8 inner_dip[0x1];
359 u8 inner_frag[0x1];
360 u8 inner_ip_protocol[0x1];
361 u8 inner_ip_ecn[0x1];
362 u8 inner_ip_dscp[0x1];
363 u8 inner_udp_sport[0x1];
364 u8 inner_udp_dport[0x1];
365 u8 inner_tcp_sport[0x1];
366 u8 inner_tcp_dport[0x1];
367 u8 inner_tcp_flags[0x1];
368 u8 reserved_at_37[0x9];
370 u8 geneve_tlv_option_0_data[0x1];
371 u8 reserved_at_41[0x4];
372 u8 outer_first_mpls_over_udp[0x4];
373 u8 outer_first_mpls_over_gre[0x4];
374 u8 inner_first_mpls[0x4];
375 u8 outer_first_mpls[0x4];
376 u8 reserved_at_55[0x2];
377 u8 outer_esp_spi[0x1];
378 u8 reserved_at_58[0x2];
379 u8 bth_dst_qp[0x1];
380 u8 reserved_at_5b[0x5];
382 u8 reserved_at_60[0x18];
383 u8 metadata_reg_c_7[0x1];
384 u8 metadata_reg_c_6[0x1];
385 u8 metadata_reg_c_5[0x1];
386 u8 metadata_reg_c_4[0x1];
387 u8 metadata_reg_c_3[0x1];
388 u8 metadata_reg_c_2[0x1];
389 u8 metadata_reg_c_1[0x1];
390 u8 metadata_reg_c_0[0x1];
394 u8 ft_support[0x1];
395 u8 reserved_at_1[0x1];
396 u8 flow_counter[0x1];
397 u8 flow_modify_en[0x1];
398 u8 modify_root[0x1];
399 u8 identified_miss_table_mode[0x1];
400 u8 flow_table_modify[0x1];
401 u8 reformat[0x1];
402 u8 decap[0x1];
403 u8 reserved_at_9[0x1];
404 u8 pop_vlan[0x1];
405 u8 push_vlan[0x1];
406 u8 reserved_at_c[0x1];
407 u8 pop_vlan_2[0x1];
408 u8 push_vlan_2[0x1];
409 u8 reformat_and_vlan_action[0x1];
410 u8 reserved_at_10[0x1];
411 u8 sw_owner[0x1];
412 u8 reformat_l3_tunnel_to_l2[0x1];
413 u8 reformat_l2_to_l3_tunnel[0x1];
414 u8 reformat_and_modify_action[0x1];
415 u8 ignore_flow_level[0x1];
416 u8 reserved_at_16[0x1];
417 u8 table_miss_action_domain[0x1];
418 u8 termination_table[0x1];
419 u8 reformat_and_fwd_to_table[0x1];
420 u8 reserved_at_1a[0x2];
421 u8 ipsec_encrypt[0x1];
422 u8 ipsec_decrypt[0x1];
423 u8 sw_owner_v2[0x1];
424 u8 reserved_at_1f[0x1];
426 u8 termination_table_raw_traffic[0x1];
427 u8 reserved_at_21[0x1];
428 u8 log_max_ft_size[0x6];
429 u8 log_max_modify_header_context[0x8];
430 u8 max_modify_header_actions[0x8];
431 u8 max_ft_level[0x8];
433 u8 reserved_at_40[0x20];
435 u8 reserved_at_60[0x18];
436 u8 log_max_ft_num[0x8];
438 u8 reserved_at_80[0x18];
439 u8 log_max_destination[0x8];
441 u8 log_max_flow_counter[0x8];
442 u8 reserved_at_a8[0x10];
443 u8 log_max_flow[0x8];
445 u8 reserved_at_c0[0x40];
453 u8 send[0x1];
454 u8 receive[0x1];
455 u8 write[0x1];
456 u8 read[0x1];
457 u8 atomic[0x1];
458 u8 srq_receive[0x1];
459 u8 reserved_at_6[0x1a];
463 u8 smac_47_16[0x20];
465 u8 smac_15_0[0x10];
466 u8 ethertype[0x10];
468 u8 dmac_47_16[0x20];
470 u8 dmac_15_0[0x10];
471 u8 first_prio[0x3];
472 u8 first_cfi[0x1];
473 u8 first_vid[0xc];
475 u8 ip_protocol[0x8];
476 u8 ip_dscp[0x6];
477 u8 ip_ecn[0x2];
478 u8 cvlan_tag[0x1];
479 u8 svlan_tag[0x1];
480 u8 frag[0x1];
481 u8 ip_version[0x4];
482 u8 tcp_flags[0x9];
484 u8 tcp_sport[0x10];
485 u8 tcp_dport[0x10];
487 u8 reserved_at_c0[0x18];
488 u8 ttl_hoplimit[0x8];
490 u8 udp_sport[0x10];
491 u8 udp_dport[0x10];
499 u8 hi[0x18];
500 u8 lo[0x8];
505 u8 key[0x20];
509 u8 gre_c_present[0x1];
510 u8 reserved_at_1[0x1];
511 u8 gre_k_present[0x1];
512 u8 gre_s_present[0x1];
513 u8 source_vhca_port[0x4];
514 u8 source_sqn[0x18];
516 u8 source_eswitch_owner_vhca_id[0x10];
517 u8 source_port[0x10];
519 u8 outer_second_prio[0x3];
520 u8 outer_second_cfi[0x1];
521 u8 outer_second_vid[0xc];
522 u8 inner_second_prio[0x3];
523 u8 inner_second_cfi[0x1];
524 u8 inner_second_vid[0xc];
526 u8 outer_second_cvlan_tag[0x1];
527 u8 inner_second_cvlan_tag[0x1];
528 u8 outer_second_svlan_tag[0x1];
529 u8 inner_second_svlan_tag[0x1];
530 u8 reserved_at_64[0xc];
531 u8 gre_protocol[0x10];
535 u8 vxlan_vni[0x18];
536 u8 reserved_at_b8[0x8];
538 u8 geneve_vni[0x18];
539 u8 reserved_at_d8[0x7];
540 u8 geneve_oam[0x1];
542 u8 reserved_at_e0[0xc];
543 u8 outer_ipv6_flow_label[0x14];
545 u8 reserved_at_100[0xc];
546 u8 inner_ipv6_flow_label[0x14];
548 u8 reserved_at_120[0xa];
549 u8 geneve_opt_len[0x6];
550 u8 geneve_protocol_type[0x10];
552 u8 reserved_at_140[0x8];
553 u8 bth_dst_qp[0x18];
554 u8 reserved_at_160[0x20];
555 u8 outer_esp_spi[0x20];
556 u8 reserved_at_1a0[0x60];
560 u8 mpls_label[0x14];
561 u8 mpls_exp[0x3];
562 u8 mpls_s_bos[0x1];
563 u8 mpls_ttl[0x8];
575 u8 metadata_reg_c_7[0x20];
577 u8 metadata_reg_c_6[0x20];
579 u8 metadata_reg_c_5[0x20];
581 u8 metadata_reg_c_4[0x20];
583 u8 metadata_reg_c_3[0x20];
585 u8 metadata_reg_c_2[0x20];
587 u8 metadata_reg_c_1[0x20];
589 u8 metadata_reg_c_0[0x20];
591 u8 metadata_reg_a[0x20];
593 u8 reserved_at_1a0[0x60];
597 u8 inner_tcp_seq_num[0x20];
599 u8 outer_tcp_seq_num[0x20];
601 u8 inner_tcp_ack_num[0x20];
603 u8 outer_tcp_ack_num[0x20];
605 u8 reserved_at_80[0x8];
606 u8 outer_vxlan_gpe_vni[0x18];
608 u8 outer_vxlan_gpe_next_protocol[0x8];
609 u8 outer_vxlan_gpe_flags[0x8];
610 u8 reserved_at_b0[0x10];
612 u8 icmp_header_data[0x20];
614 u8 icmpv6_header_data[0x20];
616 u8 icmp_type[0x8];
617 u8 icmp_code[0x8];
618 u8 icmpv6_type[0x8];
619 u8 icmpv6_code[0x8];
621 u8 geneve_tlv_option_0_data[0x20];
623 u8 reserved_at_140[0xc0];
627 u8 pa_h[0x20];
629 u8 pa_l[0x14];
630 u8 reserved_at_34[0xc];
634 u8 hi[0x20];
636 u8 lo[0x20];
640 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0,
641 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7,
642 MLX5_ADS_STAT_RATE_10GBPS = 0x8,
643 MLX5_ADS_STAT_RATE_30GBPS = 0x9,
644 MLX5_ADS_STAT_RATE_5GBPS = 0xa,
645 MLX5_ADS_STAT_RATE_20GBPS = 0xb,
646 MLX5_ADS_STAT_RATE_40GBPS = 0xc,
647 MLX5_ADS_STAT_RATE_60GBPS = 0xd,
648 MLX5_ADS_STAT_RATE_80GBPS = 0xe,
649 MLX5_ADS_STAT_RATE_120GBPS = 0xf,
653 u8 fl[0x1];
654 u8 free_ar[0x1];
655 u8 reserved_at_2[0xe];
656 u8 pkey_index[0x10];
658 u8 reserved_at_20[0x8];
659 u8 grh[0x1];
660 u8 mlid[0x7];
661 u8 rlid[0x10];
663 u8 ack_timeout[0x5];
664 u8 reserved_at_45[0x3];
665 u8 src_addr_index[0x8];
666 u8 reserved_at_50[0x4];
667 u8 stat_rate[0x4];
668 u8 hop_limit[0x8];
670 u8 reserved_at_60[0x4];
671 u8 tclass[0x8];
672 u8 flow_label[0x14];
674 u8 rgid_rip[16][0x8];
676 u8 reserved_at_100[0x4];
677 u8 f_dscp[0x1];
678 u8 f_ecn[0x1];
679 u8 reserved_at_106[0x1];
680 u8 f_eth_prio[0x1];
681 u8 ecn[0x2];
682 u8 dscp[0x6];
683 u8 udp_sport[0x10];
685 u8 dei_cfi[0x1];
686 u8 eth_prio[0x3];
687 u8 sl[0x4];
688 u8 vhca_port_num[0x8];
689 u8 rmac_47_32[0x10];
691 u8 rmac_31_0[0x20];
695 u8 nic_rx_multi_path_tirs[0x1];
696 u8 nic_rx_multi_path_tirs_fts[0x1];
697 u8 allow_sniffer_and_nic_rx_shared_tir[0x1];
698 u8 reserved_at_3[0x4];
699 u8 sw_owner_reformat_supported[0x1];
700 u8 reserved_at_8[0x18];
702 u8 encap_general_header[0x1];
703 u8 reserved_at_21[0xa];
704 u8 log_max_packet_reformat_context[0x5];
705 u8 reserved_at_30[0x6];
706 u8 max_encap_header_size[0xa];
707 u8 reserved_at_40[0x1c0];
721 u8 reserved_at_e00[0x1200];
723 u8 sw_steering_nic_rx_action_drop_icm_address[0x40];
725 u8 sw_steering_nic_tx_action_drop_icm_address[0x40];
727 u8 sw_steering_nic_tx_action_allow_icm_address[0x40];
729 u8 reserved_at_20c0[0x5f40];
733 MLX5_FDB_TO_VPORT_REG_C_0 = 0x01,
734 MLX5_FDB_TO_VPORT_REG_C_1 = 0x02,
735 MLX5_FDB_TO_VPORT_REG_C_2 = 0x04,
736 MLX5_FDB_TO_VPORT_REG_C_3 = 0x08,
737 MLX5_FDB_TO_VPORT_REG_C_4 = 0x10,
738 MLX5_FDB_TO_VPORT_REG_C_5 = 0x20,
739 MLX5_FDB_TO_VPORT_REG_C_6 = 0x40,
740 MLX5_FDB_TO_VPORT_REG_C_7 = 0x80,
744 u8 fdb_to_vport_reg_c_id[0x8];
745 u8 reserved_at_8[0xd];
746 u8 fdb_modify_header_fwd_to_table[0x1];
747 u8 reserved_at_16[0x1];
748 u8 flow_source[0x1];
749 u8 reserved_at_18[0x2];
750 u8 multi_fdb_encap[0x1];
751 u8 egress_acl_forward_to_vport[0x1];
752 u8 fdb_multi_path_to_table[0x1];
753 u8 reserved_at_1d[0x3];
755 u8 reserved_at_20[0x1e0];
763 u8 reserved_at_800[0x1000];
765 u8 sw_steering_fdb_action_drop_icm_address_rx[0x40];
767 u8 sw_steering_fdb_action_drop_icm_address_tx[0x40];
769 u8 sw_steering_uplink_icm_address_rx[0x40];
771 u8 sw_steering_uplink_icm_address_tx[0x40];
773 u8 reserved_at_1900[0x6700];
777 MLX5_COUNTER_SOURCE_ESWITCH = 0x0,
778 MLX5_COUNTER_FLOW_ESWITCH = 0x1,
782 u8 vport_svlan_strip[0x1];
783 u8 vport_cvlan_strip[0x1];
784 u8 vport_svlan_insert[0x1];
785 u8 vport_cvlan_insert_if_not_exist[0x1];
786 u8 vport_cvlan_insert_overwrite[0x1];
787 u8 reserved_at_5[0x3];
788 u8 esw_uplink_ingress_acl[0x1];
789 u8 reserved_at_9[0x10];
790 u8 esw_functions_changed[0x1];
791 u8 reserved_at_1a[0x1];
792 u8 ecpf_vport_exists[0x1];
793 u8 counter_eswitch_affinity[0x1];
794 u8 merged_eswitch[0x1];
795 u8 nic_vport_node_guid_modify[0x1];
796 u8 nic_vport_port_guid_modify[0x1];
798 u8 vxlan_encap_decap[0x1];
799 u8 nvgre_encap_decap[0x1];
800 u8 reserved_at_22[0x1];
801 u8 log_max_fdb_encap_uplink[0x5];
802 u8 reserved_at_21[0x3];
803 u8 log_max_packet_reformat_context[0x5];
804 u8 reserved_2b[0x6];
805 u8 max_encap_header_size[0xa];
807 u8 reserved_at_40[0xb];
808 u8 log_max_esw_sf[0x5];
809 u8 esw_sf_base_id[0x10];
811 u8 reserved_at_60[0x7a0];
816 u8 packet_pacing[0x1];
817 u8 esw_scheduling[0x1];
818 u8 esw_bw_share[0x1];
819 u8 esw_rate_limit[0x1];
820 u8 reserved_at_4[0x1];
821 u8 packet_pacing_burst_bound[0x1];
822 u8 packet_pacing_typical_size[0x1];
823 u8 reserved_at_7[0x4];
824 u8 packet_pacing_uid[0x1];
825 u8 reserved_at_c[0x14];
827 u8 reserved_at_20[0x20];
829 u8 packet_pacing_max_rate[0x20];
831 u8 packet_pacing_min_rate[0x20];
833 u8 reserved_at_80[0x10];
834 u8 packet_pacing_rate_table_size[0x10];
836 u8 esw_element_type[0x10];
837 u8 esw_tsar_type[0x10];
839 u8 reserved_at_c0[0x10];
840 u8 max_qos_para_vport[0x10];
842 u8 max_tsar_bw_share[0x20];
844 u8 reserved_at_100[0x700];
848 u8 core_dump_general[0x1];
849 u8 core_dump_qp[0x1];
850 u8 reserved_at_2[0x7];
851 u8 resource_dump[0x1];
852 u8 reserved_at_a[0x16];
854 u8 reserved_at_20[0x2];
855 u8 stall_detect[0x1];
856 u8 reserved_at_23[0x1d];
858 u8 reserved_at_40[0x7c0];
862 u8 csum_cap[0x1];
863 u8 vlan_cap[0x1];
864 u8 lro_cap[0x1];
865 u8 lro_psh_flag[0x1];
866 u8 lro_time_stamp[0x1];
867 u8 reserved_at_5[0x2];
868 u8 wqe_vlan_insert[0x1];
869 u8 self_lb_en_modifiable[0x1];
870 u8 reserved_at_9[0x2];
871 u8 max_lso_cap[0x5];
872 u8 multi_pkt_send_wqe[0x2];
873 u8 wqe_inline_mode[0x2];
874 u8 rss_ind_tbl_cap[0x4];
875 u8 reg_umr_sq[0x1];
876 u8 scatter_fcs[0x1];
877 u8 enhanced_multi_pkt_send_wqe[0x1];
878 u8 tunnel_lso_const_out_ip_id[0x1];
879 u8 reserved_at_1c[0x2];
880 u8 tunnel_stateless_gre[0x1];
881 u8 tunnel_stateless_vxlan[0x1];
883 u8 swp[0x1];
884 u8 swp_csum[0x1];
885 u8 swp_lso[0x1];
886 u8 cqe_checksum_full[0x1];
887 u8 tunnel_stateless_geneve_tx[0x1];
888 u8 tunnel_stateless_mpls_over_udp[0x1];
889 u8 tunnel_stateless_mpls_over_gre[0x1];
890 u8 tunnel_stateless_vxlan_gpe[0x1];
891 u8 tunnel_stateless_ipv4_over_vxlan[0x1];
892 u8 tunnel_stateless_ip_over_ip[0x1];
893 u8 insert_trailer[0x1];
894 u8 reserved_at_2b[0x5];
895 u8 max_vxlan_udp_ports[0x8];
896 u8 reserved_at_38[0x6];
897 u8 max_geneve_opt_len[0x1];
898 u8 tunnel_stateless_geneve_rx[0x1];
900 u8 reserved_at_40[0x10];
901 u8 lro_min_mss_size[0x10];
903 u8 reserved_at_60[0x120];
905 u8 lro_timer_supported_periods[4][0x20];
907 u8 reserved_at_200[0x600];
911 u8 roce_apm[0x1];
912 u8 reserved_at_1[0x3];
913 u8 sw_r_roce_src_udp_port[0x1];
914 u8 reserved_at_5[0x1b];
916 u8 reserved_at_20[0x60];
918 u8 reserved_at_80[0xc];
919 u8 l3_type[0x4];
920 u8 reserved_at_90[0x8];
921 u8 roce_version[0x8];
923 u8 reserved_at_a0[0x10];
924 u8 r_roce_dest_udp_port[0x10];
926 u8 r_roce_max_src_udp_port[0x10];
927 u8 r_roce_min_src_udp_port[0x10];
929 u8 reserved_at_e0[0x10];
930 u8 roce_address_table_size[0x10];
932 u8 reserved_at_100[0x700];
936 u8 opcode[0x10];
937 u8 uid[0x10];
939 u8 reserved_at_20[0x10];
940 u8 op_mod[0x10];
942 u8 reserved_at_40[0xc0];
946 u8 status[0x8];
947 u8 reserved_at_8[0x18];
949 u8 syndrome[0x20];
951 u8 reserved_at_40[0x40];
955 u8 memic[0x1];
956 u8 reserved_at_1[0x1f];
958 u8 reserved_at_20[0xb];
959 u8 log_min_memic_alloc_size[0x5];
960 u8 reserved_at_30[0x8];
961 u8 log_max_memic_addr_alignment[0x8];
963 u8 memic_bar_start_addr[0x40];
965 u8 memic_bar_size[0x20];
967 u8 max_memic_size[0x20];
969 u8 steering_sw_icm_start_address[0x40];
971 u8 reserved_at_100[0x8];
972 u8 log_header_modify_sw_icm_size[0x8];
973 u8 reserved_at_110[0x2];
974 u8 log_sw_icm_alloc_granularity[0x6];
975 u8 log_steering_sw_icm_size[0x8];
977 u8 reserved_at_120[0x20];
979 u8 header_modify_sw_icm_start_address[0x40];
981 u8 reserved_at_180[0x680];
985 u8 user_affiliated_events[4][0x40];
987 u8 user_unaffiliated_events[4][0x40];
991 u8 desc_tunnel_offload_type[0x1];
992 u8 eth_frame_offload_type[0x1];
993 u8 virtio_version_1_0[0x1];
994 u8 device_features_bits_mask[0xd];
995 u8 event_mode[0x8];
996 u8 virtio_queue_type[0x8];
998 u8 max_tunnel_desc[0x10];
999 u8 reserved_at_30[0x3];
1000 u8 log_doorbell_stride[0x5];
1001 u8 reserved_at_38[0x3];
1002 u8 log_doorbell_bar_size[0x5];
1004 u8 doorbell_bar_offset[0x40];
1006 u8 max_emulated_devices[0x8];
1007 u8 max_num_virtio_queues[0x18];
1009 u8 reserved_at_a0[0x60];
1011 u8 umem_1_buffer_param_a[0x20];
1013 u8 umem_1_buffer_param_b[0x20];
1015 u8 umem_2_buffer_param_a[0x20];
1017 u8 umem_2_buffer_param_b[0x20];
1019 u8 umem_3_buffer_param_a[0x20];
1021 u8 umem_3_buffer_param_b[0x20];
1023 u8 reserved_at_1c0[0x640];
1027 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0,
1028 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2,
1029 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4,
1030 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8,
1031 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10,
1032 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20,
1033 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40,
1034 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80,
1035 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100,
1039 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1,
1040 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2,
1041 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4,
1042 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8,
1043 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10,
1044 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20,
1045 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40,
1046 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80,
1047 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100,
1051 u8 reserved_at_0[0x40];
1053 u8 atomic_req_8B_endianness_mode[0x2];
1054 u8 reserved_at_42[0x4];
1055 u8 supported_atomic_req_8B_endianness_mode_1[0x1];
1057 u8 reserved_at_47[0x19];
1059 u8 reserved_at_60[0x20];
1061 u8 reserved_at_80[0x10];
1062 u8 atomic_operations[0x10];
1064 u8 reserved_at_a0[0x10];
1065 u8 atomic_size_qp[0x10];
1067 u8 reserved_at_c0[0x10];
1068 u8 atomic_size_dc[0x10];
1070 u8 reserved_at_e0[0x720];
1074 u8 reserved_at_0[0x40];
1076 u8 sig[0x1];
1077 u8 reserved_at_41[0x1f];
1079 u8 reserved_at_60[0x20];
1091 u8 reserved_at_120[0x6E0];
1095 u8 reserved_at_0[0x10];
1096 u8 reserved_at_10[0x9];
1097 u8 op_swap_endianness[0x1];
1098 u8 op_min[0x1];
1099 u8 op_xor[0x1];
1100 u8 op_or[0x1];
1101 u8 op_and[0x1];
1102 u8 op_max[0x1];
1103 u8 op_add[0x1];
1107 u8 calc_matrix[0x1];
1108 u8 reserved_at_1[0x1f];
1109 u8 reserved_at_20[0x8];
1110 u8 max_vec_count[0x8];
1111 u8 reserved_at_30[0xd];
1112 u8 max_chunk_size[0x3];
1118 u8 reserved_at_c0[0x720];
1122 u8 tls_1_2_aes_gcm_128[0x1];
1123 u8 tls_1_3_aes_gcm_128[0x1];
1124 u8 tls_1_2_aes_gcm_256[0x1];
1125 u8 tls_1_3_aes_gcm_256[0x1];
1126 u8 reserved_at_4[0x1c];
1128 u8 reserved_at_20[0x7e0];
1132 u8 ipsec_full_offload[0x1];
1133 u8 ipsec_crypto_offload[0x1];
1134 u8 ipsec_esn[0x1];
1135 u8 ipsec_crypto_esp_aes_gcm_256_encrypt[0x1];
1136 u8 ipsec_crypto_esp_aes_gcm_128_encrypt[0x1];
1137 u8 ipsec_crypto_esp_aes_gcm_256_decrypt[0x1];
1138 u8 ipsec_crypto_esp_aes_gcm_128_decrypt[0x1];
1139 u8 reserved_at_7[0x4];
1140 u8 log_max_ipsec_offload[0x5];
1141 u8 reserved_at_10[0x10];
1143 u8 min_log_ipsec_full_replay_window[0x8];
1144 u8 max_log_ipsec_full_replay_window[0x8];
1145 u8 reserved_at_30[0x7d0];
1149 MLX5_WQ_TYPE_LINKED_LIST = 0x0,
1150 MLX5_WQ_TYPE_CYCLIC = 0x1,
1151 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2,
1152 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3,
1156 MLX5_WQ_END_PAD_MODE_NONE = 0x0,
1157 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1,
1161 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0,
1162 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1,
1163 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2,
1164 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3,
1165 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4,
1169 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0,
1170 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1,
1171 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2,
1172 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3,
1173 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4,
1174 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5,
1178 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0,
1179 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1,
1183 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0,
1184 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1,
1185 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3,
1189 MLX5_CAP_PORT_TYPE_IB = 0x0,
1190 MLX5_CAP_PORT_TYPE_ETH = 0x1,
1194 MLX5_CAP_UMR_FENCE_STRONG = 0x0,
1195 MLX5_CAP_UMR_FENCE_SMALL = 0x1,
1196 MLX5_CAP_UMR_FENCE_NONE = 0x2,
1207 MLX5_UCTX_CAP_RAW_TX = 1UL << 0,
1214 MLX5_FC_BULK_128 = (1 << 0),
1227 MLX5_STEERING_FORMAT_CONNECTX_5 = 0,
1232 u8 reserved_at_0[0x30];
1233 u8 vhca_id[0x10];
1235 u8 reserved_at_40[0x40];
1237 u8 log_max_srq_sz[0x8];
1238 u8 log_max_qp_sz[0x8];
1239 u8 event_cap[0x1];
1240 u8 reserved_at_91[0x7];
1241 u8 prio_tag_required[0x1];
1242 u8 reserved_at_99[0x2];
1243 u8 log_max_qp[0x5];
1245 u8 reserved_at_a0[0x3];
1246 u8 ece_support[0x1];
1247 u8 reserved_at_a4[0x7];
1248 u8 log_max_srq[0x5];
1249 u8 reserved_at_b0[0x10];
1251 u8 max_sgl_for_optimized_performance[0x8];
1252 u8 log_max_cq_sz[0x8];
1253 u8 relaxed_ordering_write_umr[0x1];
1254 u8 relaxed_ordering_read_umr[0x1];
1255 u8 reserved_at_d2[0x7];
1256 u8 virtio_net_device_emualtion_manager[0x1];
1257 u8 virtio_blk_device_emualtion_manager[0x1];
1258 u8 log_max_cq[0x5];
1260 u8 log_max_eq_sz[0x8];
1261 u8 relaxed_ordering_write[0x1];
1262 u8 relaxed_ordering_read[0x1];
1263 u8 log_max_mkey[0x6];
1264 u8 reserved_at_f0[0x8];
1265 u8 dump_fill_mkey[0x1];
1266 u8 reserved_at_f9[0x2];
1267 u8 fast_teardown[0x1];
1268 u8 log_max_eq[0x4];
1270 u8 max_indirection[0x8];
1271 u8 fixed_buffer_size[0x1];
1272 u8 log_max_mrw_sz[0x7];
1273 u8 force_teardown[0x1];
1274 u8 reserved_at_111[0x1];
1275 u8 log_max_bsf_list_size[0x6];
1276 u8 umr_extended_translation_offset[0x1];
1277 u8 null_mkey[0x1];
1278 u8 log_max_klm_list_size[0x6];
1280 u8 reserved_at_120[0xa];
1281 u8 log_max_ra_req_dc[0x6];
1282 u8 reserved_at_130[0xa];
1283 u8 log_max_ra_res_dc[0x6];
1285 u8 reserved_at_140[0x6];
1286 u8 release_all_pages[0x1];
1287 u8 reserved_at_147[0x2];
1288 u8 roce_accl[0x1];
1289 u8 log_max_ra_req_qp[0x6];
1290 u8 reserved_at_150[0xa];
1291 u8 log_max_ra_res_qp[0x6];
1293 u8 end_pad[0x1];
1294 u8 cc_query_allowed[0x1];
1295 u8 cc_modify_allowed[0x1];
1296 u8 start_pad[0x1];
1297 u8 cache_line_128byte[0x1];
1298 u8 reserved_at_165[0x4];
1299 u8 rts2rts_qp_counters_set_id[0x1];
1300 u8 reserved_at_16a[0x2];
1301 u8 vnic_env_int_rq_oob[0x1];
1302 u8 sbcam_reg[0x1];
1303 u8 reserved_at_16e[0x1];
1304 u8 qcam_reg[0x1];
1305 u8 gid_table_size[0x10];
1307 u8 out_of_seq_cnt[0x1];
1308 u8 vport_counters[0x1];
1309 u8 retransmission_q_counters[0x1];
1310 u8 debug[0x1];
1311 u8 modify_rq_counter_set_id[0x1];
1312 u8 rq_delay_drop[0x1];
1313 u8 max_qp_cnt[0xa];
1314 u8 pkey_table_size[0x10];
1316 u8 vport_group_manager[0x1];
1317 u8 vhca_group_manager[0x1];
1318 u8 ib_virt[0x1];
1319 u8 eth_virt[0x1];
1320 u8 vnic_env_queue_counters[0x1];
1321 u8 ets[0x1];
1322 u8 nic_flow_table[0x1];
1323 u8 eswitch_manager[0x1];
1324 u8 device_memory[0x1];
1325 u8 mcam_reg[0x1];
1326 u8 pcam_reg[0x1];
1327 u8 local_ca_ack_delay[0x5];
1328 u8 port_module_event[0x1];
1329 u8 enhanced_error_q_counters[0x1];
1330 u8 ports_check[0x1];
1331 u8 reserved_at_1b3[0x1];
1332 u8 disable_link_up[0x1];
1333 u8 beacon_led[0x1];
1334 u8 port_type[0x2];
1335 u8 num_ports[0x8];
1337 u8 reserved_at_1c0[0x1];
1338 u8 pps[0x1];
1339 u8 pps_modify[0x1];
1340 u8 log_max_msg[0x5];
1341 u8 reserved_at_1c8[0x4];
1342 u8 max_tc[0x4];
1343 u8 temp_warn_event[0x1];
1344 u8 dcbx[0x1];
1345 u8 general_notification_event[0x1];
1346 u8 reserved_at_1d3[0x2];
1347 u8 fpga[0x1];
1348 u8 rol_s[0x1];
1349 u8 rol_g[0x1];
1350 u8 reserved_at_1d8[0x1];
1351 u8 wol_s[0x1];
1352 u8 wol_g[0x1];
1353 u8 wol_a[0x1];
1354 u8 wol_b[0x1];
1355 u8 wol_m[0x1];
1356 u8 wol_u[0x1];
1357 u8 wol_p[0x1];
1359 u8 stat_rate_support[0x10];
1360 u8 reserved_at_1f0[0x1];
1361 u8 pci_sync_for_fw_update_event[0x1];
1362 u8 reserved_at_1f2[0x6];
1363 u8 init2_lag_tx_port_affinity[0x1];
1364 u8 reserved_at_1fa[0x3];
1365 u8 cqe_version[0x4];
1367 u8 compact_address_vector[0x1];
1368 u8 striding_rq[0x1];
1369 u8 reserved_at_202[0x1];
1370 u8 ipoib_enhanced_offloads[0x1];
1371 u8 ipoib_basic_offloads[0x1];
1372 u8 reserved_at_205[0x1];
1373 u8 repeated_block_disabled[0x1];
1374 u8 umr_modify_entity_size_disabled[0x1];
1375 u8 umr_modify_atomic_disabled[0x1];
1376 u8 umr_indirect_mkey_disabled[0x1];
1377 u8 umr_fence[0x2];
1378 u8 dc_req_scat_data_cqe[0x1];
1379 u8 reserved_at_20d[0x2];
1380 u8 drain_sigerr[0x1];
1381 u8 cmdif_checksum[0x2];
1382 u8 sigerr_cqe[0x1];
1383 u8 reserved_at_213[0x1];
1384 u8 wq_signature[0x1];
1385 u8 sctr_data_cqe[0x1];
1386 u8 reserved_at_216[0x1];
1387 u8 sho[0x1];
1388 u8 tph[0x1];
1389 u8 rf[0x1];
1390 u8 dct[0x1];
1391 u8 qos[0x1];
1392 u8 eth_net_offloads[0x1];
1393 u8 roce[0x1];
1394 u8 atomic[0x1];
1395 u8 reserved_at_21f[0x1];
1397 u8 cq_oi[0x1];
1398 u8 cq_resize[0x1];
1399 u8 cq_moderation[0x1];
1400 u8 reserved_at_223[0x3];
1401 u8 cq_eq_remap[0x1];
1402 u8 pg[0x1];
1403 u8 block_lb_mc[0x1];
1404 u8 reserved_at_229[0x1];
1405 u8 scqe_break_moderation[0x1];
1406 u8 cq_period_start_from_cqe[0x1];
1407 u8 cd[0x1];
1408 u8 reserved_at_22d[0x1];
1409 u8 apm[0x1];
1410 u8 vector_calc[0x1];
1411 u8 umr_ptr_rlky[0x1];
1412 u8 imaicl[0x1];
1413 u8 qp_packet_based[0x1];
1414 u8 reserved_at_233[0x3];
1415 u8 qkv[0x1];
1416 u8 pkv[0x1];
1417 u8 set_deth_sqpn[0x1];
1418 u8 reserved_at_239[0x3];
1419 u8 xrc[0x1];
1420 u8 ud[0x1];
1421 u8 uc[0x1];
1422 u8 rc[0x1];
1424 u8 uar_4k[0x1];
1425 u8 reserved_at_241[0x9];
1426 u8 uar_sz[0x6];
1427 u8 reserved_at_250[0x8];
1428 u8 log_pg_sz[0x8];
1430 u8 bf[0x1];
1431 u8 driver_version[0x1];
1432 u8 pad_tx_eth_packet[0x1];
1433 u8 reserved_at_263[0x3];
1434 u8 mkey_by_name[0x1];
1435 u8 reserved_at_267[0x4];
1437 u8 log_bf_reg_size[0x5];
1439 u8 reserved_at_270[0x6];
1440 u8 lag_dct[0x2];
1441 u8 lag_tx_port_affinity[0x1];
1442 u8 reserved_at_279[0x2];
1443 u8 lag_master[0x1];
1444 u8 num_lag_ports[0x4];
1446 u8 reserved_at_280[0x10];
1447 u8 max_wqe_sz_sq[0x10];
1449 u8 reserved_at_2a0[0x10];
1450 u8 max_wqe_sz_rq[0x10];
1452 u8 max_flow_counter_31_16[0x10];
1453 u8 max_wqe_sz_sq_dc[0x10];
1455 u8 reserved_at_2e0[0x7];
1456 u8 max_qp_mcg[0x19];
1458 u8 reserved_at_300[0x10];
1459 u8 flow_counter_bulk_alloc[0x8];
1460 u8 log_max_mcg[0x8];
1462 u8 reserved_at_320[0x3];
1463 u8 log_max_transport_domain[0x5];
1464 u8 reserved_at_328[0x3];
1465 u8 log_max_pd[0x5];
1466 u8 reserved_at_330[0xb];
1467 u8 log_max_xrcd[0x5];
1469 u8 nic_receive_steering_discard[0x1];
1470 u8 receive_discard_vport_down[0x1];
1471 u8 transmit_discard_vport_down[0x1];
1472 u8 reserved_at_343[0x5];
1473 u8 log_max_flow_counter_bulk[0x8];
1474 u8 max_flow_counter_15_0[0x10];
1477 u8 reserved_at_360[0x3];
1478 u8 log_max_rq[0x5];
1479 u8 reserved_at_368[0x3];
1480 u8 log_max_sq[0x5];
1481 u8 reserved_at_370[0x3];
1482 u8 log_max_tir[0x5];
1483 u8 reserved_at_378[0x3];
1484 u8 log_max_tis[0x5];
1486 u8 basic_cyclic_rcv_wqe[0x1];
1487 u8 reserved_at_381[0x2];
1488 u8 log_max_rmp[0x5];
1489 u8 reserved_at_388[0x3];
1490 u8 log_max_rqt[0x5];
1491 u8 reserved_at_390[0x3];
1492 u8 log_max_rqt_size[0x5];
1493 u8 reserved_at_398[0x3];
1494 u8 log_max_tis_per_sq[0x5];
1496 u8 ext_stride_num_range[0x1];
1497 u8 reserved_at_3a1[0x2];
1498 u8 log_max_stride_sz_rq[0x5];
1499 u8 reserved_at_3a8[0x3];
1500 u8 log_min_stride_sz_rq[0x5];
1501 u8 reserved_at_3b0[0x3];
1502 u8 log_max_stride_sz_sq[0x5];
1503 u8 reserved_at_3b8[0x3];
1504 u8 log_min_stride_sz_sq[0x5];
1506 u8 hairpin[0x1];
1507 u8 reserved_at_3c1[0x2];
1508 u8 log_max_hairpin_queues[0x5];
1509 u8 reserved_at_3c8[0x3];
1510 u8 log_max_hairpin_wq_data_sz[0x5];
1511 u8 reserved_at_3d0[0x3];
1512 u8 log_max_hairpin_num_packets[0x5];
1513 u8 reserved_at_3d8[0x3];
1514 u8 log_max_wq_sz[0x5];
1516 u8 nic_vport_change_event[0x1];
1517 u8 disable_local_lb_uc[0x1];
1518 u8 disable_local_lb_mc[0x1];
1519 u8 log_min_hairpin_wq_data_sz[0x5];
1520 u8 reserved_at_3e8[0x3];
1521 u8 log_max_vlan_list[0x5];
1522 u8 reserved_at_3f0[0x3];
1523 u8 log_max_current_mc_list[0x5];
1524 u8 reserved_at_3f8[0x3];
1525 u8 log_max_current_uc_list[0x5];
1527 u8 general_obj_types[0x40];
1529 u8 reserved_at_440[0x4];
1530 u8 steering_format_version[0x4];
1531 u8 create_qp_start_hint[0x18];
1533 u8 reserved_at_460[0x3];
1534 u8 log_max_uctx[0x5];
1535 u8 reserved_at_468[0x2];
1536 u8 ipsec_offload[0x1];
1537 u8 log_max_umem[0x5];
1538 u8 max_num_eqs[0x10];
1540 u8 reserved_at_480[0x1];
1541 u8 tls_tx[0x1];
1542 u8 tls_rx[0x1];
1543 u8 log_max_l2_table[0x5];
1544 u8 reserved_at_488[0x8];
1545 u8 log_uar_page_sz[0x10];
1547 u8 reserved_at_4a0[0x20];
1548 u8 device_frequency_mhz[0x20];
1549 u8 device_frequency_khz[0x20];
1551 u8 reserved_at_500[0x20];
1552 u8 num_of_uars_per_page[0x20];
1554 u8 flex_parser_protocols[0x20];
1556 u8 max_geneve_tlv_options[0x8];
1557 u8 reserved_at_568[0x3];
1558 u8 max_geneve_tlv_option_data_len[0x5];
1559 u8 reserved_at_570[0x10];
1561 u8 reserved_at_580[0x33];
1562 u8 log_max_dek[0x5];
1563 u8 reserved_at_5b8[0x4];
1564 u8 mini_cqe_resp_stride_index[0x1];
1565 u8 cqe_128_always[0x1];
1566 u8 cqe_compression_128[0x1];
1567 u8 cqe_compression[0x1];
1569 u8 cqe_compression_timeout[0x10];
1570 u8 cqe_compression_max_num[0x10];
1572 u8 reserved_at_5e0[0x10];
1573 u8 tag_matching[0x1];
1574 u8 rndv_offload_rc[0x1];
1575 u8 rndv_offload_dc[0x1];
1576 u8 log_tag_matching_list_sz[0x5];
1577 u8 reserved_at_5f8[0x3];
1578 u8 log_max_xrq[0x5];
1580 u8 affiliate_nic_vport_criteria[0x8];
1581 u8 native_port_num[0x8];
1582 u8 num_vhca_ports[0x8];
1583 u8 reserved_at_618[0x6];
1584 u8 sw_owner_id[0x1];
1585 u8 reserved_at_61f[0x1];
1587 u8 max_num_of_monitor_counters[0x10];
1588 u8 num_ppcnt_monitor_counters[0x10];
1590 u8 reserved_at_640[0x10];
1591 u8 num_q_monitor_counters[0x10];
1593 u8 reserved_at_660[0x20];
1595 u8 sf[0x1];
1596 u8 sf_set_partition[0x1];
1597 u8 reserved_at_682[0x1];
1598 u8 log_max_sf[0x5];
1599 u8 reserved_at_688[0x8];
1600 u8 log_min_sf_size[0x8];
1601 u8 max_num_sf_partitions[0x8];
1603 u8 uctx_cap[0x20];
1605 u8 reserved_at_6c0[0x4];
1606 u8 flex_parser_id_geneve_tlv_option_0[0x4];
1607 u8 flex_parser_id_icmp_dw1[0x4];
1608 u8 flex_parser_id_icmp_dw0[0x4];
1609 u8 flex_parser_id_icmpv6_dw1[0x4];
1610 u8 flex_parser_id_icmpv6_dw0[0x4];
1611 u8 flex_parser_id_outer_first_mpls_over_gre[0x4];
1612 u8 flex_parser_id_outer_first_mpls_over_udp_label[0x4];
1614 u8 reserved_at_6e0[0x10];
1615 u8 sf_base_id[0x10];
1617 u8 reserved_at_700[0x80];
1618 u8 vhca_tunnel_commands[0x40];
1619 u8 reserved_at_7c0[0x40];
1623 MLX5_FLOW_DESTINATION_TYPE_VPORT = 0x0,
1624 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1,
1625 MLX5_FLOW_DESTINATION_TYPE_TIR = 0x2,
1627 MLX5_FLOW_DESTINATION_TYPE_PORT = 0x99,
1628 MLX5_FLOW_DESTINATION_TYPE_COUNTER = 0x100,
1629 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE_NUM = 0x101,
1639 u8 destination_type[0x8];
1640 u8 destination_id[0x18];
1642 u8 destination_eswitch_owner_vhca_id_valid[0x1];
1643 u8 packet_reformat[0x1];
1644 u8 reserved_at_22[0xe];
1645 u8 destination_eswitch_owner_vhca_id[0x10];
1649 u8 flow_counter_id[0x20];
1651 u8 reserved_at_20[0x20];
1657 u8 packet_reformat_id[0x20];
1659 u8 reserved_at_60[0x20];
1678 u8 reserved_at_a00[0x600];
1682 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0,
1683 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1,
1684 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2,
1685 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3,
1686 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4,
1690 u8 l3_prot_type[0x1];
1691 u8 l4_prot_type[0x1];
1692 u8 selected_fields[0x1e];
1696 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0,
1697 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1,
1701 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0,
1702 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1,
1706 u8 wq_type[0x4];
1707 u8 wq_signature[0x1];
1708 u8 end_padding_mode[0x2];
1709 u8 cd_slave[0x1];
1710 u8 reserved_at_8[0x18];
1712 u8 hds_skip_first_sge[0x1];
1713 u8 log2_hds_buf_size[0x3];
1714 u8 reserved_at_24[0x7];
1715 u8 page_offset[0x5];
1716 u8 lwm[0x10];
1718 u8 reserved_at_40[0x8];
1719 u8 pd[0x18];
1721 u8 reserved_at_60[0x8];
1722 u8 uar_page[0x18];
1724 u8 dbr_addr[0x40];
1726 u8 hw_counter[0x20];
1728 u8 sw_counter[0x20];
1730 u8 reserved_at_100[0xc];
1731 u8 log_wq_stride[0x4];
1732 u8 reserved_at_110[0x3];
1733 u8 log_wq_pg_sz[0x5];
1734 u8 reserved_at_118[0x3];
1735 u8 log_wq_sz[0x5];
1737 u8 dbr_umem_valid[0x1];
1738 u8 wq_umem_valid[0x1];
1739 u8 reserved_at_122[0x1];
1740 u8 log_hairpin_num_packets[0x5];
1741 u8 reserved_at_128[0x3];
1742 u8 log_hairpin_data_sz[0x5];
1744 u8 reserved_at_130[0x4];
1745 u8 log_wqe_num_of_strides[0x4];
1746 u8 two_byte_shift_en[0x1];
1747 u8 reserved_at_139[0x4];
1748 u8 log_wqe_stride_size[0x3];
1750 u8 reserved_at_140[0x4c0];
1756 u8 reserved_at_0[0x8];
1757 u8 rq_num[0x18];
1761 u8 reserved_at_0[0x10];
1762 u8 mac_addr_47_32[0x10];
1764 u8 mac_addr_31_0[0x20];
1768 u8 reserved_at_0[0x14];
1769 u8 vlan[0x0c];
1771 u8 reserved_at_20[0x20];
1775 u8 reserved_at_0[0xa0];
1777 u8 min_time_between_cnps[0x20];
1779 u8 reserved_at_c0[0x12];
1780 u8 cnp_dscp[0x6];
1781 u8 reserved_at_d8[0x4];
1782 u8 cnp_prio_mode[0x1];
1783 u8 cnp_802p_prio[0x3];
1785 u8 reserved_at_e0[0x720];
1789 u8 reserved_at_0[0x60];
1791 u8 reserved_at_60[0x4];
1792 u8 clamp_tgt_rate[0x1];
1793 u8 reserved_at_65[0x3];
1794 u8 clamp_tgt_rate_after_time_inc[0x1];
1795 u8 reserved_at_69[0x17];
1797 u8 reserved_at_80[0x20];
1799 u8 rpg_time_reset[0x20];
1801 u8 rpg_byte_reset[0x20];
1803 u8 rpg_threshold[0x20];
1805 u8 rpg_max_rate[0x20];
1807 u8 rpg_ai_rate[0x20];
1809 u8 rpg_hai_rate[0x20];
1811 u8 rpg_gd[0x20];
1813 u8 rpg_min_dec_fac[0x20];
1815 u8 rpg_min_rate[0x20];
1817 u8 reserved_at_1c0[0xe0];
1819 u8 rate_to_set_on_first_cnp[0x20];
1821 u8 dce_tcp_g[0x20];
1823 u8 dce_tcp_rtt[0x20];
1825 u8 rate_reduce_monitor_period[0x20];
1827 u8 reserved_at_320[0x20];
1829 u8 initial_alpha_value[0x20];
1831 u8 reserved_at_360[0x4a0];
1835 u8 reserved_at_0[0x80];
1837 u8 rppp_max_rps[0x20];
1839 u8 rpg_time_reset[0x20];
1841 u8 rpg_byte_reset[0x20];
1843 u8 rpg_threshold[0x20];
1845 u8 rpg_max_rate[0x20];
1847 u8 rpg_ai_rate[0x20];
1849 u8 rpg_hai_rate[0x20];
1851 u8 rpg_gd[0x20];
1853 u8 rpg_min_dec_fac[0x20];
1855 u8 rpg_min_rate[0x20];
1857 u8 reserved_at_1c0[0x640];
1861 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1,
1862 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2,
1863 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4,
1867 u8 resize_field_select[0x20];
1871 u8 more_dump[0x1];
1872 u8 inline_dump[0x1];
1873 u8 reserved_at_2[0xa];
1874 u8 seq_num[0x4];
1875 u8 segment_type[0x10];
1877 u8 reserved_at_20[0x10];
1878 u8 vhca_id[0x10];
1880 u8 index1[0x20];
1882 u8 index2[0x20];
1884 u8 num_of_obj1[0x10];
1885 u8 num_of_obj2[0x10];
1887 u8 reserved_at_a0[0x20];
1889 u8 device_opaque[0x40];
1891 u8 mkey[0x20];
1893 u8 size[0x20];
1895 u8 address[0x40];
1897 u8 inline_data[52][0x20];
1901 u8 reserved_at_0[0x4];
1902 u8 num_of_obj2_supports_active[0x1];
1903 u8 num_of_obj2_supports_all[0x1];
1904 u8 must_have_num_of_obj2[0x1];
1905 u8 support_num_of_obj2[0x1];
1906 u8 num_of_obj1_supports_active[0x1];
1907 u8 num_of_obj1_supports_all[0x1];
1908 u8 must_have_num_of_obj1[0x1];
1909 u8 support_num_of_obj1[0x1];
1910 u8 must_have_index2[0x1];
1911 u8 support_index2[0x1];
1912 u8 must_have_index1[0x1];
1913 u8 support_index1[0x1];
1914 u8 segment_type[0x10];
1916 u8 segment_name[4][0x20];
1918 u8 index1_name[4][0x20];
1920 u8 index2_name[4][0x20];
1924 u8 length_dw[0x10];
1925 u8 segment_type[0x10];
1931 u8 segment_called[0x10];
1932 u8 vhca_id[0x10];
1934 u8 index1[0x20];
1936 u8 index2[0x20];
1938 u8 num_of_obj1[0x10];
1939 u8 num_of_obj2[0x10];
1945 u8 reserved_at_20[0x10];
1946 u8 syndrome_id[0x10];
1948 u8 reserved_at_40[0x40];
1950 u8 error[8][0x20];
1956 u8 reserved_at_20[0x18];
1957 u8 dump_version[0x8];
1959 u8 hw_version[0x20];
1961 u8 fw_version[0x20];
1967 u8 reserved_at_20[0x10];
1968 u8 num_of_records[0x10];
1976 u8 reserved_at_20[0x20];
1978 u8 index1[0x20];
1980 u8 index2[0x20];
1982 u8 payload[][0x20];
1997 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1,
1998 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2,
1999 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4,
2000 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8,
2004 u8 modify_field_select[0x20];
2008 u8 field_select_r_roce_np[0x20];
2012 u8 field_select_r_roce_rp[0x20];
2016 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4,
2017 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8,
2018 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10,
2019 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20,
2020 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40,
2021 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80,
2022 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100,
2023 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200,
2024 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400,
2025 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800,
2029 u8 field_select_8021qaurp[0x20];
2033 u8 time_since_last_clear_high[0x20];
2035 u8 time_since_last_clear_low[0x20];
2037 u8 symbol_errors_high[0x20];
2039 u8 symbol_errors_low[0x20];
2041 u8 sync_headers_errors_high[0x20];
2043 u8 sync_headers_errors_low[0x20];
2045 u8 edpl_bip_errors_lane0_high[0x20];
2047 u8 edpl_bip_errors_lane0_low[0x20];
2049 u8 edpl_bip_errors_lane1_high[0x20];
2051 u8 edpl_bip_errors_lane1_low[0x20];
2053 u8 edpl_bip_errors_lane2_high[0x20];
2055 u8 edpl_bip_errors_lane2_low[0x20];
2057 u8 edpl_bip_errors_lane3_high[0x20];
2059 u8 edpl_bip_errors_lane3_low[0x20];
2061 u8 fc_fec_corrected_blocks_lane0_high[0x20];
2063 u8 fc_fec_corrected_blocks_lane0_low[0x20];
2065 u8 fc_fec_corrected_blocks_lane1_high[0x20];
2067 u8 fc_fec_corrected_blocks_lane1_low[0x20];
2069 u8 fc_fec_corrected_blocks_lane2_high[0x20];
2071 u8 fc_fec_corrected_blocks_lane2_low[0x20];
2073 u8 fc_fec_corrected_blocks_lane3_high[0x20];
2075 u8 fc_fec_corrected_blocks_lane3_low[0x20];
2077 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20];
2079 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20];
2081 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20];
2083 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20];
2085 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20];
2087 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20];
2089 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20];
2091 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20];
2093 u8 rs_fec_corrected_blocks_high[0x20];
2095 u8 rs_fec_corrected_blocks_low[0x20];
2097 u8 rs_fec_uncorrectable_blocks_high[0x20];
2099 u8 rs_fec_uncorrectable_blocks_low[0x20];
2101 u8 rs_fec_no_errors_blocks_high[0x20];
2103 u8 rs_fec_no_errors_blocks_low[0x20];
2105 u8 rs_fec_single_error_blocks_high[0x20];
2107 u8 rs_fec_single_error_blocks_low[0x20];
2109 u8 rs_fec_corrected_symbols_total_high[0x20];
2111 u8 rs_fec_corrected_symbols_total_low[0x20];
2113 u8 rs_fec_corrected_symbols_lane0_high[0x20];
2115 u8 rs_fec_corrected_symbols_lane0_low[0x20];
2117 u8 rs_fec_corrected_symbols_lane1_high[0x20];
2119 u8 rs_fec_corrected_symbols_lane1_low[0x20];
2121 u8 rs_fec_corrected_symbols_lane2_high[0x20];
2123 u8 rs_fec_corrected_symbols_lane2_low[0x20];
2125 u8 rs_fec_corrected_symbols_lane3_high[0x20];
2127 u8 rs_fec_corrected_symbols_lane3_low[0x20];
2129 u8 link_down_events[0x20];
2131 u8 successful_recovery_events[0x20];
2133 u8 reserved_at_640[0x180];
2137 u8 time_since_last_clear_high[0x20];
2139 u8 time_since_last_clear_low[0x20];
2141 u8 phy_received_bits_high[0x20];
2143 u8 phy_received_bits_low[0x20];
2145 u8 phy_symbol_errors_high[0x20];
2147 u8 phy_symbol_errors_low[0x20];
2149 u8 phy_corrected_bits_high[0x20];
2151 u8 phy_corrected_bits_low[0x20];
2153 u8 phy_corrected_bits_lane0_high[0x20];
2155 u8 phy_corrected_bits_lane0_low[0x20];
2157 u8 phy_corrected_bits_lane1_high[0x20];
2159 u8 phy_corrected_bits_lane1_low[0x20];
2161 u8 phy_corrected_bits_lane2_high[0x20];
2163 u8 phy_corrected_bits_lane2_low[0x20];
2165 u8 phy_corrected_bits_lane3_high[0x20];
2167 u8 phy_corrected_bits_lane3_low[0x20];
2169 u8 reserved_at_200[0x5c0];
2173 u8 symbol_error_counter[0x10];
2175 u8 link_error_recovery_counter[0x8];
2177 u8 link_downed_counter[0x8];
2179 u8 port_rcv_errors[0x10];
2181 u8 port_rcv_remote_physical_errors[0x10];
2183 u8 port_rcv_switch_relay_errors[0x10];
2185 u8 port_xmit_discards[0x10];
2187 u8 port_xmit_constraint_errors[0x8];
2189 u8 port_rcv_constraint_errors[0x8];
2191 u8 reserved_at_70[0x8];
2193 u8 link_overrun_errors[0x8];
2195 u8 reserved_at_80[0x10];
2197 u8 vl_15_dropped[0x10];
2199 u8 reserved_at_a0[0x80];
2201 u8 port_xmit_wait[0x20];
2205 u8 transmit_queue_high[0x20];
2207 u8 transmit_queue_low[0x20];
2209 u8 no_buffer_discard_uc_high[0x20];
2211 u8 no_buffer_discard_uc_low[0x20];
2213 u8 reserved_at_80[0x740];
2217 u8 wred_discard_high[0x20];
2219 u8 wred_discard_low[0x20];
2221 u8 ecn_marked_tc_high[0x20];
2223 u8 ecn_marked_tc_low[0x20];
2225 u8 reserved_at_80[0x740];
2229 u8 rx_octets_high[0x20];
2231 u8 rx_octets_low[0x20];
2233 u8 reserved_at_40[0xc0];
2235 u8 rx_frames_high[0x20];
2237 u8 rx_frames_low[0x20];
2239 u8 tx_octets_high[0x20];
2241 u8 tx_octets_low[0x20];
2243 u8 reserved_at_180[0xc0];
2245 u8 tx_frames_high[0x20];
2247 u8 tx_frames_low[0x20];
2249 u8 rx_pause_high[0x20];
2251 u8 rx_pause_low[0x20];
2253 u8 rx_pause_duration_high[0x20];
2255 u8 rx_pause_duration_low[0x20];
2257 u8 tx_pause_high[0x20];
2259 u8 tx_pause_low[0x20];
2261 u8 tx_pause_duration_high[0x20];
2263 u8 tx_pause_duration_low[0x20];
2265 u8 rx_pause_transition_high[0x20];
2267 u8 rx_pause_transition_low[0x20];
2269 u8 rx_discards_high[0x20];
2271 u8 rx_discards_low[0x20];
2273 u8 device_stall_minor_watermark_cnt_high[0x20];
2275 u8 device_stall_minor_watermark_cnt_low[0x20];
2277 u8 device_stall_critical_watermark_cnt_high[0x20];
2279 u8 device_stall_critical_watermark_cnt_low[0x20];
2281 u8 reserved_at_480[0x340];
2285 u8 port_transmit_wait_high[0x20];
2287 u8 port_transmit_wait_low[0x20];
2289 u8 reserved_at_40[0x100];
2291 u8 rx_buffer_almost_full_high[0x20];
2293 u8 rx_buffer_almost_full_low[0x20];
2295 u8 rx_buffer_full_high[0x20];
2297 u8 rx_buffer_full_low[0x20];
2299 u8 rx_icrc_encapsulated_high[0x20];
2301 u8 rx_icrc_encapsulated_low[0x20];
2303 u8 reserved_at_200[0x5c0];
2307 u8 dot3stats_alignment_errors_high[0x20];
2309 u8 dot3stats_alignment_errors_low[0x20];
2311 u8 dot3stats_fcs_errors_high[0x20];
2313 u8 dot3stats_fcs_errors_low[0x20];
2315 u8 dot3stats_single_collision_frames_high[0x20];
2317 u8 dot3stats_single_collision_frames_low[0x20];
2319 u8 dot3stats_multiple_collision_frames_high[0x20];
2321 u8 dot3stats_multiple_collision_frames_low[0x20];
2323 u8 dot3stats_sqe_test_errors_high[0x20];
2325 u8 dot3stats_sqe_test_errors_low[0x20];
2327 u8 dot3stats_deferred_transmissions_high[0x20];
2329 u8 dot3stats_deferred_transmissions_low[0x20];
2331 u8 dot3stats_late_collisions_high[0x20];
2333 u8 dot3stats_late_collisions_low[0x20];
2335 u8 dot3stats_excessive_collisions_high[0x20];
2337 u8 dot3stats_excessive_collisions_low[0x20];
2339 u8 dot3stats_internal_mac_transmit_errors_high[0x20];
2341 u8 dot3stats_internal_mac_transmit_errors_low[0x20];
2343 u8 dot3stats_carrier_sense_errors_high[0x20];
2345 u8 dot3stats_carrier_sense_errors_low[0x20];
2347 u8 dot3stats_frame_too_longs_high[0x20];
2349 u8 dot3stats_frame_too_longs_low[0x20];
2351 u8 dot3stats_internal_mac_receive_errors_high[0x20];
2353 u8 dot3stats_internal_mac_receive_errors_low[0x20];
2355 u8 dot3stats_symbol_errors_high[0x20];
2357 u8 dot3stats_symbol_errors_low[0x20];
2359 u8 dot3control_in_unknown_opcodes_high[0x20];
2361 u8 dot3control_in_unknown_opcodes_low[0x20];
2363 u8 dot3in_pause_frames_high[0x20];
2365 u8 dot3in_pause_frames_low[0x20];
2367 u8 dot3out_pause_frames_high[0x20];
2369 u8 dot3out_pause_frames_low[0x20];
2371 u8 reserved_at_400[0x3c0];
2375 u8 ether_stats_drop_events_high[0x20];
2377 u8 ether_stats_drop_events_low[0x20];
2379 u8 ether_stats_octets_high[0x20];
2381 u8 ether_stats_octets_low[0x20];
2383 u8 ether_stats_pkts_high[0x20];
2385 u8 ether_stats_pkts_low[0x20];
2387 u8 ether_stats_broadcast_pkts_high[0x20];
2389 u8 ether_stats_broadcast_pkts_low[0x20];
2391 u8 ether_stats_multicast_pkts_high[0x20];
2393 u8 ether_stats_multicast_pkts_low[0x20];
2395 u8 ether_stats_crc_align_errors_high[0x20];
2397 u8 ether_stats_crc_align_errors_low[0x20];
2399 u8 ether_stats_undersize_pkts_high[0x20];
2401 u8 ether_stats_undersize_pkts_low[0x20];
2403 u8 ether_stats_oversize_pkts_high[0x20];
2405 u8 ether_stats_oversize_pkts_low[0x20];
2407 u8 ether_stats_fragments_high[0x20];
2409 u8 ether_stats_fragments_low[0x20];
2411 u8 ether_stats_jabbers_high[0x20];
2413 u8 ether_stats_jabbers_low[0x20];
2415 u8 ether_stats_collisions_high[0x20];
2417 u8 ether_stats_collisions_low[0x20];
2419 u8 ether_stats_pkts64octets_high[0x20];
2421 u8 ether_stats_pkts64octets_low[0x20];
2423 u8 ether_stats_pkts65to127octets_high[0x20];
2425 u8 ether_stats_pkts65to127octets_low[0x20];
2427 u8 ether_stats_pkts128to255octets_high[0x20];
2429 u8 ether_stats_pkts128to255octets_low[0x20];
2431 u8 ether_stats_pkts256to511octets_high[0x20];
2433 u8 ether_stats_pkts256to511octets_low[0x20];
2435 u8 ether_stats_pkts512to1023octets_high[0x20];
2437 u8 ether_stats_pkts512to1023octets_low[0x20];
2439 u8 ether_stats_pkts1024to1518octets_high[0x20];
2441 u8 ether_stats_pkts1024to1518octets_low[0x20];
2443 u8 ether_stats_pkts1519to2047octets_high[0x20];
2445 u8 ether_stats_pkts1519to2047octets_low[0x20];
2447 u8 ether_stats_pkts2048to4095octets_high[0x20];
2449 u8 ether_stats_pkts2048to4095octets_low[0x20];
2451 u8 ether_stats_pkts4096to8191octets_high[0x20];
2453 u8 ether_stats_pkts4096to8191octets_low[0x20];
2455 u8 ether_stats_pkts8192to10239octets_high[0x20];
2457 u8 ether_stats_pkts8192to10239octets_low[0x20];
2459 u8 reserved_at_540[0x280];
2463 u8 if_in_octets_high[0x20];
2465 u8 if_in_octets_low[0x20];
2467 u8 if_in_ucast_pkts_high[0x20];
2469 u8 if_in_ucast_pkts_low[0x20];
2471 u8 if_in_discards_high[0x20];
2473 u8 if_in_discards_low[0x20];
2475 u8 if_in_errors_high[0x20];
2477 u8 if_in_errors_low[0x20];
2479 u8 if_in_unknown_protos_high[0x20];
2481 u8 if_in_unknown_protos_low[0x20];
2483 u8 if_out_octets_high[0x20];
2485 u8 if_out_octets_low[0x20];
2487 u8 if_out_ucast_pkts_high[0x20];
2489 u8 if_out_ucast_pkts_low[0x20];
2491 u8 if_out_discards_high[0x20];
2493 u8 if_out_discards_low[0x20];
2495 u8 if_out_errors_high[0x20];
2497 u8 if_out_errors_low[0x20];
2499 u8 if_in_multicast_pkts_high[0x20];
2501 u8 if_in_multicast_pkts_low[0x20];
2503 u8 if_in_broadcast_pkts_high[0x20];
2505 u8 if_in_broadcast_pkts_low[0x20];
2507 u8 if_out_multicast_pkts_high[0x20];
2509 u8 if_out_multicast_pkts_low[0x20];
2511 u8 if_out_broadcast_pkts_high[0x20];
2513 u8 if_out_broadcast_pkts_low[0x20];
2515 u8 reserved_at_340[0x480];
2519 u8 a_frames_transmitted_ok_high[0x20];
2521 u8 a_frames_transmitted_ok_low[0x20];
2523 u8 a_frames_received_ok_high[0x20];
2525 u8 a_frames_received_ok_low[0x20];
2527 u8 a_frame_check_sequence_errors_high[0x20];
2529 u8 a_frame_check_sequence_errors_low[0x20];
2531 u8 a_alignment_errors_high[0x20];
2533 u8 a_alignment_errors_low[0x20];
2535 u8 a_octets_transmitted_ok_high[0x20];
2537 u8 a_octets_transmitted_ok_low[0x20];
2539 u8 a_octets_received_ok_high[0x20];
2541 u8 a_octets_received_ok_low[0x20];
2543 u8 a_multicast_frames_xmitted_ok_high[0x20];
2545 u8 a_multicast_frames_xmitted_ok_low[0x20];
2547 u8 a_broadcast_frames_xmitted_ok_high[0x20];
2549 u8 a_broadcast_frames_xmitted_ok_low[0x20];
2551 u8 a_multicast_frames_received_ok_high[0x20];
2553 u8 a_multicast_frames_received_ok_low[0x20];
2555 u8 a_broadcast_frames_received_ok_high[0x20];
2557 u8 a_broadcast_frames_received_ok_low[0x20];
2559 u8 a_in_range_length_errors_high[0x20];
2561 u8 a_in_range_length_errors_low[0x20];
2563 u8 a_out_of_range_length_field_high[0x20];
2565 u8 a_out_of_range_length_field_low[0x20];
2567 u8 a_frame_too_long_errors_high[0x20];
2569 u8 a_frame_too_long_errors_low[0x20];
2571 u8 a_symbol_error_during_carrier_high[0x20];
2573 u8 a_symbol_error_during_carrier_low[0x20];
2575 u8 a_mac_control_frames_transmitted_high[0x20];
2577 u8 a_mac_control_frames_transmitted_low[0x20];
2579 u8 a_mac_control_frames_received_high[0x20];
2581 u8 a_mac_control_frames_received_low[0x20];
2583 u8 a_unsupported_opcodes_received_high[0x20];
2585 u8 a_unsupported_opcodes_received_low[0x20];
2587 u8 a_pause_mac_ctrl_frames_received_high[0x20];
2589 u8 a_pause_mac_ctrl_frames_received_low[0x20];
2591 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20];
2593 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20];
2595 u8 reserved_at_4c0[0x300];
2599 u8 life_time_counter_high[0x20];
2601 u8 life_time_counter_low[0x20];
2603 u8 rx_errors[0x20];
2605 u8 tx_errors[0x20];
2607 u8 l0_to_recovery_eieos[0x20];
2609 u8 l0_to_recovery_ts[0x20];
2611 u8 l0_to_recovery_framing[0x20];
2613 u8 l0_to_recovery_retrain[0x20];
2615 u8 crc_error_dllp[0x20];
2617 u8 crc_error_tlp[0x20];
2619 u8 tx_overflow_buffer_pkt_high[0x20];
2621 u8 tx_overflow_buffer_pkt_low[0x20];
2623 u8 outbound_stalled_reads[0x20];
2625 u8 outbound_stalled_writes[0x20];
2627 u8 outbound_stalled_reads_events[0x20];
2629 u8 outbound_stalled_writes_events[0x20];
2631 u8 reserved_at_200[0x5c0];
2635 u8 command_completion_vector[0x20];
2637 u8 reserved_at_20[0xc0];
2641 u8 reserved_at_0[0x18];
2642 u8 port_num[0x1];
2643 u8 reserved_at_19[0x3];
2644 u8 vl[0x4];
2646 u8 reserved_at_20[0xa0];
2650 u8 event_subtype[0x8];
2651 u8 reserved_at_8[0x8];
2652 u8 congestion_level[0x8];
2653 u8 reserved_at_18[0x8];
2655 u8 reserved_at_20[0xa0];
2659 u8 reserved_at_0[0x60];
2661 u8 gpio_event_hi[0x20];
2663 u8 gpio_event_lo[0x20];
2665 u8 reserved_at_a0[0x40];
2669 u8 reserved_at_0[0x40];
2671 u8 port_num[0x4];
2672 u8 reserved_at_44[0x1c];
2674 u8 reserved_at_60[0x80];
2678 u8 reserved_at_0[0xe0];
2682 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1,
2683 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2,
2687 u8 reserved_at_0[0x8];
2688 u8 cqn[0x18];
2690 u8 reserved_at_20[0x20];
2692 u8 reserved_at_40[0x18];
2693 u8 syndrome[0x8];
2695 u8 reserved_at_60[0x80];
2699 u8 bytes_committed[0x20];
2701 u8 r_key[0x20];
2703 u8 reserved_at_40[0x10];
2704 u8 packet_len[0x10];
2706 u8 rdma_op_len[0x20];
2708 u8 rdma_va[0x40];
2710 u8 reserved_at_c0[0x5];
2711 u8 rdma[0x1];
2712 u8 write[0x1];
2713 u8 requestor[0x1];
2714 u8 qp_number[0x18];
2718 u8 bytes_committed[0x20];
2720 u8 reserved_at_20[0x10];
2721 u8 wqe_index[0x10];
2723 u8 reserved_at_40[0x10];
2724 u8 len[0x10];
2726 u8 reserved_at_60[0x60];
2728 u8 reserved_at_c0[0x5];
2729 u8 rdma[0x1];
2730 u8 write_read[0x1];
2731 u8 requestor[0x1];
2732 u8 qpn[0x18];
2736 u8 reserved_at_0[0xa0];
2738 u8 type[0x8];
2739 u8 reserved_at_a8[0x18];
2741 u8 reserved_at_c0[0x8];
2742 u8 qpn_rqn_sqn[0x18];
2746 u8 reserved_at_0[0xc0];
2748 u8 reserved_at_c0[0x8];
2749 u8 dct_number[0x18];
2753 u8 reserved_at_0[0xc0];
2755 u8 reserved_at_c0[0x8];
2756 u8 cq_number[0x18];
2760 MLX5_QPC_STATE_RST = 0x0,
2761 MLX5_QPC_STATE_INIT = 0x1,
2762 MLX5_QPC_STATE_RTR = 0x2,
2763 MLX5_QPC_STATE_RTS = 0x3,
2764 MLX5_QPC_STATE_SQER = 0x4,
2765 MLX5_QPC_STATE_ERR = 0x6,
2766 MLX5_QPC_STATE_SQD = 0x7,
2767 MLX5_QPC_STATE_SUSPENDED = 0x9,
2771 MLX5_QPC_ST_RC = 0x0,
2772 MLX5_QPC_ST_UC = 0x1,
2773 MLX5_QPC_ST_UD = 0x2,
2774 MLX5_QPC_ST_XRC = 0x3,
2775 MLX5_QPC_ST_DCI = 0x5,
2776 MLX5_QPC_ST_QP0 = 0x7,
2777 MLX5_QPC_ST_QP1 = 0x8,
2778 MLX5_QPC_ST_RAW_DATAGRAM = 0x9,
2779 MLX5_QPC_ST_REG_UMR = 0xc,
2783 MLX5_QPC_PM_STATE_ARMED = 0x0,
2784 MLX5_QPC_PM_STATE_REARM = 0x1,
2785 MLX5_QPC_PM_STATE_RESERVED = 0x2,
2786 MLX5_QPC_PM_STATE_MIGRATED = 0x3,
2790 MLX5_QPC_OFFLOAD_TYPE_RNDV = 0x1,
2794 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0,
2795 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1,
2799 MLX5_QPC_MTU_256_BYTES = 0x1,
2800 MLX5_QPC_MTU_512_BYTES = 0x2,
2801 MLX5_QPC_MTU_1K_BYTES = 0x3,
2802 MLX5_QPC_MTU_2K_BYTES = 0x4,
2803 MLX5_QPC_MTU_4K_BYTES = 0x5,
2804 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7,
2808 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1,
2809 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2,
2810 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3,
2811 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4,
2812 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5,
2813 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6,
2814 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7,
2815 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8,
2819 MLX5_QPC_CS_REQ_DISABLE = 0x0,
2820 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11,
2821 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22,
2825 MLX5_QPC_CS_RES_DISABLE = 0x0,
2826 MLX5_QPC_CS_RES_UP_TO_32B = 0x1,
2827 MLX5_QPC_CS_RES_UP_TO_64B = 0x2,
2831 u8 state[0x4];
2832 u8 lag_tx_port_affinity[0x4];
2833 u8 st[0x8];
2834 u8 reserved_at_10[0x3];
2835 u8 pm_state[0x2];
2836 u8 reserved_at_15[0x1];
2837 u8 req_e2e_credit_mode[0x2];
2838 u8 offload_type[0x4];
2839 u8 end_padding_mode[0x2];
2840 u8 reserved_at_1e[0x2];
2842 u8 wq_signature[0x1];
2843 u8 block_lb_mc[0x1];
2844 u8 atomic_like_write_en[0x1];
2845 u8 latency_sensitive[0x1];
2846 u8 reserved_at_24[0x1];
2847 u8 drain_sigerr[0x1];
2848 u8 reserved_at_26[0x2];
2849 u8 pd[0x18];
2851 u8 mtu[0x3];
2852 u8 log_msg_max[0x5];
2853 u8 reserved_at_48[0x1];
2854 u8 log_rq_size[0x4];
2855 u8 log_rq_stride[0x3];
2856 u8 no_sq[0x1];
2857 u8 log_sq_size[0x4];
2858 u8 reserved_at_55[0x6];
2859 u8 rlky[0x1];
2860 u8 ulp_stateless_offload_mode[0x4];
2862 u8 counter_set_id[0x8];
2863 u8 uar_page[0x18];
2865 u8 reserved_at_80[0x8];
2866 u8 user_index[0x18];
2868 u8 reserved_at_a0[0x3];
2869 u8 log_page_size[0x5];
2870 u8 remote_qpn[0x18];
2876 u8 log_ack_req_freq[0x4];
2877 u8 reserved_at_384[0x4];
2878 u8 log_sra_max[0x3];
2879 u8 reserved_at_38b[0x2];
2880 u8 retry_count[0x3];
2881 u8 rnr_retry[0x3];
2882 u8 reserved_at_393[0x1];
2883 u8 fre[0x1];
2884 u8 cur_rnr_retry[0x3];
2885 u8 cur_retry_count[0x3];
2886 u8 reserved_at_39b[0x5];
2888 u8 reserved_at_3a0[0x20];
2890 u8 reserved_at_3c0[0x8];
2891 u8 next_send_psn[0x18];
2893 u8 reserved_at_3e0[0x8];
2894 u8 cqn_snd[0x18];
2896 u8 reserved_at_400[0x8];
2897 u8 deth_sqpn[0x18];
2899 u8 reserved_at_420[0x20];
2901 u8 reserved_at_440[0x8];
2902 u8 last_acked_psn[0x18];
2904 u8 reserved_at_460[0x8];
2905 u8 ssn[0x18];
2907 u8 reserved_at_480[0x8];
2908 u8 log_rra_max[0x3];
2909 u8 reserved_at_48b[0x1];
2910 u8 atomic_mode[0x4];
2911 u8 rre[0x1];
2912 u8 rwe[0x1];
2913 u8 rae[0x1];
2914 u8 reserved_at_493[0x1];
2915 u8 page_offset[0x6];
2916 u8 reserved_at_49a[0x3];
2917 u8 cd_slave_receive[0x1];
2918 u8 cd_slave_send[0x1];
2919 u8 cd_master[0x1];
2921 u8 reserved_at_4a0[0x3];
2922 u8 min_rnr_nak[0x5];
2923 u8 next_rcv_psn[0x18];
2925 u8 reserved_at_4c0[0x8];
2926 u8 xrcd[0x18];
2928 u8 reserved_at_4e0[0x8];
2929 u8 cqn_rcv[0x18];
2931 u8 dbr_addr[0x40];
2933 u8 q_key[0x20];
2935 u8 reserved_at_560[0x5];
2936 u8 rq_type[0x3];
2937 u8 srqn_rmpn_xrqn[0x18];
2939 u8 reserved_at_580[0x8];
2940 u8 rmsn[0x18];
2942 u8 hw_sq_wqebb_counter[0x10];
2943 u8 sw_sq_wqebb_counter[0x10];
2945 u8 hw_rq_counter[0x20];
2947 u8 sw_rq_counter[0x20];
2949 u8 reserved_at_600[0x20];
2951 u8 reserved_at_620[0xf];
2952 u8 cgs[0x1];
2953 u8 cs_req[0x8];
2954 u8 cs_res[0x8];
2956 u8 dc_access_key[0x40];
2958 u8 reserved_at_680[0x3];
2959 u8 dbr_umem_valid[0x1];
2961 u8 reserved_at_684[0xbc];
2965 u8 source_l3_address[16][0x8];
2967 u8 reserved_at_80[0x3];
2968 u8 vlan_valid[0x1];
2969 u8 vlan_id[0xc];
2970 u8 source_mac_47_32[0x10];
2972 u8 source_mac_31_0[0x20];
2974 u8 reserved_at_c0[0x14];
2975 u8 roce_l3_type[0x4];
2976 u8 roce_version[0x8];
2978 u8 reserved_at_e0[0x20];
2997 u8 reserved_at_0[0x8000];
3001 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1,
3002 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2,
3003 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4,
3004 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8,
3005 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT = 0x10,
3006 MLX5_FLOW_CONTEXT_ACTION_DECAP = 0x20,
3007 MLX5_FLOW_CONTEXT_ACTION_MOD_HDR = 0x40,
3008 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP = 0x80,
3009 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100,
3010 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2 = 0x400,
3011 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2 = 0x800,
3012 MLX5_FLOW_CONTEXT_ACTION_IPSEC_DECRYPT = 0x1000,
3013 MLX5_FLOW_CONTEXT_ACTION_IPSEC_ENCRYPT = 0x2000,
3017 MLX5_FLOW_CONTEXT_FLOW_SOURCE_ANY_VPORT = 0x0,
3018 MLX5_FLOW_CONTEXT_FLOW_SOURCE_UPLINK = 0x1,
3019 MLX5_FLOW_CONTEXT_FLOW_SOURCE_LOCAL_VPORT = 0x2,
3023 u8 ethtype[0x10];
3024 u8 prio[0x3];
3025 u8 cfi[0x1];
3026 u8 vid[0xc];
3032 u8 group_id[0x20];
3034 u8 reserved_at_40[0x8];
3035 u8 flow_tag[0x18];
3037 u8 reserved_at_60[0x10];
3038 u8 action[0x10];
3040 u8 extended_destination[0x1];
3041 u8 reserved_at_81[0x1];
3042 u8 flow_source[0x2];
3043 u8 reserved_at_84[0x4];
3044 u8 destination_list_size[0x18];
3046 u8 reserved_at_a0[0x8];
3047 u8 flow_counter_list_size[0x18];
3049 u8 packet_reformat_id[0x20];
3051 u8 modify_header_id[0x20];
3055 u8 ipsec_obj_id[0x20];
3056 u8 reserved_at_140[0xc0];
3060 u8 reserved_at_1200[0x600];
3066 MLX5_XRC_SRQC_STATE_GOOD = 0x0,
3067 MLX5_XRC_SRQC_STATE_ERROR = 0x1,
3071 u8 state[0x4];
3072 u8 log_xrc_srq_size[0x4];
3073 u8 reserved_at_8[0x18];
3075 u8 wq_signature[0x1];
3076 u8 cont_srq[0x1];
3077 u8 reserved_at_22[0x1];
3078 u8 rlky[0x1];
3079 u8 basic_cyclic_rcv_wqe[0x1];
3080 u8 log_rq_stride[0x3];
3081 u8 xrcd[0x18];
3083 u8 page_offset[0x6];
3084 u8 reserved_at_46[0x1];
3085 u8 dbr_umem_valid[0x1];
3086 u8 cqn[0x18];
3088 u8 reserved_at_60[0x20];
3090 u8 user_index_equal_xrc_srqn[0x1];
3091 u8 reserved_at_81[0x1];
3092 u8 log_page_size[0x6];
3093 u8 user_index[0x18];
3095 u8 reserved_at_a0[0x20];
3097 u8 reserved_at_c0[0x8];
3098 u8 pd[0x18];
3100 u8 lwm[0x10];
3101 u8 wqe_cnt[0x10];
3103 u8 reserved_at_100[0x40];
3105 u8 db_record_addr_h[0x20];
3107 u8 db_record_addr_l[0x1e];
3108 u8 reserved_at_17e[0x2];
3110 u8 reserved_at_180[0x80];
3114 u8 counter_error_queues[0x20];
3116 u8 total_error_queues[0x20];
3118 u8 send_queue_priority_update_flow[0x20];
3120 u8 reserved_at_60[0x20];
3122 u8 nic_receive_steering_discard[0x40];
3124 u8 receive_discard_vport_down[0x40];
3126 u8 transmit_discard_vport_down[0x40];
3128 u8 reserved_at_140[0xa0];
3130 u8 internal_rq_out_of_buffer[0x20];
3132 u8 reserved_at_200[0xe00];
3136 u8 packets[0x40];
3138 u8 octets[0x40];
3142 u8 strict_lag_tx_port_affinity[0x1];
3143 u8 tls_en[0x1];
3144 u8 reserved_at_2[0x2];
3145 u8 lag_tx_port_affinity[0x04];
3147 u8 reserved_at_8[0x4];
3148 u8 prio[0x4];
3149 u8 reserved_at_10[0x10];
3151 u8 reserved_at_20[0x100];
3153 u8 reserved_at_120[0x8];
3154 u8 transport_domain[0x18];
3156 u8 reserved_at_140[0x8];
3157 u8 underlay_qpn[0x18];
3159 u8 reserved_at_160[0x8];
3160 u8 pd[0x18];
3162 u8 reserved_at_180[0x380];
3166 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0,
3167 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1,
3171 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO = 0x1,
3172 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO = 0x2,
3176 MLX5_RX_HASH_FN_NONE = 0x0,
3177 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1,
3178 MLX5_RX_HASH_FN_TOEPLITZ = 0x2,
3182 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST = 0x1,
3183 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST = 0x2,
3187 u8 reserved_at_0[0x20];
3189 u8 disp_type[0x4];
3190 u8 tls_en[0x1];
3191 u8 reserved_at_25[0x1b];
3193 u8 reserved_at_40[0x40];
3195 u8 reserved_at_80[0x4];
3196 u8 lro_timeout_period_usecs[0x10];
3197 u8 lro_enable_mask[0x4];
3198 u8 lro_max_ip_payload_size[0x8];
3200 u8 reserved_at_a0[0x40];
3202 u8 reserved_at_e0[0x8];
3203 u8 inline_rqn[0x18];
3205 u8 rx_hash_symmetric[0x1];
3206 u8 reserved_at_101[0x1];
3207 u8 tunneled_offload_en[0x1];
3208 u8 reserved_at_103[0x5];
3209 u8 indirect_table[0x18];
3211 u8 rx_hash_fn[0x4];
3212 u8 reserved_at_124[0x2];
3213 u8 self_lb_block[0x2];
3214 u8 transport_domain[0x18];
3216 u8 rx_hash_toeplitz_key[10][0x20];
3222 u8 reserved_at_2c0[0x4c0];
3226 MLX5_SRQC_STATE_GOOD = 0x0,
3227 MLX5_SRQC_STATE_ERROR = 0x1,
3231 u8 state[0x4];
3232 u8 log_srq_size[0x4];
3233 u8 reserved_at_8[0x18];
3235 u8 wq_signature[0x1];
3236 u8 cont_srq[0x1];
3237 u8 reserved_at_22[0x1];
3238 u8 rlky[0x1];
3239 u8 reserved_at_24[0x1];
3240 u8 log_rq_stride[0x3];
3241 u8 xrcd[0x18];
3243 u8 page_offset[0x6];
3244 u8 reserved_at_46[0x2];
3245 u8 cqn[0x18];
3247 u8 reserved_at_60[0x20];
3249 u8 reserved_at_80[0x2];
3250 u8 log_page_size[0x6];
3251 u8 reserved_at_88[0x18];
3253 u8 reserved_at_a0[0x20];
3255 u8 reserved_at_c0[0x8];
3256 u8 pd[0x18];
3258 u8 lwm[0x10];
3259 u8 wqe_cnt[0x10];
3261 u8 reserved_at_100[0x40];
3263 u8 dbr_addr[0x40];
3265 u8 reserved_at_180[0x80];
3269 MLX5_SQC_STATE_RST = 0x0,
3270 MLX5_SQC_STATE_RDY = 0x1,
3271 MLX5_SQC_STATE_ERR = 0x3,
3275 u8 rlky[0x1];
3276 u8 cd_master[0x1];
3277 u8 fre[0x1];
3278 u8 flush_in_error_en[0x1];
3279 u8 allow_multi_pkt_send_wqe[0x1];
3280 u8 min_wqe_inline_mode[0x3];
3281 u8 state[0x4];
3282 u8 reg_umr[0x1];
3283 u8 allow_swp[0x1];
3284 u8 hairpin[0x1];
3285 u8 reserved_at_f[0x11];
3287 u8 reserved_at_20[0x8];
3288 u8 user_index[0x18];
3290 u8 reserved_at_40[0x8];
3291 u8 cqn[0x18];
3293 u8 reserved_at_60[0x8];
3294 u8 hairpin_peer_rq[0x18];
3296 u8 reserved_at_80[0x10];
3297 u8 hairpin_peer_vhca[0x10];
3299 u8 reserved_at_a0[0x50];
3301 u8 packet_pacing_rate_limit_index[0x10];
3302 u8 tis_lst_sz[0x10];
3303 u8 reserved_at_110[0x10];
3305 u8 reserved_at_120[0x40];
3307 u8 reserved_at_160[0x8];
3308 u8 tis_num_0[0x18];
3314 SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0,
3315 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1,
3316 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2,
3317 SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3,
3321 ELEMENT_TYPE_CAP_MASK_TASR = 1 << 0,
3328 u8 element_type[0x8];
3329 u8 reserved_at_8[0x18];
3331 u8 element_attributes[0x20];
3333 u8 parent_element_id[0x20];
3335 u8 reserved_at_60[0x40];
3337 u8 bw_share[0x20];
3339 u8 max_average_bw[0x20];
3341 u8 reserved_at_e0[0x120];
3345 u8 reserved_at_0[0xa0];
3347 u8 reserved_at_a0[0x5];
3348 u8 list_q_type[0x3];
3349 u8 reserved_at_a8[0x8];
3350 u8 rqt_max_size[0x10];
3352 u8 rq_vhca_id_format[0x1];
3353 u8 reserved_at_c1[0xf];
3354 u8 rqt_actual_size[0x10];
3356 u8 reserved_at_e0[0x6a0];
3362 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0,
3363 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1,
3367 MLX5_RQC_STATE_RST = 0x0,
3368 MLX5_RQC_STATE_RDY = 0x1,
3369 MLX5_RQC_STATE_ERR = 0x3,
3373 u8 rlky[0x1];
3374 u8 delay_drop_en[0x1];
3375 u8 scatter_fcs[0x1];
3376 u8 vsd[0x1];
3377 u8 mem_rq_type[0x4];
3378 u8 state[0x4];
3379 u8 reserved_at_c[0x1];
3380 u8 flush_in_error_en[0x1];
3381 u8 hairpin[0x1];
3382 u8 reserved_at_f[0x11];
3384 u8 reserved_at_20[0x8];
3385 u8 user_index[0x18];
3387 u8 reserved_at_40[0x8];
3388 u8 cqn[0x18];
3390 u8 counter_set_id[0x8];
3391 u8 reserved_at_68[0x18];
3393 u8 reserved_at_80[0x8];
3394 u8 rmpn[0x18];
3396 u8 reserved_at_a0[0x8];
3397 u8 hairpin_peer_sq[0x18];
3399 u8 reserved_at_c0[0x10];
3400 u8 hairpin_peer_vhca[0x10];
3402 u8 reserved_at_e0[0xa0];
3408 MLX5_RMPC_STATE_RDY = 0x1,
3409 MLX5_RMPC_STATE_ERR = 0x3,
3413 u8 reserved_at_0[0x8];
3414 u8 state[0x4];
3415 u8 reserved_at_c[0x14];
3417 u8 basic_cyclic_rcv_wqe[0x1];
3418 u8 reserved_at_21[0x1f];
3420 u8 reserved_at_40[0x140];
3426 u8 reserved_at_0[0x5];
3427 u8 min_wqe_inline_mode[0x3];
3428 u8 reserved_at_8[0x15];
3429 u8 disable_mc_local_lb[0x1];
3430 u8 disable_uc_local_lb[0x1];
3431 u8 roce_en[0x1];
3433 u8 arm_change_event[0x1];
3434 u8 reserved_at_21[0x1a];
3435 u8 event_on_mtu[0x1];
3436 u8 event_on_promisc_change[0x1];
3437 u8 event_on_vlan_change[0x1];
3438 u8 event_on_mc_address_change[0x1];
3439 u8 event_on_uc_address_change[0x1];
3441 u8 reserved_at_40[0xc];
3443 u8 affiliation_criteria[0x4];
3444 u8 affiliated_vhca_id[0x10];
3446 u8 reserved_at_60[0xd0];
3448 u8 mtu[0x10];
3450 u8 system_image_guid[0x40];
3451 u8 port_guid[0x40];
3452 u8 node_guid[0x40];
3454 u8 reserved_at_200[0x140];
3455 u8 qkey_violation_counter[0x10];
3456 u8 reserved_at_350[0x430];
3458 u8 promisc_uc[0x1];
3459 u8 promisc_mc[0x1];
3460 u8 promisc_all[0x1];
3461 u8 reserved_at_783[0x2];
3462 u8 allowed_list_type[0x3];
3463 u8 reserved_at_788[0xc];
3464 u8 allowed_list_size[0xc];
3468 u8 reserved_at_7e0[0x20];
3470 u8 current_uc_mac_address[][0x40];
3474 MLX5_MKC_ACCESS_MODE_PA = 0x0,
3475 MLX5_MKC_ACCESS_MODE_MTT = 0x1,
3476 MLX5_MKC_ACCESS_MODE_KLMS = 0x2,
3477 MLX5_MKC_ACCESS_MODE_KSM = 0x3,
3478 MLX5_MKC_ACCESS_MODE_SW_ICM = 0x4,
3479 MLX5_MKC_ACCESS_MODE_MEMIC = 0x5,
3483 u8 reserved_at_0[0x1];
3484 u8 free[0x1];
3485 u8 reserved_at_2[0x1];
3486 u8 access_mode_4_2[0x3];
3487 u8 reserved_at_6[0x7];
3488 u8 relaxed_ordering_write[0x1];
3489 u8 reserved_at_e[0x1];
3490 u8 small_fence_on_rdma_read_response[0x1];
3491 u8 umr_en[0x1];
3492 u8 a[0x1];
3493 u8 rw[0x1];
3494 u8 rr[0x1];
3495 u8 lw[0x1];
3496 u8 lr[0x1];
3497 u8 access_mode_1_0[0x2];
3498 u8 reserved_at_18[0x8];
3500 u8 qpn[0x18];
3501 u8 mkey_7_0[0x8];
3503 u8 reserved_at_40[0x20];
3505 u8 length64[0x1];
3506 u8 bsf_en[0x1];
3507 u8 sync_umr[0x1];
3508 u8 reserved_at_63[0x2];
3509 u8 expected_sigerr_count[0x1];
3510 u8 reserved_at_66[0x1];
3511 u8 en_rinval[0x1];
3512 u8 pd[0x18];
3514 u8 start_addr[0x40];
3516 u8 len[0x40];
3518 u8 bsf_octword_size[0x20];
3520 u8 reserved_at_120[0x80];
3522 u8 translations_octword_size[0x20];
3524 u8 reserved_at_1c0[0x19];
3525 u8 relaxed_ordering_read[0x1];
3526 u8 reserved_at_1d9[0x1];
3527 u8 log_page_size[0x5];
3529 u8 reserved_at_1e0[0x20];
3533 u8 reserved_at_0[0x10];
3534 u8 pkey[0x10];
3538 u8 array128_auto[16][0x8];
3542 u8 field_select[0x20];
3544 u8 reserved_at_20[0xe0];
3546 u8 sm_virt_aware[0x1];
3547 u8 has_smi[0x1];
3548 u8 has_raw[0x1];
3549 u8 grh_required[0x1];
3550 u8 reserved_at_104[0xc];
3551 u8 port_physical_state[0x4];
3552 u8 vport_state_policy[0x4];
3553 u8 port_state[0x4];
3554 u8 vport_state[0x4];
3556 u8 reserved_at_120[0x20];
3558 u8 system_image_guid[0x40];
3560 u8 port_guid[0x40];
3562 u8 node_guid[0x40];
3564 u8 cap_mask1[0x20];
3566 u8 cap_mask1_field_select[0x20];
3568 u8 cap_mask2[0x20];
3570 u8 cap_mask2_field_select[0x20];
3572 u8 reserved_at_280[0x80];
3574 u8 lid[0x10];
3575 u8 reserved_at_310[0x4];
3576 u8 init_type_reply[0x4];
3577 u8 lmc[0x3];
3578 u8 subnet_timeout[0x5];
3580 u8 sm_lid[0x10];
3581 u8 sm_sl[0x4];
3582 u8 reserved_at_334[0xc];
3584 u8 qkey_violation_counter[0x10];
3585 u8 pkey_violation_counter[0x10];
3587 u8 reserved_at_360[0xca0];
3591 u8 fdb_to_vport_reg_c[0x1];
3592 u8 reserved_at_1[0x2];
3593 u8 vport_svlan_strip[0x1];
3594 u8 vport_cvlan_strip[0x1];
3595 u8 vport_svlan_insert[0x1];
3596 u8 vport_cvlan_insert[0x2];
3597 u8 fdb_to_vport_reg_c_id[0x8];
3598 u8 reserved_at_10[0x10];
3600 u8 reserved_at_20[0x20];
3602 u8 svlan_cfi[0x1];
3603 u8 svlan_pcp[0x3];
3604 u8 svlan_id[0xc];
3605 u8 cvlan_cfi[0x1];
3606 u8 cvlan_pcp[0x3];
3607 u8 cvlan_id[0xc];
3609 u8 reserved_at_60[0x720];
3611 u8 sw_steering_vport_icm_address_rx[0x40];
3613 u8 sw_steering_vport_icm_address_tx[0x40];
3617 MLX5_EQC_STATUS_OK = 0x0,
3618 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa,
3622 MLX5_EQC_ST_ARMED = 0x9,
3623 MLX5_EQC_ST_FIRED = 0xa,
3627 u8 status[0x4];
3628 u8 reserved_at_4[0x9];
3629 u8 ec[0x1];
3630 u8 oi[0x1];
3631 u8 reserved_at_f[0x5];
3632 u8 st[0x4];
3633 u8 reserved_at_18[0x8];
3635 u8 reserved_at_20[0x20];
3637 u8 reserved_at_40[0x14];
3638 u8 page_offset[0x6];
3639 u8 reserved_at_5a[0x6];
3641 u8 reserved_at_60[0x3];
3642 u8 log_eq_size[0x5];
3643 u8 uar_page[0x18];
3645 u8 reserved_at_80[0x20];
3647 u8 reserved_at_a0[0x18];
3648 u8 intr[0x8];
3650 u8 reserved_at_c0[0x3];
3651 u8 log_page_size[0x5];
3652 u8 reserved_at_c8[0x18];
3654 u8 reserved_at_e0[0x60];
3656 u8 reserved_at_140[0x8];
3657 u8 consumer_counter[0x18];
3659 u8 reserved_at_160[0x8];
3660 u8 producer_counter[0x18];
3662 u8 reserved_at_180[0x80];
3666 MLX5_DCTC_STATE_ACTIVE = 0x0,
3667 MLX5_DCTC_STATE_DRAINING = 0x1,
3668 MLX5_DCTC_STATE_DRAINED = 0x2,
3672 MLX5_DCTC_CS_RES_DISABLE = 0x0,
3673 MLX5_DCTC_CS_RES_NA = 0x1,
3674 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2,
3678 MLX5_DCTC_MTU_256_BYTES = 0x1,
3679 MLX5_DCTC_MTU_512_BYTES = 0x2,
3680 MLX5_DCTC_MTU_1K_BYTES = 0x3,
3681 MLX5_DCTC_MTU_2K_BYTES = 0x4,
3682 MLX5_DCTC_MTU_4K_BYTES = 0x5,
3686 u8 reserved_at_0[0x4];
3687 u8 state[0x4];
3688 u8 reserved_at_8[0x18];
3690 u8 reserved_at_20[0x8];
3691 u8 user_index[0x18];
3693 u8 reserved_at_40[0x8];
3694 u8 cqn[0x18];
3696 u8 counter_set_id[0x8];
3697 u8 atomic_mode[0x4];
3698 u8 rre[0x1];
3699 u8 rwe[0x1];
3700 u8 rae[0x1];
3701 u8 atomic_like_write_en[0x1];
3702 u8 latency_sensitive[0x1];
3703 u8 rlky[0x1];
3704 u8 free_ar[0x1];
3705 u8 reserved_at_73[0xd];
3707 u8 reserved_at_80[0x8];
3708 u8 cs_res[0x8];
3709 u8 reserved_at_90[0x3];
3710 u8 min_rnr_nak[0x5];
3711 u8 reserved_at_98[0x8];
3713 u8 reserved_at_a0[0x8];
3714 u8 srqn_xrqn[0x18];
3716 u8 reserved_at_c0[0x8];
3717 u8 pd[0x18];
3719 u8 tclass[0x8];
3720 u8 reserved_at_e8[0x4];
3721 u8 flow_label[0x14];
3723 u8 dc_access_key[0x40];
3725 u8 reserved_at_140[0x5];
3726 u8 mtu[0x3];
3727 u8 port[0x8];
3728 u8 pkey_index[0x10];
3730 u8 reserved_at_160[0x8];
3731 u8 my_addr_index[0x8];
3732 u8 reserved_at_170[0x8];
3733 u8 hop_limit[0x8];
3735 u8 dc_access_key_violation_count[0x20];
3737 u8 reserved_at_1a0[0x14];
3738 u8 dei_cfi[0x1];
3739 u8 eth_prio[0x3];
3740 u8 ecn[0x2];
3741 u8 dscp[0x6];
3743 u8 reserved_at_1c0[0x20];
3744 u8 ece[0x20];
3748 MLX5_CQC_STATUS_OK = 0x0,
3749 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9,
3750 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa,
3754 MLX5_CQC_CQE_SZ_64_BYTES = 0x0,
3755 MLX5_CQC_CQE_SZ_128_BYTES = 0x1,
3759 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6,
3760 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9,
3761 MLX5_CQC_ST_FIRED = 0xa,
3765 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0,
3766 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1,
3771 u8 status[0x4];
3772 u8 reserved_at_4[0x2];
3773 u8 dbr_umem_valid[0x1];
3774 u8 reserved_at_7[0x1];
3775 u8 cqe_sz[0x3];
3776 u8 cc[0x1];
3777 u8 reserved_at_c[0x1];
3778 u8 scqe_break_moderation_en[0x1];
3779 u8 oi[0x1];
3780 u8 cq_period_mode[0x2];
3781 u8 cqe_comp_en[0x1];
3782 u8 mini_cqe_res_format[0x2];
3783 u8 st[0x4];
3784 u8 reserved_at_18[0x8];
3786 u8 reserved_at_20[0x20];
3788 u8 reserved_at_40[0x14];
3789 u8 page_offset[0x6];
3790 u8 reserved_at_5a[0x6];
3792 u8 reserved_at_60[0x3];
3793 u8 log_cq_size[0x5];
3794 u8 uar_page[0x18];
3796 u8 reserved_at_80[0x4];
3797 u8 cq_period[0xc];
3798 u8 cq_max_count[0x10];
3800 u8 reserved_at_a0[0x18];
3801 u8 c_eqn[0x8];
3803 u8 reserved_at_c0[0x3];
3804 u8 log_page_size[0x5];
3805 u8 reserved_at_c8[0x18];
3807 u8 reserved_at_e0[0x20];
3809 u8 reserved_at_100[0x8];
3810 u8 last_notified_index[0x18];
3812 u8 reserved_at_120[0x8];
3813 u8 last_solicit_index[0x18];
3815 u8 reserved_at_140[0x8];
3816 u8 consumer_counter[0x18];
3818 u8 reserved_at_160[0x8];
3819 u8 producer_counter[0x18];
3821 u8 reserved_at_180[0x40];
3823 u8 dbr_addr[0x40];
3830 u8 reserved_at_0[0x800];
3834 u8 reserved_at_0[0xc0];
3836 u8 reserved_at_c0[0x8];
3837 u8 ieee_vendor_id[0x18];
3839 u8 reserved_at_e0[0x10];
3840 u8 vsd_vendor_id[0x10];
3842 u8 vsd[208][0x8];
3844 u8 vsd_contd_psid[16][0x8];
3848 MLX5_XRQC_STATE_GOOD = 0x0,
3849 MLX5_XRQC_STATE_ERROR = 0x1,
3853 MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0,
3854 MLX5_XRQC_TOPOLOGY_TAG_MATCHING = 0x1,
3858 MLX5_XRQC_OFFLOAD_RNDV = 0x1,
3862 u8 log_matching_list_sz[0x4];
3863 u8 reserved_at_4[0xc];
3864 u8 append_next_index[0x10];
3866 u8 sw_phase_cnt[0x10];
3867 u8 hw_phase_cnt[0x10];
3869 u8 reserved_at_40[0x40];
3873 u8 state[0x4];
3874 u8 rlkey[0x1];
3875 u8 reserved_at_5[0xf];
3876 u8 topology[0x4];
3877 u8 reserved_at_18[0x4];
3878 u8 offload[0x4];
3880 u8 reserved_at_20[0x8];
3881 u8 user_index[0x18];
3883 u8 reserved_at_40[0x8];
3884 u8 cqn[0x18];
3886 u8 reserved_at_60[0xa0];
3890 u8 reserved_at_180[0x280];
3898 u8 reserved_at_0[0x20];
3905 u8 reserved_at_0[0x20];
3920 u8 reserved_at_0[0x7c0];
3925 u8 reserved_at_0[0x7c0];
3941 u8 reserved_at_0[0xe0];
3945 u8 reserved_at_0[0x100];
3947 u8 assert_existptr[0x20];
3949 u8 assert_callra[0x20];
3951 u8 reserved_at_140[0x40];
3953 u8 fw_version[0x20];
3955 u8 hw_id[0x20];
3957 u8 reserved_at_1c0[0x20];
3959 u8 irisc_index[0x8];
3960 u8 synd[0x8];
3961 u8 ext_synd[0x10];
3965 u8 no_lb[0x1];
3966 u8 reserved_at_1[0x7];
3967 u8 port[0x8];
3968 u8 reserved_at_10[0x10];
3970 u8 reserved_at_20[0x60];
3974 u8 traffic_class[0x4];
3975 u8 reserved_at_4[0xc];
3976 u8 vport_number[0x10];
3980 u8 reserved_at_0[0x10];
3981 u8 vport_number[0x10];
3985 TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0,
3986 TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1,
3987 TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2,
3991 u8 reserved_at_0[0x8];
3992 u8 tsar_type[0x8];
3993 u8 reserved_at_10[0x10];
3997 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0,
3998 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1,
4002 u8 status[0x8];
4003 u8 reserved_at_8[0x18];
4005 u8 syndrome[0x20];
4007 u8 reserved_at_40[0x3f];
4009 u8 state[0x1];
4013 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0,
4014 MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE = 0x1,
4015 MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN = 0x2,
4019 u8 opcode[0x10];
4020 u8 reserved_at_10[0x10];
4022 u8 reserved_at_20[0x10];
4023 u8 op_mod[0x10];
4025 u8 reserved_at_40[0x10];
4026 u8 profile[0x10];
4028 u8 reserved_at_60[0x20];
4032 u8 status[0x8];
4033 u8 reserved_at_8[0x18];
4035 u8 syndrome[0x20];
4037 u8 reserved_at_40[0x40];
4041 u8 opcode[0x10];
4042 u8 uid[0x10];
4044 u8 reserved_at_20[0x10];
4045 u8 op_mod[0x10];
4047 u8 reserved_at_40[0x8];
4048 u8 qpn[0x18];
4050 u8 reserved_at_60[0x20];
4052 u8 opt_param_mask[0x20];
4054 u8 reserved_at_a0[0x20];
4058 u8 reserved_at_800[0x80];
4062 u8 status[0x8];
4063 u8 reserved_at_8[0x18];
4065 u8 syndrome[0x20];
4067 u8 reserved_at_40[0x40];
4071 u8 opcode[0x10];
4072 u8 uid[0x10];
4074 u8 reserved_at_20[0x10];
4075 u8 op_mod[0x10];
4077 u8 reserved_at_40[0x8];
4078 u8 qpn[0x18];
4080 u8 reserved_at_60[0x20];
4082 u8 opt_param_mask[0x20];
4084 u8 reserved_at_a0[0x20];
4088 u8 reserved_at_800[0x80];
4092 u8 status[0x8];
4093 u8 reserved_at_8[0x18];
4095 u8 syndrome[0x20];
4097 u8 reserved_at_40[0x40];
4101 u8 opcode[0x10];
4102 u8 reserved_at_10[0x10];
4104 u8 reserved_at_20[0x10];
4105 u8 op_mod[0x10];
4107 u8 roce_address_index[0x10];
4108 u8 reserved_at_50[0xc];
4109 u8 vhca_port_num[0x4];
4111 u8 reserved_at_60[0x20];
4117 u8 status[0x8];
4118 u8 reserved_at_8[0x18];
4120 u8 syndrome[0x20];
4122 u8 reserved_at_40[0x40];
4126 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0,
4127 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2,
4131 u8 opcode[0x10];
4132 u8 reserved_at_10[0x10];
4134 u8 reserved_at_20[0x10];
4135 u8 op_mod[0x10];
4137 u8 reserved_at_40[0x20];
4139 u8 reserved_at_60[0x6];
4140 u8 demux_mode[0x2];
4141 u8 reserved_at_68[0x18];
4145 u8 status[0x8];
4146 u8 reserved_at_8[0x18];
4148 u8 syndrome[0x20];
4150 u8 reserved_at_40[0x40];
4154 u8 opcode[0x10];
4155 u8 reserved_at_10[0x10];
4157 u8 reserved_at_20[0x10];
4158 u8 op_mod[0x10];
4160 u8 reserved_at_40[0x60];
4162 u8 reserved_at_a0[0x8];
4163 u8 table_index[0x18];
4165 u8 reserved_at_c0[0x20];
4167 u8 reserved_at_e0[0x13];
4168 u8 vlan_valid[0x1];
4169 u8 vlan[0xc];
4173 u8 reserved_at_140[0xc0];
4177 u8 status[0x8];
4178 u8 reserved_at_8[0x18];
4180 u8 syndrome[0x20];
4182 u8 reserved_at_40[0x40];
4186 u8 opcode[0x10];
4187 u8 reserved_at_10[0x10];
4189 u8 reserved_at_20[0x10];
4190 u8 op_mod[0x10];
4192 u8 reserved_at_40[0x10];
4193 u8 current_issi[0x10];
4195 u8 reserved_at_60[0x20];
4199 u8 status[0x8];
4200 u8 reserved_at_8[0x18];
4202 u8 syndrome[0x20];
4204 u8 reserved_at_40[0x40];
4208 u8 opcode[0x10];
4209 u8 reserved_at_10[0x10];
4211 u8 reserved_at_20[0x10];
4212 u8 op_mod[0x10];
4214 u8 reserved_at_40[0x40];
4220 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0,
4221 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1,
4222 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2,
4223 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3,
4224 MLX5_SET_FTE_MODIFY_ENABLE_MASK_IPSEC_OBJ_ID = 0x4
4228 u8 status[0x8];
4229 u8 reserved_at_8[0x18];
4231 u8 syndrome[0x20];
4233 u8 reserved_at_40[0x40];
4237 u8 opcode[0x10];
4238 u8 reserved_at_10[0x10];
4240 u8 reserved_at_20[0x10];
4241 u8 op_mod[0x10];
4243 u8 other_vport[0x1];
4244 u8 reserved_at_41[0xf];
4245 u8 vport_number[0x10];
4247 u8 reserved_at_60[0x20];
4249 u8 table_type[0x8];
4250 u8 reserved_at_88[0x18];
4252 u8 reserved_at_a0[0x8];
4253 u8 table_id[0x18];
4255 u8 ignore_flow_level[0x1];
4256 u8 reserved_at_c1[0x17];
4257 u8 modify_enable_mask[0x8];
4259 u8 reserved_at_e0[0x20];
4261 u8 flow_index[0x20];
4263 u8 reserved_at_120[0xe0];
4269 u8 status[0x8];
4270 u8 reserved_at_8[0x18];
4272 u8 syndrome[0x20];
4274 u8 reserved_at_40[0x20];
4275 u8 ece[0x20];
4279 u8 opcode[0x10];
4280 u8 uid[0x10];
4282 u8 reserved_at_20[0x10];
4283 u8 op_mod[0x10];
4285 u8 reserved_at_40[0x8];
4286 u8 qpn[0x18];
4288 u8 reserved_at_60[0x20];
4290 u8 opt_param_mask[0x20];
4292 u8 ece[0x20];
4296 u8 reserved_at_800[0x80];
4300 u8 status[0x8];
4301 u8 reserved_at_8[0x18];
4303 u8 syndrome[0x20];
4305 u8 reserved_at_40[0x20];
4306 u8 ece[0x20];
4310 u8 opcode[0x10];
4311 u8 uid[0x10];
4313 u8 reserved_at_20[0x10];
4314 u8 op_mod[0x10];
4316 u8 reserved_at_40[0x8];
4317 u8 qpn[0x18];
4319 u8 reserved_at_60[0x20];
4321 u8 opt_param_mask[0x20];
4323 u8 ece[0x20];
4327 u8 reserved_at_800[0x80];
4331 u8 status[0x8];
4332 u8 reserved_at_8[0x18];
4334 u8 syndrome[0x20];
4336 u8 reserved_at_40[0x20];
4337 u8 ece[0x20];
4341 u8 opcode[0x10];
4342 u8 uid[0x10];
4344 u8 reserved_at_20[0x10];
4345 u8 op_mod[0x10];
4347 u8 reserved_at_40[0x8];
4348 u8 qpn[0x18];
4350 u8 reserved_at_60[0x20];
4352 u8 opt_param_mask[0x20];
4354 u8 ece[0x20];
4358 u8 reserved_at_800[0x80];
4362 u8 status[0x8];
4363 u8 reserved_at_8[0x18];
4365 u8 syndrome[0x20];
4367 u8 reserved_at_40[0x40];
4373 u8 opcode[0x10];
4374 u8 reserved_at_10[0x10];
4376 u8 reserved_at_20[0x10];
4377 u8 op_mod[0x10];
4379 u8 reserved_at_40[0x8];
4380 u8 xrqn[0x18];
4382 u8 reserved_at_60[0x20];
4386 u8 status[0x8];
4387 u8 reserved_at_8[0x18];
4389 u8 syndrome[0x20];
4391 u8 reserved_at_40[0x40];
4395 u8 reserved_at_280[0x600];
4397 u8 pas[][0x40];
4401 u8 opcode[0x10];
4402 u8 reserved_at_10[0x10];
4404 u8 reserved_at_20[0x10];
4405 u8 op_mod[0x10];
4407 u8 reserved_at_40[0x8];
4408 u8 xrc_srqn[0x18];
4410 u8 reserved_at_60[0x20];
4414 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0,
4415 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1,
4419 u8 status[0x8];
4420 u8 reserved_at_8[0x18];
4422 u8 syndrome[0x20];
4424 u8 reserved_at_40[0x20];
4426 u8 reserved_at_60[0x18];
4427 u8 admin_state[0x4];
4428 u8 state[0x4];
4432 MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT = 0x0,
4433 MLX5_VPORT_STATE_OP_MOD_ESW_VPORT = 0x1,
4434 MLX5_VPORT_STATE_OP_MOD_UPLINK = 0x2,
4438 u8 opcode[0x10];
4439 u8 uid[0x10];
4441 u8 reserved_at_20[0x10];
4442 u8 op_mod[0x10];
4444 u8 reserved_at_40[0x20];
4446 u8 reserved_at_60[0x20];
4450 u8 status[0x8];
4451 u8 reserved_at_8[0x18];
4453 u8 syndrome[0x20];
4455 u8 reserved_at_40[0x40];
4459 MLX5_QUERY_MONITOR_CNT_TYPE_PPCNT = 0x0,
4460 MLX5_QUERY_MONITOR_CNT_TYPE_Q_COUNTER = 0x1,
4464 MLX5_QUERY_MONITOR_PPCNT_IN_RANGE_LENGTH_ERRORS = 0x0,
4465 MLX5_QUERY_MONITOR_PPCNT_OUT_OF_RANGE_LENGTH_FIELD = 0x1,
4466 MLX5_QUERY_MONITOR_PPCNT_FRAME_TOO_LONG_ERRORS = 0x2,
4467 MLX5_QUERY_MONITOR_PPCNT_FRAME_CHECK_SEQUENCE_ERRORS = 0x3,
4468 MLX5_QUERY_MONITOR_PPCNT_ALIGNMENT_ERRORS = 0x4,
4469 MLX5_QUERY_MONITOR_PPCNT_IF_OUT_DISCARDS = 0x5,
4473 MLX5_QUERY_MONITOR_Q_COUNTER_RX_OUT_OF_BUFFER = 0x4,
4477 u8 reserved_at_0[0x4];
4478 u8 type[0x4];
4479 u8 reserved_at_8[0x8];
4480 u8 counter[0x10];
4482 u8 counter_group_id[0x20];
4491 u8 opcode[0x10];
4492 u8 uid[0x10];
4494 u8 reserved_at_20[0x10];
4495 u8 op_mod[0x10];
4497 u8 reserved_at_40[0x10];
4498 u8 num_of_counters[0x10];
4500 u8 reserved_at_60[0x20];
4506 u8 status[0x8];
4507 u8 reserved_at_8[0x18];
4509 u8 syndrome[0x20];
4511 u8 reserved_at_40[0x40];
4515 u8 opcode[0x10];
4516 u8 reserved_at_10[0x10];
4518 u8 reserved_at_20[0x10];
4519 u8 op_mod[0x10];
4521 u8 other_vport[0x1];
4522 u8 reserved_at_41[0xf];
4523 u8 vport_number[0x10];
4525 u8 reserved_at_60[0x20];
4529 u8 status[0x8];
4530 u8 reserved_at_8[0x18];
4532 u8 syndrome[0x20];
4534 u8 reserved_at_40[0x40];
4540 MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS = 0x0,
4544 u8 opcode[0x10];
4545 u8 reserved_at_10[0x10];
4547 u8 reserved_at_20[0x10];
4548 u8 op_mod[0x10];
4550 u8 other_vport[0x1];
4551 u8 reserved_at_41[0xf];
4552 u8 vport_number[0x10];
4554 u8 reserved_at_60[0x20];
4558 u8 status[0x8];
4559 u8 reserved_at_8[0x18];
4561 u8 syndrome[0x20];
4563 u8 reserved_at_40[0x40];
4589 u8 reserved_at_680[0xa00];
4593 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0,
4597 u8 opcode[0x10];
4598 u8 reserved_at_10[0x10];
4600 u8 reserved_at_20[0x10];
4601 u8 op_mod[0x10];
4603 u8 other_vport[0x1];
4604 u8 reserved_at_41[0xb];
4605 u8 port_num[0x4];
4606 u8 vport_number[0x10];
4608 u8 reserved_at_60[0x60];
4610 u8 clear[0x1];
4611 u8 reserved_at_c1[0x1f];
4613 u8 reserved_at_e0[0x20];
4617 u8 status[0x8];
4618 u8 reserved_at_8[0x18];
4620 u8 syndrome[0x20];
4622 u8 reserved_at_40[0x40];
4628 u8 opcode[0x10];
4629 u8 reserved_at_10[0x10];
4631 u8 reserved_at_20[0x10];
4632 u8 op_mod[0x10];
4634 u8 reserved_at_40[0x8];
4635 u8 tisn[0x18];
4637 u8 reserved_at_60[0x20];
4641 u8 status[0x8];
4642 u8 reserved_at_8[0x18];
4644 u8 syndrome[0x20];
4646 u8 reserved_at_40[0xc0];
4652 u8 opcode[0x10];
4653 u8 reserved_at_10[0x10];
4655 u8 reserved_at_20[0x10];
4656 u8 op_mod[0x10];
4658 u8 reserved_at_40[0x8];
4659 u8 tirn[0x18];
4661 u8 reserved_at_60[0x20];
4665 u8 status[0x8];
4666 u8 reserved_at_8[0x18];
4668 u8 syndrome[0x20];
4670 u8 reserved_at_40[0x40];
4674 u8 reserved_at_280[0x600];
4676 u8 pas[][0x40];
4680 u8 opcode[0x10];
4681 u8 reserved_at_10[0x10];
4683 u8 reserved_at_20[0x10];
4684 u8 op_mod[0x10];
4686 u8 reserved_at_40[0x8];
4687 u8 srqn[0x18];
4689 u8 reserved_at_60[0x20];
4693 u8 status[0x8];
4694 u8 reserved_at_8[0x18];
4696 u8 syndrome[0x20];
4698 u8 reserved_at_40[0xc0];
4704 u8 opcode[0x10];
4705 u8 reserved_at_10[0x10];
4707 u8 reserved_at_20[0x10];
4708 u8 op_mod[0x10];
4710 u8 reserved_at_40[0x8];
4711 u8 sqn[0x18];
4713 u8 reserved_at_60[0x20];
4717 u8 status[0x8];
4718 u8 reserved_at_8[0x18];
4720 u8 syndrome[0x20];
4722 u8 dump_fill_mkey[0x20];
4724 u8 resd_lkey[0x20];
4726 u8 null_mkey[0x20];
4728 u8 reserved_at_a0[0x60];
4732 u8 opcode[0x10];
4733 u8 reserved_at_10[0x10];
4735 u8 reserved_at_20[0x10];
4736 u8 op_mod[0x10];
4738 u8 reserved_at_40[0x40];
4742 u8 opcode[0x10];
4743 u8 reserved_at_10[0x10];
4745 u8 reserved_at_20[0x10];
4746 u8 op_mod[0x10];
4748 u8 reserved_at_40[0xc0];
4752 u8 reserved_at_300[0x100];
4756 SCHEDULING_HIERARCHY_E_SWITCH = 0x2,
4760 u8 opcode[0x10];
4761 u8 reserved_at_10[0x10];
4763 u8 reserved_at_20[0x10];
4764 u8 op_mod[0x10];
4766 u8 scheduling_hierarchy[0x8];
4767 u8 reserved_at_48[0x18];
4769 u8 scheduling_element_id[0x20];
4771 u8 reserved_at_80[0x180];
4775 u8 status[0x8];
4776 u8 reserved_at_8[0x18];
4778 u8 syndrome[0x20];
4780 u8 reserved_at_40[0xc0];
4786 u8 opcode[0x10];
4787 u8 reserved_at_10[0x10];
4789 u8 reserved_at_20[0x10];
4790 u8 op_mod[0x10];
4792 u8 reserved_at_40[0x8];
4793 u8 rqtn[0x18];
4795 u8 reserved_at_60[0x20];
4799 u8 status[0x8];
4800 u8 reserved_at_8[0x18];
4802 u8 syndrome[0x20];
4804 u8 reserved_at_40[0xc0];
4810 u8 opcode[0x10];
4811 u8 reserved_at_10[0x10];
4813 u8 reserved_at_20[0x10];
4814 u8 op_mod[0x10];
4816 u8 reserved_at_40[0x8];
4817 u8 rqn[0x18];
4819 u8 reserved_at_60[0x20];
4823 u8 status[0x8];
4824 u8 reserved_at_8[0x18];
4826 u8 syndrome[0x20];
4828 u8 reserved_at_40[0x40];
4834 u8 opcode[0x10];
4835 u8 reserved_at_10[0x10];
4837 u8 reserved_at_20[0x10];
4838 u8 op_mod[0x10];
4840 u8 roce_address_index[0x10];
4841 u8 reserved_at_50[0xc];
4842 u8 vhca_port_num[0x4];
4844 u8 reserved_at_60[0x20];
4848 u8 status[0x8];
4849 u8 reserved_at_8[0x18];
4851 u8 syndrome[0x20];
4853 u8 reserved_at_40[0xc0];
4859 u8 opcode[0x10];
4860 u8 reserved_at_10[0x10];
4862 u8 reserved_at_20[0x10];
4863 u8 op_mod[0x10];
4865 u8 reserved_at_40[0x8];
4866 u8 rmpn[0x18];
4868 u8 reserved_at_60[0x20];
4872 u8 status[0x8];
4873 u8 reserved_at_8[0x18];
4875 u8 syndrome[0x20];
4877 u8 reserved_at_40[0x20];
4878 u8 ece[0x20];
4880 u8 opt_param_mask[0x20];
4882 u8 reserved_at_a0[0x20];
4886 u8 reserved_at_800[0x80];
4888 u8 pas[][0x40];
4892 u8 opcode[0x10];
4893 u8 reserved_at_10[0x10];
4895 u8 reserved_at_20[0x10];
4896 u8 op_mod[0x10];
4898 u8 reserved_at_40[0x8];
4899 u8 qpn[0x18];
4901 u8 reserved_at_60[0x20];
4905 u8 status[0x8];
4906 u8 reserved_at_8[0x18];
4908 u8 syndrome[0x20];
4910 u8 reserved_at_40[0x40];
4912 u8 rx_write_requests[0x20];
4914 u8 reserved_at_a0[0x20];
4916 u8 rx_read_requests[0x20];
4918 u8 reserved_at_e0[0x20];
4920 u8 rx_atomic_requests[0x20];
4922 u8 reserved_at_120[0x20];
4924 u8 rx_dct_connect[0x20];
4926 u8 reserved_at_160[0x20];
4928 u8 out_of_buffer[0x20];
4930 u8 reserved_at_1a0[0x20];
4932 u8 out_of_sequence[0x20];
4934 u8 reserved_at_1e0[0x20];
4936 u8 duplicate_request[0x20];
4938 u8 reserved_at_220[0x20];
4940 u8 rnr_nak_retry_err[0x20];
4942 u8 reserved_at_260[0x20];
4944 u8 packet_seq_err[0x20];
4946 u8 reserved_at_2a0[0x20];
4948 u8 implied_nak_seq_err[0x20];
4950 u8 reserved_at_2e0[0x20];
4952 u8 local_ack_timeout_err[0x20];
4954 u8 reserved_at_320[0xa0];
4956 u8 resp_local_length_error[0x20];
4958 u8 req_local_length_error[0x20];
4960 u8 resp_local_qp_error[0x20];
4962 u8 local_operation_error[0x20];
4964 u8 resp_local_protection[0x20];
4966 u8 req_local_protection[0x20];
4968 u8 resp_cqe_error[0x20];
4970 u8 req_cqe_error[0x20];
4972 u8 req_mw_binding[0x20];
4974 u8 req_bad_response[0x20];
4976 u8 req_remote_invalid_request[0x20];
4978 u8 resp_remote_invalid_request[0x20];
4980 u8 req_remote_access_errors[0x20];
4982 u8 resp_remote_access_errors[0x20];
4984 u8 req_remote_operation_errors[0x20];
4986 u8 req_transport_retries_exceeded[0x20];
4988 u8 cq_overflow[0x20];
4990 u8 resp_cqe_flush_error[0x20];
4992 u8 req_cqe_flush_error[0x20];
4994 u8 reserved_at_620[0x20];
4996 u8 roce_adp_retrans[0x20];
4998 u8 roce_adp_retrans_to[0x20];
5000 u8 roce_slow_restart[0x20];
5002 u8 roce_slow_restart_cnps[0x20];
5004 u8 roce_slow_restart_trans[0x20];
5006 u8 reserved_at_6e0[0x120];
5010 u8 opcode[0x10];
5011 u8 reserved_at_10[0x10];
5013 u8 reserved_at_20[0x10];
5014 u8 op_mod[0x10];
5016 u8 reserved_at_40[0x80];
5018 u8 clear[0x1];
5019 u8 reserved_at_c1[0x1f];
5021 u8 reserved_at_e0[0x18];
5022 u8 counter_set_id[0x8];
5026 u8 status[0x8];
5027 u8 reserved_at_8[0x18];
5029 u8 syndrome[0x20];
5031 u8 embedded_cpu_function[0x1];
5032 u8 reserved_at_41[0xf];
5033 u8 function_id[0x10];
5035 u8 num_pages[0x20];
5039 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1,
5040 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2,
5041 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3,
5045 u8 opcode[0x10];
5046 u8 reserved_at_10[0x10];
5048 u8 reserved_at_20[0x10];
5049 u8 op_mod[0x10];
5051 u8 embedded_cpu_function[0x1];
5052 u8 reserved_at_41[0xf];
5053 u8 function_id[0x10];
5055 u8 reserved_at_60[0x20];
5059 u8 status[0x8];
5060 u8 reserved_at_8[0x18];
5062 u8 syndrome[0x20];
5064 u8 reserved_at_40[0x40];
5070 u8 opcode[0x10];
5071 u8 reserved_at_10[0x10];
5073 u8 reserved_at_20[0x10];
5074 u8 op_mod[0x10];
5076 u8 other_vport[0x1];
5077 u8 reserved_at_41[0xf];
5078 u8 vport_number[0x10];
5080 u8 reserved_at_60[0x5];
5081 u8 allowed_list_type[0x3];
5082 u8 reserved_at_68[0x18];
5086 u8 status[0x8];
5087 u8 reserved_at_8[0x18];
5089 u8 syndrome[0x20];
5091 u8 reserved_at_40[0x40];
5095 u8 reserved_at_280[0x600];
5097 u8 bsf0_klm0_pas_mtt0_1[16][0x8];
5099 u8 bsf1_klm1_pas_mtt2_3[16][0x8];
5103 u8 opcode[0x10];
5104 u8 reserved_at_10[0x10];
5106 u8 reserved_at_20[0x10];
5107 u8 op_mod[0x10];
5109 u8 reserved_at_40[0x8];
5110 u8 mkey_index[0x18];
5112 u8 pg_access[0x1];
5113 u8 reserved_at_61[0x1f];
5117 u8 status[0x8];
5118 u8 reserved_at_8[0x18];
5120 u8 syndrome[0x20];
5122 u8 reserved_at_40[0x40];
5124 u8 mad_dumux_parameters_block[0x20];
5128 u8 opcode[0x10];
5129 u8 reserved_at_10[0x10];
5131 u8 reserved_at_20[0x10];
5132 u8 op_mod[0x10];
5134 u8 reserved_at_40[0x40];
5138 u8 status[0x8];
5139 u8 reserved_at_8[0x18];
5141 u8 syndrome[0x20];
5143 u8 reserved_at_40[0xa0];
5145 u8 reserved_at_e0[0x13];
5146 u8 vlan_valid[0x1];
5147 u8 vlan[0xc];
5151 u8 reserved_at_140[0xc0];
5155 u8 opcode[0x10];
5156 u8 reserved_at_10[0x10];
5158 u8 reserved_at_20[0x10];
5159 u8 op_mod[0x10];
5161 u8 reserved_at_40[0x60];
5163 u8 reserved_at_a0[0x8];
5164 u8 table_index[0x18];
5166 u8 reserved_at_c0[0x140];
5170 u8 status[0x8];
5171 u8 reserved_at_8[0x18];
5173 u8 syndrome[0x20];
5175 u8 reserved_at_40[0x10];
5176 u8 current_issi[0x10];
5178 u8 reserved_at_60[0xa0];
5180 u8 reserved_at_100[76][0x8];
5181 u8 supported_issi_dw0[0x20];
5185 u8 opcode[0x10];
5186 u8 reserved_at_10[0x10];
5188 u8 reserved_at_20[0x10];
5189 u8 op_mod[0x10];
5191 u8 reserved_at_40[0x40];
5195 u8 status[0x8];
5196 u8 reserved_0[0x18];
5198 u8 syndrome[0x20];
5199 u8 reserved_1[0x40];
5203 u8 opcode[0x10];
5204 u8 reserved_0[0x10];
5206 u8 reserved_1[0x10];
5207 u8 op_mod[0x10];
5209 u8 reserved_2[0x40];
5210 u8 driver_version[64][0x8];
5214 u8 status[0x8];
5215 u8 reserved_at_8[0x18];
5217 u8 syndrome[0x20];
5219 u8 reserved_at_40[0x40];
5225 u8 opcode[0x10];
5226 u8 reserved_at_10[0x10];
5228 u8 reserved_at_20[0x10];
5229 u8 op_mod[0x10];
5231 u8 other_vport[0x1];
5232 u8 reserved_at_41[0xb];
5233 u8 port_num[0x4];
5234 u8 vport_number[0x10];
5236 u8 reserved_at_60[0x10];
5237 u8 pkey_index[0x10];
5241 MLX5_HCA_VPORT_SEL_PORT_GUID = 1 << 0,
5247 u8 status[0x8];
5248 u8 reserved_at_8[0x18];
5250 u8 syndrome[0x20];
5252 u8 reserved_at_40[0x20];
5254 u8 gids_num[0x10];
5255 u8 reserved_at_70[0x10];
5261 u8 opcode[0x10];
5262 u8 reserved_at_10[0x10];
5264 u8 reserved_at_20[0x10];
5265 u8 op_mod[0x10];
5267 u8 other_vport[0x1];
5268 u8 reserved_at_41[0xb];
5269 u8 port_num[0x4];
5270 u8 vport_number[0x10];
5272 u8 reserved_at_60[0x10];
5273 u8 gid_index[0x10];
5277 u8 status[0x8];
5278 u8 reserved_at_8[0x18];
5280 u8 syndrome[0x20];
5282 u8 reserved_at_40[0x40];
5288 u8 opcode[0x10];
5289 u8 reserved_at_10[0x10];
5291 u8 reserved_at_20[0x10];
5292 u8 op_mod[0x10];
5294 u8 other_vport[0x1];
5295 u8 reserved_at_41[0xb];
5296 u8 port_num[0x4];
5297 u8 vport_number[0x10];
5299 u8 reserved_at_60[0x20];
5303 u8 status[0x8];
5304 u8 reserved_at_8[0x18];
5306 u8 syndrome[0x20];
5308 u8 reserved_at_40[0x40];
5314 u8 opcode[0x10];
5315 u8 reserved_at_10[0x10];
5317 u8 reserved_at_20[0x10];
5318 u8 op_mod[0x10];
5320 u8 other_function[0x1];
5321 u8 reserved_at_41[0xf];
5322 u8 function_id[0x10];
5324 u8 reserved_at_60[0x20];
5328 u8 roce[0x1];
5329 u8 reserved_at_1[0x27f];
5333 u8 status[0x8];
5334 u8 reserved_at_8[0x18];
5336 u8 syndrome[0x20];
5338 u8 reserved_at_40[0x40];
5344 u8 opcode[0x10];
5345 u8 reserved_at_10[0x10];
5347 u8 reserved_at_20[0x10];
5348 u8 op_mod[0x10];
5350 u8 reserved_at_40[0x10];
5351 u8 function_id[0x10];
5353 u8 reserved_at_60[0x20];
5357 u8 status[0x8];
5358 u8 reserved_at_8[0x18];
5360 u8 syndrome[0x20];
5362 u8 reserved_at_40[0x40];
5366 u8 opcode[0x10];
5367 u8 reserved_at_10[0x10];
5369 u8 reserved_at_20[0x10];
5370 u8 op_mod[0x10];
5372 u8 reserved_at_40[0x10];
5373 u8 function_id[0x10];
5374 u8 field_select[0x20];
5380 u8 reformat_en[0x1];
5381 u8 decap_en[0x1];
5382 u8 sw_owner[0x1];
5383 u8 termination_table[0x1];
5384 u8 table_miss_action[0x4];
5385 u8 level[0x8];
5386 u8 reserved_at_10[0x8];
5387 u8 log_size[0x8];
5389 u8 reserved_at_20[0x8];
5390 u8 table_miss_id[0x18];
5392 u8 reserved_at_40[0x8];
5393 u8 lag_master_next_table_id[0x18];
5395 u8 reserved_at_60[0x60];
5397 u8 sw_owner_icm_root_1[0x40];
5399 u8 sw_owner_icm_root_0[0x40];
5404 u8 status[0x8];
5405 u8 reserved_at_8[0x18];
5407 u8 syndrome[0x20];
5409 u8 reserved_at_40[0x80];
5415 u8 opcode[0x10];
5416 u8 reserved_at_10[0x10];
5418 u8 reserved_at_20[0x10];
5419 u8 op_mod[0x10];
5421 u8 reserved_at_40[0x40];
5423 u8 table_type[0x8];
5424 u8 reserved_at_88[0x18];
5426 u8 reserved_at_a0[0x8];
5427 u8 table_id[0x18];
5429 u8 reserved_at_c0[0x140];
5433 u8 status[0x8];
5434 u8 reserved_at_8[0x18];
5436 u8 syndrome[0x20];
5438 u8 reserved_at_40[0x1c0];
5444 u8 opcode[0x10];
5445 u8 reserved_at_10[0x10];
5447 u8 reserved_at_20[0x10];
5448 u8 op_mod[0x10];
5450 u8 reserved_at_40[0x40];
5452 u8 table_type[0x8];
5453 u8 reserved_at_88[0x18];
5455 u8 reserved_at_a0[0x8];
5456 u8 table_id[0x18];
5458 u8 reserved_at_c0[0x40];
5460 u8 flow_index[0x20];
5462 u8 reserved_at_120[0xe0];
5466 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
5467 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
5468 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
5469 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3,
5470 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_3 = 0x4,
5474 u8 status[0x8];
5475 u8 reserved_at_8[0x18];
5477 u8 syndrome[0x20];
5479 u8 reserved_at_40[0xa0];
5481 u8 start_flow_index[0x20];
5483 u8 reserved_at_100[0x20];
5485 u8 end_flow_index[0x20];
5487 u8 reserved_at_140[0xa0];
5489 u8 reserved_at_1e0[0x18];
5490 u8 match_criteria_enable[0x8];
5494 u8 reserved_at_1200[0xe00];
5498 u8 opcode[0x10];
5499 u8 reserved_at_10[0x10];
5501 u8 reserved_at_20[0x10];
5502 u8 op_mod[0x10];
5504 u8 reserved_at_40[0x40];
5506 u8 table_type[0x8];
5507 u8 reserved_at_88[0x18];
5509 u8 reserved_at_a0[0x8];
5510 u8 table_id[0x18];
5512 u8 group_id[0x20];
5514 u8 reserved_at_e0[0x120];
5518 u8 status[0x8];
5519 u8 reserved_at_8[0x18];
5521 u8 syndrome[0x20];
5523 u8 reserved_at_40[0x40];
5529 u8 opcode[0x10];
5530 u8 reserved_at_10[0x10];
5532 u8 reserved_at_20[0x10];
5533 u8 op_mod[0x10];
5535 u8 reserved_at_40[0x80];
5537 u8 clear[0x1];
5538 u8 reserved_at_c1[0xf];
5539 u8 num_of_counters[0x10];
5541 u8 flow_counter_id[0x20];
5545 u8 status[0x8];
5546 u8 reserved_at_8[0x18];
5548 u8 syndrome[0x20];
5550 u8 reserved_at_40[0x40];
5556 u8 opcode[0x10];
5557 u8 reserved_at_10[0x10];
5559 u8 reserved_at_20[0x10];
5560 u8 op_mod[0x10];
5562 u8 other_vport[0x1];
5563 u8 reserved_at_41[0xf];
5564 u8 vport_number[0x10];
5566 u8 reserved_at_60[0x20];
5570 u8 status[0x8];
5571 u8 reserved_at_8[0x18];
5573 u8 syndrome[0x20];
5575 u8 reserved_at_40[0x40];
5579 u8 reserved_at_0[0x1b];
5580 u8 fdb_to_vport_reg_c_id[0x1];
5581 u8 vport_cvlan_insert[0x1];
5582 u8 vport_svlan_insert[0x1];
5583 u8 vport_cvlan_strip[0x1];
5584 u8 vport_svlan_strip[0x1];
5588 u8 opcode[0x10];
5589 u8 reserved_at_10[0x10];
5591 u8 reserved_at_20[0x10];
5592 u8 op_mod[0x10];
5594 u8 other_vport[0x1];
5595 u8 reserved_at_41[0xf];
5596 u8 vport_number[0x10];
5604 u8 status[0x8];
5605 u8 reserved_at_8[0x18];
5607 u8 syndrome[0x20];
5609 u8 reserved_at_40[0x40];
5613 u8 reserved_at_280[0x40];
5615 u8 event_bitmask[0x40];
5617 u8 reserved_at_300[0x580];
5619 u8 pas[][0x40];
5623 u8 opcode[0x10];
5624 u8 reserved_at_10[0x10];
5626 u8 reserved_at_20[0x10];
5627 u8 op_mod[0x10];
5629 u8 reserved_at_40[0x18];
5630 u8 eq_number[0x8];
5632 u8 reserved_at_60[0x20];
5636 u8 reserved_at_0[0x5];
5637 u8 reformat_type[0x3];
5638 u8 reserved_at_8[0xe];
5639 u8 reformat_data_size[0xa];
5641 u8 reserved_at_20[0x10];
5642 u8 reformat_data[2][0x8];
5644 u8 more_reformat_data[][0x8];
5648 u8 status[0x8];
5649 u8 reserved_at_8[0x18];
5651 u8 syndrome[0x20];
5653 u8 reserved_at_40[0xa0];
5659 u8 opcode[0x10];
5660 u8 reserved_at_10[0x10];
5662 u8 reserved_at_20[0x10];
5663 u8 op_mod[0x10];
5665 u8 packet_reformat_id[0x20];
5667 u8 reserved_at_60[0xa0];
5671 u8 status[0x8];
5672 u8 reserved_at_8[0x18];
5674 u8 syndrome[0x20];
5676 u8 packet_reformat_id[0x20];
5678 u8 reserved_at_60[0x20];
5682 MLX5_REFORMAT_TYPE_L2_TO_VXLAN = 0x0,
5683 MLX5_REFORMAT_TYPE_L2_TO_NVGRE = 0x1,
5684 MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL = 0x2,
5685 MLX5_REFORMAT_TYPE_L3_TUNNEL_TO_L2 = 0x3,
5686 MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL = 0x4,
5690 u8 opcode[0x10];
5691 u8 reserved_at_10[0x10];
5693 u8 reserved_at_20[0x10];
5694 u8 op_mod[0x10];
5696 u8 reserved_at_40[0xa0];
5702 u8 status[0x8];
5703 u8 reserved_at_8[0x18];
5705 u8 syndrome[0x20];
5707 u8 reserved_at_40[0x40];
5711 u8 opcode[0x10];
5712 u8 reserved_at_10[0x10];
5714 u8 reserved_20[0x10];
5715 u8 op_mod[0x10];
5717 u8 packet_reformat_id[0x20];
5719 u8 reserved_60[0x20];
5723 u8 action_type[0x4];
5724 u8 field[0xc];
5725 u8 reserved_at_10[0x3];
5726 u8 offset[0x5];
5727 u8 reserved_at_18[0x3];
5728 u8 length[0x5];
5730 u8 data[0x20];
5734 u8 action_type[0x4];
5735 u8 field[0xc];
5736 u8 reserved_at_10[0x10];
5738 u8 data[0x20];
5742 u8 action_type[0x4];
5743 u8 src_field[0xc];
5744 u8 reserved_at_10[0x3];
5745 u8 src_offset[0x5];
5746 u8 reserved_at_18[0x3];
5747 u8 length[0x5];
5749 u8 reserved_at_20[0x4];
5750 u8 dst_field[0xc];
5751 u8 reserved_at_30[0x3];
5752 u8 dst_offset[0x5];
5753 u8 reserved_at_38[0x8];
5760 u8 reserved_at_0[0x40];
5764 MLX5_ACTION_TYPE_SET = 0x1,
5765 MLX5_ACTION_TYPE_ADD = 0x2,
5766 MLX5_ACTION_TYPE_COPY = 0x3,
5770 MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16 = 0x1,
5771 MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0 = 0x2,
5772 MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE = 0x3,
5773 MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16 = 0x4,
5774 MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0 = 0x5,
5775 MLX5_ACTION_IN_FIELD_OUT_IP_DSCP = 0x6,
5776 MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS = 0x7,
5777 MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT = 0x8,
5778 MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT = 0x9,
5779 MLX5_ACTION_IN_FIELD_OUT_IP_TTL = 0xa,
5780 MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT = 0xb,
5781 MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT = 0xc,
5782 MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96 = 0xd,
5783 MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64 = 0xe,
5784 MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32 = 0xf,
5785 MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0 = 0x10,
5786 MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96 = 0x11,
5787 MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64 = 0x12,
5788 MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32 = 0x13,
5789 MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0 = 0x14,
5790 MLX5_ACTION_IN_FIELD_OUT_SIPV4 = 0x15,
5791 MLX5_ACTION_IN_FIELD_OUT_DIPV4 = 0x16,
5792 MLX5_ACTION_IN_FIELD_OUT_FIRST_VID = 0x17,
5793 MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47,
5794 MLX5_ACTION_IN_FIELD_METADATA_REG_A = 0x49,
5795 MLX5_ACTION_IN_FIELD_METADATA_REG_B = 0x50,
5796 MLX5_ACTION_IN_FIELD_METADATA_REG_C_0 = 0x51,
5797 MLX5_ACTION_IN_FIELD_METADATA_REG_C_1 = 0x52,
5798 MLX5_ACTION_IN_FIELD_METADATA_REG_C_2 = 0x53,
5799 MLX5_ACTION_IN_FIELD_METADATA_REG_C_3 = 0x54,
5800 MLX5_ACTION_IN_FIELD_METADATA_REG_C_4 = 0x55,
5801 MLX5_ACTION_IN_FIELD_METADATA_REG_C_5 = 0x56,
5802 MLX5_ACTION_IN_FIELD_METADATA_REG_C_6 = 0x57,
5803 MLX5_ACTION_IN_FIELD_METADATA_REG_C_7 = 0x58,
5804 MLX5_ACTION_IN_FIELD_OUT_TCP_SEQ_NUM = 0x59,
5805 MLX5_ACTION_IN_FIELD_OUT_TCP_ACK_NUM = 0x5B,
5806 MLX5_ACTION_IN_FIELD_IPSEC_SYNDROME = 0x5D,
5810 u8 status[0x8];
5811 u8 reserved_at_8[0x18];
5813 u8 syndrome[0x20];
5815 u8 modify_header_id[0x20];
5817 u8 reserved_at_60[0x20];
5821 u8 opcode[0x10];
5822 u8 reserved_at_10[0x10];
5824 u8 reserved_at_20[0x10];
5825 u8 op_mod[0x10];
5827 u8 reserved_at_40[0x20];
5829 u8 table_type[0x8];
5830 u8 reserved_at_68[0x10];
5831 u8 num_of_actions[0x8];
5837 u8 status[0x8];
5838 u8 reserved_at_8[0x18];
5840 u8 syndrome[0x20];
5842 u8 reserved_at_40[0x40];
5846 u8 opcode[0x10];
5847 u8 reserved_at_10[0x10];
5849 u8 reserved_at_20[0x10];
5850 u8 op_mod[0x10];
5852 u8 modify_header_id[0x20];
5854 u8 reserved_at_60[0x20];
5858 u8 status[0x8];
5859 u8 reserved_at_8[0x18];
5861 u8 syndrome[0x20];
5863 u8 reserved_at_40[0x40];
5867 u8 reserved_at_280[0x180];
5871 u8 opcode[0x10];
5872 u8 reserved_at_10[0x10];
5874 u8 reserved_at_20[0x10];
5875 u8 op_mod[0x10];
5877 u8 reserved_at_40[0x8];
5878 u8 dctn[0x18];
5880 u8 reserved_at_60[0x20];
5884 u8 status[0x8];
5885 u8 reserved_at_8[0x18];
5887 u8 syndrome[0x20];
5889 u8 reserved_at_40[0x40];
5893 u8 reserved_at_280[0x600];
5895 u8 pas[][0x40];
5899 u8 opcode[0x10];
5900 u8 reserved_at_10[0x10];
5902 u8 reserved_at_20[0x10];
5903 u8 op_mod[0x10];
5905 u8 reserved_at_40[0x8];
5906 u8 cqn[0x18];
5908 u8 reserved_at_60[0x20];
5912 u8 status[0x8];
5913 u8 reserved_at_8[0x18];
5915 u8 syndrome[0x20];
5917 u8 reserved_at_40[0x20];
5919 u8 enable[0x1];
5920 u8 tag_enable[0x1];
5921 u8 reserved_at_62[0x1e];
5925 u8 opcode[0x10];
5926 u8 reserved_at_10[0x10];
5928 u8 reserved_at_20[0x10];
5929 u8 op_mod[0x10];
5931 u8 reserved_at_40[0x18];
5932 u8 priority[0x4];
5933 u8 cong_protocol[0x4];
5935 u8 reserved_at_60[0x20];
5939 u8 status[0x8];
5940 u8 reserved_at_8[0x18];
5942 u8 syndrome[0x20];
5944 u8 reserved_at_40[0x40];
5946 u8 rp_cur_flows[0x20];
5948 u8 sum_flows[0x20];
5950 u8 rp_cnp_ignored_high[0x20];
5952 u8 rp_cnp_ignored_low[0x20];
5954 u8 rp_cnp_handled_high[0x20];
5956 u8 rp_cnp_handled_low[0x20];
5958 u8 reserved_at_140[0x100];
5960 u8 time_stamp_high[0x20];
5962 u8 time_stamp_low[0x20];
5964 u8 accumulators_period[0x20];
5966 u8 np_ecn_marked_roce_packets_high[0x20];
5968 u8 np_ecn_marked_roce_packets_low[0x20];
5970 u8 np_cnp_sent_high[0x20];
5972 u8 np_cnp_sent_low[0x20];
5974 u8 reserved_at_320[0x560];
5978 u8 opcode[0x10];
5979 u8 reserved_at_10[0x10];
5981 u8 reserved_at_20[0x10];
5982 u8 op_mod[0x10];
5984 u8 clear[0x1];
5985 u8 reserved_at_41[0x1f];
5987 u8 reserved_at_60[0x20];
5991 u8 status[0x8];
5992 u8 reserved_at_8[0x18];
5994 u8 syndrome[0x20];
5996 u8 reserved_at_40[0x40];
6002 u8 opcode[0x10];
6003 u8 reserved_at_10[0x10];
6005 u8 reserved_at_20[0x10];
6006 u8 op_mod[0x10];
6008 u8 reserved_at_40[0x1c];
6009 u8 cong_protocol[0x4];
6011 u8 reserved_at_60[0x20];
6015 u8 status[0x8];
6016 u8 reserved_at_8[0x18];
6018 u8 syndrome[0x20];
6020 u8 reserved_at_40[0x40];
6026 u8 opcode[0x10];
6027 u8 reserved_at_10[0x10];
6029 u8 reserved_at_20[0x10];
6030 u8 op_mod[0x10];
6032 u8 reserved_at_40[0x40];
6036 u8 status[0x8];
6037 u8 reserved_at_8[0x18];
6039 u8 syndrome[0x20];
6041 u8 reserved_at_40[0x40];
6045 u8 opcode[0x10];
6046 u8 uid[0x10];
6048 u8 reserved_at_20[0x10];
6049 u8 op_mod[0x10];
6051 u8 reserved_at_40[0x8];
6052 u8 qpn[0x18];
6054 u8 reserved_at_60[0x20];
6058 u8 status[0x8];
6059 u8 reserved_at_8[0x18];
6061 u8 syndrome[0x20];
6063 u8 reserved_at_40[0x40];
6067 u8 opcode[0x10];
6068 u8 uid[0x10];
6070 u8 reserved_at_20[0x10];
6071 u8 op_mod[0x10];
6073 u8 reserved_at_40[0x8];
6074 u8 qpn[0x18];
6076 u8 reserved_at_60[0x20];
6080 u8 status[0x8];
6081 u8 reserved_at_8[0x18];
6083 u8 syndrome[0x20];
6085 u8 reserved_at_40[0x40];
6089 u8 opcode[0x10];
6090 u8 reserved_at_10[0x10];
6092 u8 reserved_at_20[0x10];
6093 u8 op_mod[0x10];
6095 u8 error[0x1];
6096 u8 reserved_at_41[0x4];
6097 u8 page_fault_type[0x3];
6098 u8 wq_number[0x18];
6100 u8 reserved_at_60[0x8];
6101 u8 token[0x18];
6105 u8 status[0x8];
6106 u8 reserved_at_8[0x18];
6108 u8 syndrome[0x20];
6110 u8 reserved_at_40[0x40];
6114 u8 opcode[0x10];
6115 u8 reserved_at_10[0x10];
6117 u8 reserved_at_20[0x10];
6118 u8 op_mod[0x10];
6120 u8 reserved_at_40[0x40];
6124 u8 status[0x8];
6125 u8 reserved_at_8[0x18];
6127 u8 syndrome[0x20];
6129 u8 reserved_at_40[0x40];
6133 u8 opcode[0x10];
6134 u8 reserved_at_10[0x10];
6136 u8 reserved_at_20[0x10];
6137 u8 op_mod[0x10];
6139 u8 other_vport[0x1];
6140 u8 reserved_at_41[0xf];
6141 u8 vport_number[0x10];
6143 u8 reserved_at_60[0x18];
6144 u8 admin_state[0x4];
6145 u8 reserved_at_7c[0x4];
6149 u8 status[0x8];
6150 u8 reserved_at_8[0x18];
6152 u8 syndrome[0x20];
6154 u8 reserved_at_40[0x40];
6158 u8 reserved_at_0[0x20];
6160 u8 reserved_at_20[0x1d];
6161 u8 lag_tx_port_affinity[0x1];
6162 u8 strict_lag_tx_port_affinity[0x1];
6163 u8 prio[0x1];
6167 u8 opcode[0x10];
6168 u8 uid[0x10];
6170 u8 reserved_at_20[0x10];
6171 u8 op_mod[0x10];
6173 u8 reserved_at_40[0x8];
6174 u8 tisn[0x18];
6176 u8 reserved_at_60[0x20];
6180 u8 reserved_at_c0[0x40];
6186 u8 reserved_at_0[0x20];
6188 u8 reserved_at_20[0x1b];
6189 u8 self_lb_en[0x1];
6190 u8 reserved_at_3c[0x1];
6191 u8 hash[0x1];
6192 u8 reserved_at_3e[0x1];
6193 u8 lro[0x1];
6197 u8 status[0x8];
6198 u8 reserved_at_8[0x18];
6200 u8 syndrome[0x20];
6202 u8 reserved_at_40[0x40];
6206 u8 opcode[0x10];
6207 u8 uid[0x10];
6209 u8 reserved_at_20[0x10];
6210 u8 op_mod[0x10];
6212 u8 reserved_at_40[0x8];
6213 u8 tirn[0x18];
6215 u8 reserved_at_60[0x20];
6219 u8 reserved_at_c0[0x40];
6225 u8 status[0x8];
6226 u8 reserved_at_8[0x18];
6228 u8 syndrome[0x20];
6230 u8 reserved_at_40[0x40];
6234 u8 opcode[0x10];
6235 u8 uid[0x10];
6237 u8 reserved_at_20[0x10];
6238 u8 op_mod[0x10];
6240 u8 sq_state[0x4];
6241 u8 reserved_at_44[0x4];
6242 u8 sqn[0x18];
6244 u8 reserved_at_60[0x20];
6246 u8 modify_bitmask[0x40];
6248 u8 reserved_at_c0[0x40];
6254 u8 status[0x8];
6255 u8 reserved_at_8[0x18];
6257 u8 syndrome[0x20];
6259 u8 reserved_at_40[0x1c0];
6263 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1,
6264 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2,
6268 u8 opcode[0x10];
6269 u8 reserved_at_10[0x10];
6271 u8 reserved_at_20[0x10];
6272 u8 op_mod[0x10];
6274 u8 scheduling_hierarchy[0x8];
6275 u8 reserved_at_48[0x18];
6277 u8 scheduling_element_id[0x20];
6279 u8 reserved_at_80[0x20];
6281 u8 modify_bitmask[0x20];
6283 u8 reserved_at_c0[0x40];
6287 u8 reserved_at_300[0x100];
6291 u8 status[0x8];
6292 u8 reserved_at_8[0x18];
6294 u8 syndrome[0x20];
6296 u8 reserved_at_40[0x40];
6300 u8 reserved_at_0[0x20];
6302 u8 reserved_at_20[0x1f];
6303 u8 rqn_list[0x1];
6307 u8 opcode[0x10];
6308 u8 uid[0x10];
6310 u8 reserved_at_20[0x10];
6311 u8 op_mod[0x10];
6313 u8 reserved_at_40[0x8];
6314 u8 rqtn[0x18];
6316 u8 reserved_at_60[0x20];
6320 u8 reserved_at_c0[0x40];
6326 u8 status[0x8];
6327 u8 reserved_at_8[0x18];
6329 u8 syndrome[0x20];
6331 u8 reserved_at_40[0x40];
6341 u8 opcode[0x10];
6342 u8 uid[0x10];
6344 u8 reserved_at_20[0x10];
6345 u8 op_mod[0x10];
6347 u8 rq_state[0x4];
6348 u8 reserved_at_44[0x4];
6349 u8 rqn[0x18];
6351 u8 reserved_at_60[0x20];
6353 u8 modify_bitmask[0x40];
6355 u8 reserved_at_c0[0x40];
6361 u8 status[0x8];
6362 u8 reserved_at_8[0x18];
6364 u8 syndrome[0x20];
6366 u8 reserved_at_40[0x40];
6370 u8 reserved_at_0[0x20];
6372 u8 reserved_at_20[0x1f];
6373 u8 lwm[0x1];
6377 u8 opcode[0x10];
6378 u8 uid[0x10];
6380 u8 reserved_at_20[0x10];
6381 u8 op_mod[0x10];
6383 u8 rmp_state[0x4];
6384 u8 reserved_at_44[0x4];
6385 u8 rmpn[0x18];
6387 u8 reserved_at_60[0x20];
6391 u8 reserved_at_c0[0x40];
6397 u8 status[0x8];
6398 u8 reserved_at_8[0x18];
6400 u8 syndrome[0x20];
6402 u8 reserved_at_40[0x40];
6406 u8 reserved_at_0[0x12];
6407 u8 affiliation[0x1];
6408 u8 reserved_at_13[0x1];
6409 u8 disable_uc_local_lb[0x1];
6410 u8 disable_mc_local_lb[0x1];
6411 u8 node_guid[0x1];
6412 u8 port_guid[0x1];
6413 u8 min_inline[0x1];
6414 u8 mtu[0x1];
6415 u8 change_event[0x1];
6416 u8 promisc[0x1];
6417 u8 permanent_address[0x1];
6418 u8 addresses_list[0x1];
6419 u8 roce_en[0x1];
6420 u8 reserved_at_1f[0x1];
6424 u8 opcode[0x10];
6425 u8 reserved_at_10[0x10];
6427 u8 reserved_at_20[0x10];
6428 u8 op_mod[0x10];
6430 u8 other_vport[0x1];
6431 u8 reserved_at_41[0xf];
6432 u8 vport_number[0x10];
6436 u8 reserved_at_80[0x780];
6442 u8 status[0x8];
6443 u8 reserved_at_8[0x18];
6445 u8 syndrome[0x20];
6447 u8 reserved_at_40[0x40];
6451 u8 opcode[0x10];
6452 u8 reserved_at_10[0x10];
6454 u8 reserved_at_20[0x10];
6455 u8 op_mod[0x10];
6457 u8 other_vport[0x1];
6458 u8 reserved_at_41[0xb];
6459 u8 port_num[0x4];
6460 u8 vport_number[0x10];
6462 u8 reserved_at_60[0x20];
6468 u8 status[0x8];
6469 u8 reserved_at_8[0x18];
6471 u8 syndrome[0x20];
6473 u8 reserved_at_40[0x40];
6477 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0,
6478 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1,
6482 u8 opcode[0x10];
6483 u8 uid[0x10];
6485 u8 reserved_at_20[0x10];
6486 u8 op_mod[0x10];
6488 u8 reserved_at_40[0x8];
6489 u8 cqn[0x18];
6495 u8 reserved_at_280[0x60];
6497 u8 cq_umem_valid[0x1];
6498 u8 reserved_at_2e1[0x1f];
6500 u8 reserved_at_300[0x580];
6502 u8 pas[][0x40];
6506 u8 status[0x8];
6507 u8 reserved_at_8[0x18];
6509 u8 syndrome[0x20];
6511 u8 reserved_at_40[0x40];
6515 u8 opcode[0x10];
6516 u8 reserved_at_10[0x10];
6518 u8 reserved_at_20[0x10];
6519 u8 op_mod[0x10];
6521 u8 reserved_at_40[0x18];
6522 u8 priority[0x4];
6523 u8 cong_protocol[0x4];
6525 u8 enable[0x1];
6526 u8 tag_enable[0x1];
6527 u8 reserved_at_62[0x1e];
6531 u8 status[0x8];
6532 u8 reserved_at_8[0x18];
6534 u8 syndrome[0x20];
6536 u8 reserved_at_40[0x40];
6540 u8 opcode[0x10];
6541 u8 reserved_at_10[0x10];
6543 u8 reserved_at_20[0x10];
6544 u8 op_mod[0x10];
6546 u8 reserved_at_40[0x1c];
6547 u8 cong_protocol[0x4];
6551 u8 reserved_at_80[0x80];
6557 u8 status[0x8];
6558 u8 reserved_at_8[0x18];
6560 u8 syndrome[0x20];
6562 u8 output_num_entries[0x20];
6564 u8 reserved_at_60[0x20];
6566 u8 pas[][0x40];
6570 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0,
6571 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1,
6572 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2,
6576 u8 opcode[0x10];
6577 u8 reserved_at_10[0x10];
6579 u8 reserved_at_20[0x10];
6580 u8 op_mod[0x10];
6582 u8 embedded_cpu_function[0x1];
6583 u8 reserved_at_41[0xf];
6584 u8 function_id[0x10];
6586 u8 input_num_entries[0x20];
6588 u8 pas[][0x40];
6592 u8 status[0x8];
6593 u8 reserved_at_8[0x18];
6595 u8 syndrome[0x20];
6597 u8 reserved_at_40[0x40];
6599 u8 response_mad_packet[256][0x8];
6603 u8 opcode[0x10];
6604 u8 reserved_at_10[0x10];
6606 u8 reserved_at_20[0x10];
6607 u8 op_mod[0x10];
6609 u8 remote_lid[0x10];
6610 u8 reserved_at_50[0x8];
6611 u8 port[0x8];
6613 u8 reserved_at_60[0x20];
6615 u8 mad[256][0x8];
6619 u8 status[0x8];
6620 u8 reserved_at_8[0x18];
6622 u8 syndrome[0x20];
6624 u8 reserved_at_40[0x40];
6628 u8 opcode[0x10];
6629 u8 reserved_at_10[0x10];
6631 u8 reserved_at_20[0x10];
6632 u8 op_mod[0x10];
6634 u8 reserved_at_40[0x40];
6635 u8 sw_owner_id[4][0x20];
6639 u8 status[0x8];
6640 u8 reserved_at_8[0x18];
6642 u8 syndrome[0x20];
6644 u8 reserved_at_40[0x20];
6645 u8 ece[0x20];
6649 u8 opcode[0x10];
6650 u8 uid[0x10];
6652 u8 reserved_at_20[0x10];
6653 u8 op_mod[0x10];
6655 u8 reserved_at_40[0x8];
6656 u8 qpn[0x18];
6658 u8 reserved_at_60[0x20];
6660 u8 opt_param_mask[0x20];
6662 u8 ece[0x20];
6666 u8 reserved_at_800[0x80];
6670 u8 status[0x8];
6671 u8 reserved_at_8[0x18];
6673 u8 syndrome[0x20];
6675 u8 reserved_at_40[0x20];
6676 u8 ece[0x20];
6680 u8 opcode[0x10];
6681 u8 uid[0x10];
6683 u8 reserved_at_20[0x10];
6684 u8 op_mod[0x10];
6686 u8 reserved_at_40[0x8];
6687 u8 qpn[0x18];
6689 u8 reserved_at_60[0x20];
6691 u8 opt_param_mask[0x20];
6693 u8 ece[0x20];
6697 u8 reserved_at_800[0x80];
6701 u8 status[0x8];
6702 u8 reserved_at_8[0x18];
6704 u8 syndrome[0x20];
6706 u8 reserved_at_40[0x40];
6708 u8 packet_headers_log[128][0x8];
6710 u8 packet_syndrome[64][0x8];
6714 u8 opcode[0x10];
6715 u8 reserved_at_10[0x10];
6717 u8 reserved_at_20[0x10];
6718 u8 op_mod[0x10];
6720 u8 reserved_at_40[0x40];
6724 u8 opcode[0x10];
6725 u8 reserved_at_10[0x10];
6727 u8 reserved_at_20[0x10];
6728 u8 op_mod[0x10];
6730 u8 reserved_at_40[0x18];
6731 u8 eq_number[0x8];
6733 u8 reserved_at_60[0x20];
6735 u8 eqe[64][0x8];
6739 u8 status[0x8];
6740 u8 reserved_at_8[0x18];
6742 u8 syndrome[0x20];
6744 u8 reserved_at_40[0x40];
6748 u8 status[0x8];
6749 u8 reserved_at_8[0x18];
6751 u8 syndrome[0x20];
6753 u8 reserved_at_40[0x20];
6757 u8 opcode[0x10];
6758 u8 reserved_at_10[0x10];
6760 u8 reserved_at_20[0x10];
6761 u8 op_mod[0x10];
6763 u8 embedded_cpu_function[0x1];
6764 u8 reserved_at_41[0xf];
6765 u8 function_id[0x10];
6767 u8 reserved_at_60[0x20];
6771 u8 status[0x8];
6772 u8 reserved_at_8[0x18];
6774 u8 syndrome[0x20];
6776 u8 reserved_at_40[0x40];
6780 u8 opcode[0x10];
6781 u8 uid[0x10];
6783 u8 reserved_at_20[0x10];
6784 u8 op_mod[0x10];
6786 u8 reserved_at_40[0x8];
6787 u8 dctn[0x18];
6789 u8 reserved_at_60[0x20];
6793 u8 status[0x8];
6794 u8 reserved_at_8[0x18];
6796 u8 syndrome[0x20];
6798 u8 reserved_at_40[0x20];
6802 u8 opcode[0x10];
6803 u8 reserved_at_10[0x10];
6805 u8 reserved_at_20[0x10];
6806 u8 op_mod[0x10];
6808 u8 embedded_cpu_function[0x1];
6809 u8 reserved_at_41[0xf];
6810 u8 function_id[0x10];
6812 u8 reserved_at_60[0x20];
6816 u8 status[0x8];
6817 u8 reserved_at_8[0x18];
6819 u8 syndrome[0x20];
6821 u8 reserved_at_40[0x40];
6825 u8 opcode[0x10];
6826 u8 uid[0x10];
6828 u8 reserved_at_20[0x10];
6829 u8 op_mod[0x10];
6831 u8 reserved_at_40[0x8];
6832 u8 qpn[0x18];
6834 u8 reserved_at_60[0x20];
6836 u8 multicast_gid[16][0x8];
6840 u8 status[0x8];
6841 u8 reserved_at_8[0x18];
6843 u8 syndrome[0x20];
6845 u8 reserved_at_40[0x40];
6849 u8 opcode[0x10];
6850 u8 uid[0x10];
6852 u8 reserved_at_20[0x10];
6853 u8 op_mod[0x10];
6855 u8 reserved_at_40[0x8];
6856 u8 xrqn[0x18];
6858 u8 reserved_at_60[0x20];
6862 u8 status[0x8];
6863 u8 reserved_at_8[0x18];
6865 u8 syndrome[0x20];
6867 u8 reserved_at_40[0x40];
6871 u8 opcode[0x10];
6872 u8 uid[0x10];
6874 u8 reserved_at_20[0x10];
6875 u8 op_mod[0x10];
6877 u8 reserved_at_40[0x8];
6878 u8 xrc_srqn[0x18];
6880 u8 reserved_at_60[0x20];
6884 u8 status[0x8];
6885 u8 reserved_at_8[0x18];
6887 u8 syndrome[0x20];
6889 u8 reserved_at_40[0x40];
6893 u8 opcode[0x10];
6894 u8 uid[0x10];
6896 u8 reserved_at_20[0x10];
6897 u8 op_mod[0x10];
6899 u8 reserved_at_40[0x8];
6900 u8 tisn[0x18];
6902 u8 reserved_at_60[0x20];
6906 u8 status[0x8];
6907 u8 reserved_at_8[0x18];
6909 u8 syndrome[0x20];
6911 u8 reserved_at_40[0x40];
6915 u8 opcode[0x10];
6916 u8 uid[0x10];
6918 u8 reserved_at_20[0x10];
6919 u8 op_mod[0x10];
6921 u8 reserved_at_40[0x8];
6922 u8 tirn[0x18];
6924 u8 reserved_at_60[0x20];
6928 u8 status[0x8];
6929 u8 reserved_at_8[0x18];
6931 u8 syndrome[0x20];
6933 u8 reserved_at_40[0x40];
6937 u8 opcode[0x10];
6938 u8 uid[0x10];
6940 u8 reserved_at_20[0x10];
6941 u8 op_mod[0x10];
6943 u8 reserved_at_40[0x8];
6944 u8 srqn[0x18];
6946 u8 reserved_at_60[0x20];
6950 u8 status[0x8];
6951 u8 reserved_at_8[0x18];
6953 u8 syndrome[0x20];
6955 u8 reserved_at_40[0x40];
6959 u8 opcode[0x10];
6960 u8 uid[0x10];
6962 u8 reserved_at_20[0x10];
6963 u8 op_mod[0x10];
6965 u8 reserved_at_40[0x8];
6966 u8 sqn[0x18];
6968 u8 reserved_at_60[0x20];
6972 u8 status[0x8];
6973 u8 reserved_at_8[0x18];
6975 u8 syndrome[0x20];
6977 u8 reserved_at_40[0x1c0];
6981 u8 opcode[0x10];
6982 u8 reserved_at_10[0x10];
6984 u8 reserved_at_20[0x10];
6985 u8 op_mod[0x10];
6987 u8 scheduling_hierarchy[0x8];
6988 u8 reserved_at_48[0x18];
6990 u8 scheduling_element_id[0x20];
6992 u8 reserved_at_80[0x180];
6996 u8 status[0x8];
6997 u8 reserved_at_8[0x18];
6999 u8 syndrome[0x20];
7001 u8 reserved_at_40[0x40];
7005 u8 opcode[0x10];
7006 u8 uid[0x10];
7008 u8 reserved_at_20[0x10];
7009 u8 op_mod[0x10];
7011 u8 reserved_at_40[0x8];
7012 u8 rqtn[0x18];
7014 u8 reserved_at_60[0x20];
7018 u8 status[0x8];
7019 u8 reserved_at_8[0x18];
7021 u8 syndrome[0x20];
7023 u8 reserved_at_40[0x40];
7027 u8 opcode[0x10];
7028 u8 uid[0x10];
7030 u8 reserved_at_20[0x10];
7031 u8 op_mod[0x10];
7033 u8 reserved_at_40[0x8];
7034 u8 rqn[0x18];
7036 u8 reserved_at_60[0x20];
7040 u8 opcode[0x10];
7041 u8 reserved_at_10[0x10];
7043 u8 reserved_at_20[0x10];
7044 u8 op_mod[0x10];
7046 u8 reserved_at_40[0x20];
7048 u8 reserved_at_60[0x10];
7049 u8 delay_drop_timeout[0x10];
7053 u8 status[0x8];
7054 u8 reserved_at_8[0x18];
7056 u8 syndrome[0x20];
7058 u8 reserved_at_40[0x40];
7062 u8 status[0x8];
7063 u8 reserved_at_8[0x18];
7065 u8 syndrome[0x20];
7067 u8 reserved_at_40[0x40];
7071 u8 opcode[0x10];
7072 u8 uid[0x10];
7074 u8 reserved_at_20[0x10];
7075 u8 op_mod[0x10];
7077 u8 reserved_at_40[0x8];
7078 u8 rmpn[0x18];
7080 u8 reserved_at_60[0x20];
7084 u8 status[0x8];
7085 u8 reserved_at_8[0x18];
7087 u8 syndrome[0x20];
7089 u8 reserved_at_40[0x40];
7093 u8 opcode[0x10];
7094 u8 uid[0x10];
7096 u8 reserved_at_20[0x10];
7097 u8 op_mod[0x10];
7099 u8 reserved_at_40[0x8];
7100 u8 qpn[0x18];
7102 u8 reserved_at_60[0x20];
7106 u8 status[0x8];
7107 u8 reserved_at_8[0x18];
7109 u8 syndrome[0x20];
7111 u8 reserved_at_40[0x40];
7115 u8 opcode[0x10];
7116 u8 reserved_at_10[0x10];
7118 u8 reserved_at_20[0x10];
7119 u8 op_mod[0x10];
7121 u8 reserved_at_40[0x8];
7122 u8 psvn[0x18];
7124 u8 reserved_at_60[0x20];
7128 u8 status[0x8];
7129 u8 reserved_at_8[0x18];
7131 u8 syndrome[0x20];
7133 u8 reserved_at_40[0x40];
7137 u8 opcode[0x10];
7138 u8 uid[0x10];
7140 u8 reserved_at_20[0x10];
7141 u8 op_mod[0x10];
7143 u8 reserved_at_40[0x8];
7144 u8 mkey_index[0x18];
7146 u8 reserved_at_60[0x20];
7150 u8 status[0x8];
7151 u8 reserved_at_8[0x18];
7153 u8 syndrome[0x20];
7155 u8 reserved_at_40[0x40];
7159 u8 opcode[0x10];
7160 u8 reserved_at_10[0x10];
7162 u8 reserved_at_20[0x10];
7163 u8 op_mod[0x10];
7165 u8 other_vport[0x1];
7166 u8 reserved_at_41[0xf];
7167 u8 vport_number[0x10];
7169 u8 reserved_at_60[0x20];
7171 u8 table_type[0x8];
7172 u8 reserved_at_88[0x18];
7174 u8 reserved_at_a0[0x8];
7175 u8 table_id[0x18];
7177 u8 reserved_at_c0[0x140];
7181 u8 status[0x8];
7182 u8 reserved_at_8[0x18];
7184 u8 syndrome[0x20];
7186 u8 reserved_at_40[0x40];
7190 u8 opcode[0x10];
7191 u8 reserved_at_10[0x10];
7193 u8 reserved_at_20[0x10];
7194 u8 op_mod[0x10];
7196 u8 other_vport[0x1];
7197 u8 reserved_at_41[0xf];
7198 u8 vport_number[0x10];
7200 u8 reserved_at_60[0x20];
7202 u8 table_type[0x8];
7203 u8 reserved_at_88[0x18];
7205 u8 reserved_at_a0[0x8];
7206 u8 table_id[0x18];
7208 u8 group_id[0x20];
7210 u8 reserved_at_e0[0x120];
7214 u8 status[0x8];
7215 u8 reserved_at_8[0x18];
7217 u8 syndrome[0x20];
7219 u8 reserved_at_40[0x40];
7223 u8 opcode[0x10];
7224 u8 reserved_at_10[0x10];
7226 u8 reserved_at_20[0x10];
7227 u8 op_mod[0x10];
7229 u8 reserved_at_40[0x18];
7230 u8 eq_number[0x8];
7232 u8 reserved_at_60[0x20];
7236 u8 status[0x8];
7237 u8 reserved_at_8[0x18];
7239 u8 syndrome[0x20];
7241 u8 reserved_at_40[0x40];
7245 u8 opcode[0x10];
7246 u8 uid[0x10];
7248 u8 reserved_at_20[0x10];
7249 u8 op_mod[0x10];
7251 u8 reserved_at_40[0x8];
7252 u8 dctn[0x18];
7254 u8 reserved_at_60[0x20];
7258 u8 status[0x8];
7259 u8 reserved_at_8[0x18];
7261 u8 syndrome[0x20];
7263 u8 reserved_at_40[0x40];
7267 u8 opcode[0x10];
7268 u8 uid[0x10];
7270 u8 reserved_at_20[0x10];
7271 u8 op_mod[0x10];
7273 u8 reserved_at_40[0x8];
7274 u8 cqn[0x18];
7276 u8 reserved_at_60[0x20];
7280 u8 status[0x8];
7281 u8 reserved_at_8[0x18];
7283 u8 syndrome[0x20];
7285 u8 reserved_at_40[0x40];
7289 u8 opcode[0x10];
7290 u8 reserved_at_10[0x10];
7292 u8 reserved_at_20[0x10];
7293 u8 op_mod[0x10];
7295 u8 reserved_at_40[0x20];
7297 u8 reserved_at_60[0x10];
7298 u8 vxlan_udp_port[0x10];
7302 u8 status[0x8];
7303 u8 reserved_at_8[0x18];
7305 u8 syndrome[0x20];
7307 u8 reserved_at_40[0x40];
7311 u8 opcode[0x10];
7312 u8 reserved_at_10[0x10];
7314 u8 reserved_at_20[0x10];
7315 u8 op_mod[0x10];
7317 u8 reserved_at_40[0x60];
7319 u8 reserved_at_a0[0x8];
7320 u8 table_index[0x18];
7322 u8 reserved_at_c0[0x140];
7326 u8 status[0x8];
7327 u8 reserved_at_8[0x18];
7329 u8 syndrome[0x20];
7331 u8 reserved_at_40[0x40];
7335 u8 opcode[0x10];
7336 u8 reserved_at_10[0x10];
7338 u8 reserved_at_20[0x10];
7339 u8 op_mod[0x10];
7341 u8 other_vport[0x1];
7342 u8 reserved_at_41[0xf];
7343 u8 vport_number[0x10];
7345 u8 reserved_at_60[0x20];
7347 u8 table_type[0x8];
7348 u8 reserved_at_88[0x18];
7350 u8 reserved_at_a0[0x8];
7351 u8 table_id[0x18];
7353 u8 reserved_at_c0[0x40];
7355 u8 flow_index[0x20];
7357 u8 reserved_at_120[0xe0];
7361 u8 status[0x8];
7362 u8 reserved_at_8[0x18];
7364 u8 syndrome[0x20];
7366 u8 reserved_at_40[0x40];
7370 u8 opcode[0x10];
7371 u8 uid[0x10];
7373 u8 reserved_at_20[0x10];
7374 u8 op_mod[0x10];
7376 u8 reserved_at_40[0x8];
7377 u8 xrcd[0x18];
7379 u8 reserved_at_60[0x20];
7383 u8 status[0x8];
7384 u8 reserved_at_8[0x18];
7386 u8 syndrome[0x20];
7388 u8 reserved_at_40[0x40];
7392 u8 opcode[0x10];
7393 u8 reserved_at_10[0x10];
7395 u8 reserved_at_20[0x10];
7396 u8 op_mod[0x10];
7398 u8 reserved_at_40[0x8];
7399 u8 uar[0x18];
7401 u8 reserved_at_60[0x20];
7405 u8 status[0x8];
7406 u8 reserved_at_8[0x18];
7408 u8 syndrome[0x20];
7410 u8 reserved_at_40[0x40];
7414 u8 opcode[0x10];
7415 u8 uid[0x10];
7417 u8 reserved_at_20[0x10];
7418 u8 op_mod[0x10];
7420 u8 reserved_at_40[0x8];
7421 u8 transport_domain[0x18];
7423 u8 reserved_at_60[0x20];
7427 u8 status[0x8];
7428 u8 reserved_at_8[0x18];
7430 u8 syndrome[0x20];
7432 u8 reserved_at_40[0x40];
7436 u8 opcode[0x10];
7437 u8 reserved_at_10[0x10];
7439 u8 reserved_at_20[0x10];
7440 u8 op_mod[0x10];
7442 u8 reserved_at_40[0x18];
7443 u8 counter_set_id[0x8];
7445 u8 reserved_at_60[0x20];
7449 u8 status[0x8];
7450 u8 reserved_at_8[0x18];
7452 u8 syndrome[0x20];
7454 u8 reserved_at_40[0x40];
7458 u8 opcode[0x10];
7459 u8 uid[0x10];
7461 u8 reserved_at_20[0x10];
7462 u8 op_mod[0x10];
7464 u8 reserved_at_40[0x8];
7465 u8 pd[0x18];
7467 u8 reserved_at_60[0x20];
7471 u8 status[0x8];
7472 u8 reserved_at_8[0x18];
7474 u8 syndrome[0x20];
7476 u8 reserved_at_40[0x40];
7480 u8 opcode[0x10];
7481 u8 reserved_at_10[0x10];
7483 u8 reserved_at_20[0x10];
7484 u8 op_mod[0x10];
7486 u8 flow_counter_id[0x20];
7488 u8 reserved_at_60[0x20];
7492 u8 status[0x8];
7493 u8 reserved_at_8[0x18];
7495 u8 syndrome[0x20];
7497 u8 reserved_at_40[0x8];
7498 u8 xrqn[0x18];
7500 u8 reserved_at_60[0x20];
7504 u8 opcode[0x10];
7505 u8 uid[0x10];
7507 u8 reserved_at_20[0x10];
7508 u8 op_mod[0x10];
7510 u8 reserved_at_40[0x40];
7516 u8 status[0x8];
7517 u8 reserved_at_8[0x18];
7519 u8 syndrome[0x20];
7521 u8 reserved_at_40[0x8];
7522 u8 xrc_srqn[0x18];
7524 u8 reserved_at_60[0x20];
7528 u8 opcode[0x10];
7529 u8 uid[0x10];
7531 u8 reserved_at_20[0x10];
7532 u8 op_mod[0x10];
7534 u8 reserved_at_40[0x40];
7538 u8 reserved_at_280[0x60];
7540 u8 xrc_srq_umem_valid[0x1];
7541 u8 reserved_at_2e1[0x1f];
7543 u8 reserved_at_300[0x580];
7545 u8 pas[][0x40];
7549 u8 status[0x8];
7550 u8 reserved_at_8[0x18];
7552 u8 syndrome[0x20];
7554 u8 reserved_at_40[0x8];
7555 u8 tisn[0x18];
7557 u8 reserved_at_60[0x20];
7561 u8 opcode[0x10];
7562 u8 uid[0x10];
7564 u8 reserved_at_20[0x10];
7565 u8 op_mod[0x10];
7567 u8 reserved_at_40[0xc0];
7573 u8 status[0x8];
7574 u8 icm_address_63_40[0x18];
7576 u8 syndrome[0x20];
7578 u8 icm_address_39_32[0x8];
7579 u8 tirn[0x18];
7581 u8 icm_address_31_0[0x20];
7585 u8 opcode[0x10];
7586 u8 uid[0x10];
7588 u8 reserved_at_20[0x10];
7589 u8 op_mod[0x10];
7591 u8 reserved_at_40[0xc0];
7597 u8 status[0x8];
7598 u8 reserved_at_8[0x18];
7600 u8 syndrome[0x20];
7602 u8 reserved_at_40[0x8];
7603 u8 srqn[0x18];
7605 u8 reserved_at_60[0x20];
7609 u8 opcode[0x10];
7610 u8 uid[0x10];
7612 u8 reserved_at_20[0x10];
7613 u8 op_mod[0x10];
7615 u8 reserved_at_40[0x40];
7619 u8 reserved_at_280[0x600];
7621 u8 pas[][0x40];
7625 u8 status[0x8];
7626 u8 reserved_at_8[0x18];
7628 u8 syndrome[0x20];
7630 u8 reserved_at_40[0x8];
7631 u8 sqn[0x18];
7633 u8 reserved_at_60[0x20];
7637 u8 opcode[0x10];
7638 u8 uid[0x10];
7640 u8 reserved_at_20[0x10];
7641 u8 op_mod[0x10];
7643 u8 reserved_at_40[0xc0];
7649 u8 status[0x8];
7650 u8 reserved_at_8[0x18];
7652 u8 syndrome[0x20];
7654 u8 reserved_at_40[0x40];
7656 u8 scheduling_element_id[0x20];
7658 u8 reserved_at_a0[0x160];
7662 u8 opcode[0x10];
7663 u8 reserved_at_10[0x10];
7665 u8 reserved_at_20[0x10];
7666 u8 op_mod[0x10];
7668 u8 scheduling_hierarchy[0x8];
7669 u8 reserved_at_48[0x18];
7671 u8 reserved_at_60[0xa0];
7675 u8 reserved_at_300[0x100];
7679 u8 status[0x8];
7680 u8 reserved_at_8[0x18];
7682 u8 syndrome[0x20];
7684 u8 reserved_at_40[0x8];
7685 u8 rqtn[0x18];
7687 u8 reserved_at_60[0x20];
7691 u8 opcode[0x10];
7692 u8 uid[0x10];
7694 u8 reserved_at_20[0x10];
7695 u8 op_mod[0x10];
7697 u8 reserved_at_40[0xc0];
7703 u8 status[0x8];
7704 u8 reserved_at_8[0x18];
7706 u8 syndrome[0x20];
7708 u8 reserved_at_40[0x8];
7709 u8 rqn[0x18];
7711 u8 reserved_at_60[0x20];
7715 u8 opcode[0x10];
7716 u8 uid[0x10];
7718 u8 reserved_at_20[0x10];
7719 u8 op_mod[0x10];
7721 u8 reserved_at_40[0xc0];
7727 u8 status[0x8];
7728 u8 reserved_at_8[0x18];
7730 u8 syndrome[0x20];
7732 u8 reserved_at_40[0x8];
7733 u8 rmpn[0x18];
7735 u8 reserved_at_60[0x20];
7739 u8 opcode[0x10];
7740 u8 uid[0x10];
7742 u8 reserved_at_20[0x10];
7743 u8 op_mod[0x10];
7745 u8 reserved_at_40[0xc0];
7751 u8 status[0x8];
7752 u8 reserved_at_8[0x18];
7754 u8 syndrome[0x20];
7756 u8 reserved_at_40[0x8];
7757 u8 qpn[0x18];
7759 u8 ece[0x20];
7763 u8 opcode[0x10];
7764 u8 uid[0x10];
7766 u8 reserved_at_20[0x10];
7767 u8 op_mod[0x10];
7769 u8 reserved_at_40[0x8];
7770 u8 input_qpn[0x18];
7772 u8 reserved_at_60[0x20];
7773 u8 opt_param_mask[0x20];
7775 u8 ece[0x20];
7779 u8 reserved_at_800[0x60];
7781 u8 wq_umem_valid[0x1];
7782 u8 reserved_at_861[0x1f];
7784 u8 pas[][0x40];
7788 u8 status[0x8];
7789 u8 reserved_at_8[0x18];
7791 u8 syndrome[0x20];
7793 u8 reserved_at_40[0x40];
7795 u8 reserved_at_80[0x8];
7796 u8 psv0_index[0x18];
7798 u8 reserved_at_a0[0x8];
7799 u8 psv1_index[0x18];
7801 u8 reserved_at_c0[0x8];
7802 u8 psv2_index[0x18];
7804 u8 reserved_at_e0[0x8];
7805 u8 psv3_index[0x18];
7809 u8 opcode[0x10];
7810 u8 reserved_at_10[0x10];
7812 u8 reserved_at_20[0x10];
7813 u8 op_mod[0x10];
7815 u8 num_psv[0x4];
7816 u8 reserved_at_44[0x4];
7817 u8 pd[0x18];
7819 u8 reserved_at_60[0x20];
7823 u8 status[0x8];
7824 u8 reserved_at_8[0x18];
7826 u8 syndrome[0x20];
7828 u8 reserved_at_40[0x8];
7829 u8 mkey_index[0x18];
7831 u8 reserved_at_60[0x20];
7835 u8 opcode[0x10];
7836 u8 uid[0x10];
7838 u8 reserved_at_20[0x10];
7839 u8 op_mod[0x10];
7841 u8 reserved_at_40[0x20];
7843 u8 pg_access[0x1];
7844 u8 mkey_umem_valid[0x1];
7845 u8 reserved_at_62[0x1e];
7849 u8 reserved_at_280[0x80];
7851 u8 translations_octword_actual_size[0x20];
7853 u8 reserved_at_320[0x560];
7855 u8 klm_pas_mtt[][0x20];
7859 MLX5_FLOW_TABLE_TYPE_NIC_RX = 0x0,
7860 MLX5_FLOW_TABLE_TYPE_NIC_TX = 0x1,
7861 MLX5_FLOW_TABLE_TYPE_ESW_EGRESS_ACL = 0x2,
7862 MLX5_FLOW_TABLE_TYPE_ESW_INGRESS_ACL = 0x3,
7863 MLX5_FLOW_TABLE_TYPE_FDB = 0X4,
7864 MLX5_FLOW_TABLE_TYPE_SNIFFER_RX = 0X5,
7865 MLX5_FLOW_TABLE_TYPE_SNIFFER_TX = 0X6,
7869 u8 status[0x8];
7870 u8 icm_address_63_40[0x18];
7872 u8 syndrome[0x20];
7874 u8 icm_address_39_32[0x8];
7875 u8 table_id[0x18];
7877 u8 icm_address_31_0[0x20];
7881 u8 opcode[0x10];
7882 u8 reserved_at_10[0x10];
7884 u8 reserved_at_20[0x10];
7885 u8 op_mod[0x10];
7887 u8 other_vport[0x1];
7888 u8 reserved_at_41[0xf];
7889 u8 vport_number[0x10];
7891 u8 reserved_at_60[0x20];
7893 u8 table_type[0x8];
7894 u8 reserved_at_88[0x18];
7896 u8 reserved_at_a0[0x20];
7902 u8 status[0x8];
7903 u8 reserved_at_8[0x18];
7905 u8 syndrome[0x20];
7907 u8 reserved_at_40[0x8];
7908 u8 group_id[0x18];
7910 u8 reserved_at_60[0x20];
7914 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
7915 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
7916 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
7917 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3,
7921 u8 opcode[0x10];
7922 u8 reserved_at_10[0x10];
7924 u8 reserved_at_20[0x10];
7925 u8 op_mod[0x10];
7927 u8 other_vport[0x1];
7928 u8 reserved_at_41[0xf];
7929 u8 vport_number[0x10];
7931 u8 reserved_at_60[0x20];
7933 u8 table_type[0x8];
7934 u8 reserved_at_88[0x18];
7936 u8 reserved_at_a0[0x8];
7937 u8 table_id[0x18];
7939 u8 source_eswitch_owner_vhca_id_valid[0x1];
7941 u8 reserved_at_c1[0x1f];
7943 u8 start_flow_index[0x20];
7945 u8 reserved_at_100[0x20];
7947 u8 end_flow_index[0x20];
7949 u8 reserved_at_140[0xa0];
7951 u8 reserved_at_1e0[0x18];
7952 u8 match_criteria_enable[0x8];
7956 u8 reserved_at_1200[0xe00];
7960 u8 status[0x8];
7961 u8 reserved_at_8[0x18];
7963 u8 syndrome[0x20];
7965 u8 reserved_at_40[0x18];
7966 u8 eq_number[0x8];
7968 u8 reserved_at_60[0x20];
7972 u8 opcode[0x10];
7973 u8 uid[0x10];
7975 u8 reserved_at_20[0x10];
7976 u8 op_mod[0x10];
7978 u8 reserved_at_40[0x40];
7982 u8 reserved_at_280[0x40];
7984 u8 event_bitmask[4][0x40];
7986 u8 reserved_at_3c0[0x4c0];
7988 u8 pas[][0x40];
7992 u8 status[0x8];
7993 u8 reserved_at_8[0x18];
7995 u8 syndrome[0x20];
7997 u8 reserved_at_40[0x8];
7998 u8 dctn[0x18];
8000 u8 ece[0x20];
8004 u8 opcode[0x10];
8005 u8 uid[0x10];
8007 u8 reserved_at_20[0x10];
8008 u8 op_mod[0x10];
8010 u8 reserved_at_40[0x40];
8014 u8 reserved_at_280[0x180];
8018 u8 status[0x8];
8019 u8 reserved_at_8[0x18];
8021 u8 syndrome[0x20];
8023 u8 reserved_at_40[0x8];
8024 u8 cqn[0x18];
8026 u8 reserved_at_60[0x20];
8030 u8 opcode[0x10];
8031 u8 uid[0x10];
8033 u8 reserved_at_20[0x10];
8034 u8 op_mod[0x10];
8036 u8 reserved_at_40[0x40];
8040 u8 reserved_at_280[0x60];
8042 u8 cq_umem_valid[0x1];
8043 u8 reserved_at_2e1[0x59f];
8045 u8 pas[][0x40];
8049 u8 status[0x8];
8050 u8 reserved_at_8[0x18];
8052 u8 syndrome[0x20];
8054 u8 reserved_at_40[0x4];
8055 u8 min_delay[0xc];
8056 u8 int_vector[0x10];
8058 u8 reserved_at_60[0x20];
8062 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0,
8063 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1,
8067 u8 opcode[0x10];
8068 u8 reserved_at_10[0x10];
8070 u8 reserved_at_20[0x10];
8071 u8 op_mod[0x10];
8073 u8 reserved_at_40[0x4];
8074 u8 min_delay[0xc];
8075 u8 int_vector[0x10];
8077 u8 reserved_at_60[0x20];
8081 u8 status[0x8];
8082 u8 reserved_at_8[0x18];
8084 u8 syndrome[0x20];
8086 u8 reserved_at_40[0x40];
8090 u8 opcode[0x10];
8091 u8 uid[0x10];
8093 u8 reserved_at_20[0x10];
8094 u8 op_mod[0x10];
8096 u8 reserved_at_40[0x8];
8097 u8 qpn[0x18];
8099 u8 reserved_at_60[0x20];
8101 u8 multicast_gid[16][0x8];
8105 u8 status[0x8];
8106 u8 reserved_at_8[0x18];
8108 u8 syndrome[0x20];
8110 u8 reserved_at_40[0x40];
8114 u8 opcode[0x10];
8115 u8 reserved_at_10[0x10];
8117 u8 reserved_at_20[0x10];
8118 u8 op_mod[0x10];
8120 u8 reserved_at_40[0x8];
8121 u8 xrqn[0x18];
8123 u8 reserved_at_60[0x10];
8124 u8 lwm[0x10];
8128 u8 status[0x8];
8129 u8 reserved_at_8[0x18];
8131 u8 syndrome[0x20];
8133 u8 reserved_at_40[0x40];
8137 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1,
8141 u8 opcode[0x10];
8142 u8 uid[0x10];
8144 u8 reserved_at_20[0x10];
8145 u8 op_mod[0x10];
8147 u8 reserved_at_40[0x8];
8148 u8 xrc_srqn[0x18];
8150 u8 reserved_at_60[0x10];
8151 u8 lwm[0x10];
8155 u8 status[0x8];
8156 u8 reserved_at_8[0x18];
8158 u8 syndrome[0x20];
8160 u8 reserved_at_40[0x40];
8164 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1,
8165 MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2,
8169 u8 opcode[0x10];
8170 u8 uid[0x10];
8172 u8 reserved_at_20[0x10];
8173 u8 op_mod[0x10];
8175 u8 reserved_at_40[0x8];
8176 u8 srq_number[0x18];
8178 u8 reserved_at_60[0x10];
8179 u8 lwm[0x10];
8183 u8 status[0x8];
8184 u8 reserved_at_8[0x18];
8186 u8 syndrome[0x20];
8188 u8 reserved_at_40[0x40];
8192 u8 opcode[0x10];
8193 u8 reserved_at_10[0x10];
8195 u8 reserved_at_20[0x10];
8196 u8 op_mod[0x10];
8198 u8 reserved_at_40[0x8];
8199 u8 dct_number[0x18];
8201 u8 reserved_at_60[0x20];
8205 u8 status[0x8];
8206 u8 reserved_at_8[0x18];
8208 u8 syndrome[0x20];
8210 u8 reserved_at_40[0x8];
8211 u8 xrcd[0x18];
8213 u8 reserved_at_60[0x20];
8217 u8 opcode[0x10];
8218 u8 uid[0x10];
8220 u8 reserved_at_20[0x10];
8221 u8 op_mod[0x10];
8223 u8 reserved_at_40[0x40];
8227 u8 status[0x8];
8228 u8 reserved_at_8[0x18];
8230 u8 syndrome[0x20];
8232 u8 reserved_at_40[0x8];
8233 u8 uar[0x18];
8235 u8 reserved_at_60[0x20];
8239 u8 opcode[0x10];
8240 u8 reserved_at_10[0x10];
8242 u8 reserved_at_20[0x10];
8243 u8 op_mod[0x10];
8245 u8 reserved_at_40[0x40];
8249 u8 status[0x8];
8250 u8 reserved_at_8[0x18];
8252 u8 syndrome[0x20];
8254 u8 reserved_at_40[0x8];
8255 u8 transport_domain[0x18];
8257 u8 reserved_at_60[0x20];
8261 u8 opcode[0x10];
8262 u8 uid[0x10];
8264 u8 reserved_at_20[0x10];
8265 u8 op_mod[0x10];
8267 u8 reserved_at_40[0x40];
8271 u8 status[0x8];
8272 u8 reserved_at_8[0x18];
8274 u8 syndrome[0x20];
8276 u8 reserved_at_40[0x18];
8277 u8 counter_set_id[0x8];
8279 u8 reserved_at_60[0x20];
8283 u8 opcode[0x10];
8284 u8 uid[0x10];
8286 u8 reserved_at_20[0x10];
8287 u8 op_mod[0x10];
8289 u8 reserved_at_40[0x40];
8293 u8 status[0x8];
8294 u8 reserved_at_8[0x18];
8296 u8 syndrome[0x20];
8298 u8 reserved_at_40[0x8];
8299 u8 pd[0x18];
8301 u8 reserved_at_60[0x20];
8305 u8 opcode[0x10];
8306 u8 uid[0x10];
8308 u8 reserved_at_20[0x10];
8309 u8 op_mod[0x10];
8311 u8 reserved_at_40[0x40];
8315 u8 status[0x8];
8316 u8 reserved_at_8[0x18];
8318 u8 syndrome[0x20];
8320 u8 flow_counter_id[0x20];
8322 u8 reserved_at_60[0x20];
8326 u8 opcode[0x10];
8327 u8 reserved_at_10[0x10];
8329 u8 reserved_at_20[0x10];
8330 u8 op_mod[0x10];
8332 u8 reserved_at_40[0x38];
8333 u8 flow_counter_bulk[0x8];
8337 u8 status[0x8];
8338 u8 reserved_at_8[0x18];
8340 u8 syndrome[0x20];
8342 u8 reserved_at_40[0x40];
8346 u8 opcode[0x10];
8347 u8 reserved_at_10[0x10];
8349 u8 reserved_at_20[0x10];
8350 u8 op_mod[0x10];
8352 u8 reserved_at_40[0x20];
8354 u8 reserved_at_60[0x10];
8355 u8 vxlan_udp_port[0x10];
8359 u8 status[0x8];
8360 u8 reserved_at_8[0x18];
8362 u8 syndrome[0x20];
8364 u8 reserved_at_40[0x40];
8368 u8 rate_limit[0x20];
8370 u8 burst_upper_bound[0x20];
8372 u8 reserved_at_40[0x10];
8373 u8 typical_packet_size[0x10];
8375 u8 reserved_at_60[0x120];
8379 u8 opcode[0x10];
8380 u8 uid[0x10];
8382 u8 reserved_at_20[0x10];
8383 u8 op_mod[0x10];
8385 u8 reserved_at_40[0x10];
8386 u8 rate_limit_index[0x10];
8388 u8 reserved_at_60[0x20];
8394 u8 status[0x8];
8395 u8 reserved_at_8[0x18];
8397 u8 syndrome[0x20];
8399 u8 reserved_at_40[0x40];
8401 u8 register_data[][0x20];
8405 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0,
8406 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1,
8410 u8 opcode[0x10];
8411 u8 reserved_at_10[0x10];
8413 u8 reserved_at_20[0x10];
8414 u8 op_mod[0x10];
8416 u8 reserved_at_40[0x10];
8417 u8 register_id[0x10];
8419 u8 argument[0x20];
8421 u8 register_data[][0x20];
8425 u8 status[0x4];
8426 u8 version[0x4];
8427 u8 local_port[0x8];
8428 u8 pnat[0x2];
8429 u8 reserved_at_12[0x2];
8430 u8 lane[0x4];
8431 u8 reserved_at_18[0x8];
8433 u8 reserved_at_20[0x20];
8435 u8 reserved_at_40[0x7];
8436 u8 polarity[0x1];
8437 u8 ob_tap0[0x8];
8438 u8 ob_tap1[0x8];
8439 u8 ob_tap2[0x8];
8441 u8 reserved_at_60[0xc];
8442 u8 ob_preemp_mode[0x4];
8443 u8 ob_reg[0x8];
8444 u8 ob_bias[0x8];
8446 u8 reserved_at_80[0x20];
8450 u8 status[0x4];
8451 u8 version[0x4];
8452 u8 local_port[0x8];
8453 u8 pnat[0x2];
8454 u8 reserved_at_12[0x2];
8455 u8 lane[0x4];
8456 u8 reserved_at_18[0x8];
8458 u8 time_to_link_up[0x10];
8459 u8 reserved_at_30[0xc];
8460 u8 grade_lane_speed[0x4];
8462 u8 grade_version[0x8];
8463 u8 grade[0x18];
8465 u8 reserved_at_60[0x4];
8466 u8 height_grade_type[0x4];
8467 u8 height_grade[0x18];
8469 u8 height_dz[0x10];
8470 u8 height_dv[0x10];
8472 u8 reserved_at_a0[0x10];
8473 u8 height_sigma[0x10];
8475 u8 reserved_at_c0[0x20];
8477 u8 reserved_at_e0[0x4];
8478 u8 phase_grade_type[0x4];
8479 u8 phase_grade[0x18];
8481 u8 reserved_at_100[0x8];
8482 u8 phase_eo_pos[0x8];
8483 u8 reserved_at_110[0x8];
8484 u8 phase_eo_neg[0x8];
8486 u8 ffe_set_tested[0x10];
8487 u8 test_errors_per_lane[0x10];
8491 u8 reserved_at_0[0x8];
8492 u8 local_port[0x8];
8493 u8 reserved_at_10[0x10];
8495 u8 reserved_at_20[0x1c];
8496 u8 vl_hw_cap[0x4];
8498 u8 reserved_at_40[0x1c];
8499 u8 vl_admin[0x4];
8501 u8 reserved_at_60[0x1c];
8502 u8 vl_operational[0x4];
8506 u8 swid[0x8];
8507 u8 local_port[0x8];
8508 u8 reserved_at_10[0x4];
8509 u8 admin_status[0x4];
8510 u8 reserved_at_18[0x4];
8511 u8 oper_status[0x4];
8513 u8 reserved_at_20[0x60];
8517 u8 reserved_at_0[0x1];
8518 u8 an_disable_admin[0x1];
8519 u8 an_disable_cap[0x1];
8520 u8 reserved_at_3[0x5];
8521 u8 local_port[0x8];
8522 u8 reserved_at_10[0xd];
8523 u8 proto_mask[0x3];
8525 u8 an_status[0x4];
8526 u8 reserved_at_24[0xc];
8527 u8 data_rate_oper[0x10];
8529 u8 ext_eth_proto_capability[0x20];
8531 u8 eth_proto_capability[0x20];
8533 u8 ib_link_width_capability[0x10];
8534 u8 ib_proto_capability[0x10];
8536 u8 ext_eth_proto_admin[0x20];
8538 u8 eth_proto_admin[0x20];
8540 u8 ib_link_width_admin[0x10];
8541 u8 ib_proto_admin[0x10];
8543 u8 ext_eth_proto_oper[0x20];
8545 u8 eth_proto_oper[0x20];
8547 u8 ib_link_width_oper[0x10];
8548 u8 ib_proto_oper[0x10];
8550 u8 reserved_at_160[0x1c];
8551 u8 connector_type[0x4];
8553 u8 eth_proto_lp_advertise[0x20];
8555 u8 reserved_at_1a0[0x60];
8559 u8 reserved_at_0[0x8];
8560 u8 local_port[0x8];
8561 u8 reserved_at_10[0x20];
8563 u8 beacon_duration[0x10];
8564 u8 reserved_at_40[0x10];
8566 u8 beacon_remain[0x10];
8570 u8 reserved_at_0[0x20];
8572 u8 algorithm_options[0x10];
8573 u8 reserved_at_30[0x4];
8574 u8 repetitions_mode[0x4];
8575 u8 num_of_repetitions[0x8];
8577 u8 grade_version[0x8];
8578 u8 height_grade_type[0x4];
8579 u8 phase_grade_type[0x4];
8580 u8 height_grade_weight[0x8];
8581 u8 phase_grade_weight[0x8];
8583 u8 gisim_measure_bits[0x10];
8584 u8 adaptive_tap_measure_bits[0x10];
8586 u8 ber_bath_high_error_threshold[0x10];
8587 u8 ber_bath_mid_error_threshold[0x10];
8589 u8 ber_bath_low_error_threshold[0x10];
8590 u8 one_ratio_high_threshold[0x10];
8592 u8 one_ratio_high_mid_threshold[0x10];
8593 u8 one_ratio_low_mid_threshold[0x10];
8595 u8 one_ratio_low_threshold[0x10];
8596 u8 ndeo_error_threshold[0x10];
8598 u8 mixer_offset_step_size[0x10];
8599 u8 reserved_at_110[0x8];
8600 u8 mix90_phase_for_voltage_bath[0x8];
8602 u8 mixer_offset_start[0x10];
8603 u8 mixer_offset_end[0x10];
8605 u8 reserved_at_140[0x15];
8606 u8 ber_test_time[0xb];
8610 u8 swid[0x8];
8611 u8 local_port[0x8];
8612 u8 sub_port[0x8];
8613 u8 reserved_at_18[0x8];
8615 u8 reserved_at_20[0x20];
8619 u8 reserved_at_0[0x8];
8620 u8 local_port[0x8];
8621 u8 reserved_at_10[0x5];
8622 u8 prio[0x3];
8623 u8 reserved_at_18[0x6];
8624 u8 mode[0x2];
8626 u8 reserved_at_20[0x20];
8628 u8 reserved_at_40[0x10];
8629 u8 min_threshold[0x10];
8631 u8 reserved_at_60[0x10];
8632 u8 max_threshold[0x10];
8634 u8 reserved_at_80[0x10];
8635 u8 mark_probability_denominator[0x10];
8637 u8 reserved_at_a0[0x60];
8641 u8 reserved_at_0[0x8];
8642 u8 local_port[0x8];
8643 u8 reserved_at_10[0x10];
8645 u8 reserved_at_20[0x60];
8647 u8 reserved_at_80[0x1c];
8648 u8 wrps_admin[0x4];
8650 u8 reserved_at_a0[0x1c];
8651 u8 wrps_status[0x4];
8653 u8 reserved_at_c0[0x8];
8654 u8 up_threshold[0x8];
8655 u8 reserved_at_d0[0x8];
8656 u8 down_threshold[0x8];
8658 u8 reserved_at_e0[0x20];
8660 u8 reserved_at_100[0x1c];
8661 u8 srps_admin[0x4];
8663 u8 reserved_at_120[0x1c];
8664 u8 srps_status[0x4];
8666 u8 reserved_at_140[0x40];
8670 u8 reserved_at_0[0x8];
8671 u8 local_port[0x8];
8672 u8 reserved_at_10[0x10];
8674 u8 reserved_at_20[0x8];
8675 u8 lb_cap[0x8];
8676 u8 reserved_at_30[0x8];
8677 u8 lb_en[0x8];
8681 u8 reserved_at_0[0x8];
8682 u8 local_port[0x8];
8683 u8 reserved_at_10[0x10];
8685 u8 reserved_at_20[0x20];
8687 u8 port_profile_mode[0x8];
8688 u8 static_port_profile[0x8];
8689 u8 active_port_profile[0x8];
8690 u8 reserved_at_58[0x8];
8692 u8 retransmission_active[0x8];
8693 u8 fec_mode_active[0x18];
8695 u8 rs_fec_correction_bypass_cap[0x4];
8696 u8 reserved_at_84[0x8];
8697 u8 fec_override_cap_56g[0x4];
8698 u8 fec_override_cap_100g[0x4];
8699 u8 fec_override_cap_50g[0x4];
8700 u8 fec_override_cap_25g[0x4];
8701 u8 fec_override_cap_10g_40g[0x4];
8703 u8 rs_fec_correction_bypass_admin[0x4];
8704 u8 reserved_at_a4[0x8];
8705 u8 fec_override_admin_56g[0x4];
8706 u8 fec_override_admin_100g[0x4];
8707 u8 fec_override_admin_50g[0x4];
8708 u8 fec_override_admin_25g[0x4];
8709 u8 fec_override_admin_10g_40g[0x4];
8711 u8 fec_override_cap_400g_8x[0x10];
8712 u8 fec_override_cap_200g_4x[0x10];
8714 u8 fec_override_cap_100g_2x[0x10];
8715 u8 fec_override_cap_50g_1x[0x10];
8717 u8 fec_override_admin_400g_8x[0x10];
8718 u8 fec_override_admin_200g_4x[0x10];
8720 u8 fec_override_admin_100g_2x[0x10];
8721 u8 fec_override_admin_50g_1x[0x10];
8725 u8 swid[0x8];
8726 u8 local_port[0x8];
8727 u8 pnat[0x2];
8728 u8 reserved_at_12[0x8];
8729 u8 grp[0x6];
8731 u8 clr[0x1];
8732 u8 reserved_at_21[0x1c];
8733 u8 prio_tc[0x3];
8739 u8 reserved_at_0[0x2];
8740 u8 depth[0x6];
8741 u8 pcie_index[0x8];
8742 u8 node[0x8];
8743 u8 reserved_at_18[0x8];
8745 u8 capability_mask[0x20];
8747 u8 reserved_at_40[0x8];
8748 u8 link_width_enabled[0x8];
8749 u8 link_speed_enabled[0x10];
8751 u8 lane0_physical_position[0x8];
8752 u8 link_width_active[0x8];
8753 u8 link_speed_active[0x10];
8755 u8 num_of_pfs[0x10];
8756 u8 num_of_vfs[0x10];
8758 u8 bdf0[0x10];
8759 u8 reserved_at_b0[0x10];
8761 u8 max_read_request_size[0x4];
8762 u8 max_payload_size[0x4];
8763 u8 reserved_at_c8[0x5];
8764 u8 pwr_status[0x3];
8765 u8 port_type[0x4];
8766 u8 reserved_at_d4[0xb];
8767 u8 lane_reversal[0x1];
8769 u8 reserved_at_e0[0x14];
8770 u8 pci_power[0xc];
8772 u8 reserved_at_100[0x20];
8774 u8 device_status[0x10];
8775 u8 port_state[0x8];
8776 u8 reserved_at_138[0x8];
8778 u8 reserved_at_140[0x10];
8779 u8 receiver_detect_result[0x10];
8781 u8 reserved_at_160[0x20];
8785 u8 reserved_at_0[0x8];
8786 u8 pcie_index[0x8];
8787 u8 reserved_at_10[0xa];
8788 u8 grp[0x6];
8790 u8 clr[0x1];
8791 u8 reserved_at_21[0x1f];
8797 u8 reserved_at_0[0x3];
8798 u8 single_mac[0x1];
8799 u8 reserved_at_4[0x4];
8800 u8 local_port[0x8];
8801 u8 mac_47_32[0x10];
8803 u8 mac_31_0[0x20];
8805 u8 reserved_at_40[0x40];
8809 u8 reserved_at_0[0x8];
8810 u8 local_port[0x8];
8811 u8 reserved_at_10[0x10];
8813 u8 max_mtu[0x10];
8814 u8 reserved_at_30[0x10];
8816 u8 admin_mtu[0x10];
8817 u8 reserved_at_50[0x10];
8819 u8 oper_mtu[0x10];
8820 u8 reserved_at_70[0x10];
8824 u8 reserved_at_0[0x8];
8825 u8 module[0x8];
8826 u8 reserved_at_10[0x10];
8828 u8 reserved_at_20[0x18];
8829 u8 attenuation_5g[0x8];
8831 u8 reserved_at_40[0x18];
8832 u8 attenuation_7g[0x8];
8834 u8 reserved_at_60[0x18];
8835 u8 attenuation_12g[0x8];
8839 u8 reserved_at_0[0x8];
8840 u8 module[0x8];
8841 u8 reserved_at_10[0xc];
8842 u8 module_status[0x4];
8844 u8 reserved_at_20[0x60];
8848 u8 module_state_updated[32][0x8];
8852 u8 reserved_at_0[0x4];
8853 u8 mlpn_status[0x4];
8854 u8 local_port[0x8];
8855 u8 reserved_at_10[0x10];
8857 u8 e[0x1];
8858 u8 reserved_at_21[0x1f];
8862 u8 rxtx[0x1];
8863 u8 reserved_at_1[0x7];
8864 u8 local_port[0x8];
8865 u8 reserved_at_10[0x8];
8866 u8 width[0x8];
8868 u8 lane0_module_mapping[0x20];
8870 u8 lane1_module_mapping[0x20];
8872 u8 lane2_module_mapping[0x20];
8874 u8 lane3_module_mapping[0x20];
8876 u8 reserved_at_a0[0x160];
8880 u8 reserved_at_0[0x8];
8881 u8 module[0x8];
8882 u8 reserved_at_10[0x4];
8883 u8 admin_status[0x4];
8884 u8 reserved_at_18[0x4];
8885 u8 oper_status[0x4];
8887 u8 ase[0x1];
8888 u8 ee[0x1];
8889 u8 reserved_at_22[0x1c];
8890 u8 e[0x2];
8892 u8 reserved_at_40[0x40];
8896 u8 reserved_at_0[0x4];
8897 u8 profile_id[0xc];
8898 u8 reserved_at_10[0x4];
8899 u8 proto_mask[0x4];
8900 u8 reserved_at_18[0x8];
8902 u8 reserved_at_20[0x10];
8903 u8 lane_speed[0x10];
8905 u8 reserved_at_40[0x17];
8906 u8 lpbf[0x1];
8907 u8 fec_mode_policy[0x8];
8909 u8 retransmission_capability[0x8];
8910 u8 fec_mode_capability[0x18];
8912 u8 retransmission_support_admin[0x8];
8913 u8 fec_mode_support_admin[0x18];
8915 u8 retransmission_request_admin[0x8];
8916 u8 fec_mode_request_admin[0x18];
8918 u8 reserved_at_c0[0x80];
8922 u8 reserved_at_0[0x8];
8923 u8 local_port[0x8];
8924 u8 reserved_at_10[0x8];
8925 u8 ib_port[0x8];
8927 u8 reserved_at_20[0x60];
8931 u8 reserved_at_0[0x8];
8932 u8 local_port[0x8];
8933 u8 reserved_at_10[0xd];
8934 u8 lbf_mode[0x3];
8936 u8 reserved_at_20[0x20];
8940 u8 reserved_at_0[0x8];
8941 u8 local_port[0x8];
8942 u8 reserved_at_10[0x10];
8944 u8 dic[0x1];
8945 u8 reserved_at_21[0x19];
8946 u8 ipg[0x4];
8947 u8 reserved_at_3e[0x2];
8951 u8 reserved_at_0[0x8];
8952 u8 local_port[0x8];
8953 u8 reserved_at_10[0x10];
8955 u8 reserved_at_20[0xe0];
8957 u8 port_filter[8][0x20];
8959 u8 port_filter_update_en[8][0x20];
8963 u8 reserved_at_0[0x8];
8964 u8 local_port[0x8];
8965 u8 reserved_at_10[0xb];
8966 u8 ppan_mask_n[0x1];
8967 u8 minor_stall_mask[0x1];
8968 u8 critical_stall_mask[0x1];
8969 u8 reserved_at_1e[0x2];
8971 u8 ppan[0x4];
8972 u8 reserved_at_24[0x4];
8973 u8 prio_mask_tx[0x8];
8974 u8 reserved_at_30[0x8];
8975 u8 prio_mask_rx[0x8];
8977 u8 pptx[0x1];
8978 u8 aptx[0x1];
8979 u8 pptx_mask_n[0x1];
8980 u8 reserved_at_43[0x5];
8981 u8 pfctx[0x8];
8982 u8 reserved_at_50[0x10];
8984 u8 pprx[0x1];
8985 u8 aprx[0x1];
8986 u8 pprx_mask_n[0x1];
8987 u8 reserved_at_63[0x5];
8988 u8 pfcrx[0x8];
8989 u8 reserved_at_70[0x10];
8991 u8 device_stall_minor_watermark[0x10];
8992 u8 device_stall_critical_watermark[0x10];
8994 u8 reserved_at_a0[0x60];
8998 u8 op[0x4];
8999 u8 reserved_at_4[0x4];
9000 u8 local_port[0x8];
9001 u8 reserved_at_10[0x10];
9003 u8 op_admin[0x8];
9004 u8 op_capability[0x8];
9005 u8 op_request[0x8];
9006 u8 op_active[0x8];
9008 u8 admin[0x40];
9010 u8 capability[0x40];
9012 u8 request[0x40];
9014 u8 active[0x40];
9016 u8 reserved_at_140[0x80];
9020 u8 reserved_at_0[0x8];
9021 u8 local_port[0x8];
9022 u8 reserved_at_10[0x10];
9024 u8 reserved_at_20[0xc];
9025 u8 error_count[0x4];
9026 u8 reserved_at_30[0x10];
9028 u8 reserved_at_40[0xc];
9029 u8 lane[0x4];
9030 u8 reserved_at_50[0x8];
9031 u8 error_type[0x8];
9035 u8 reserved_at_0[0x30];
9036 u8 field_select[0x10];
9038 u8 tx_overflow_sense[0x1];
9039 u8 mark_cqe[0x1];
9040 u8 mark_cnp[0x1];
9041 u8 reserved_at_43[0x1b];
9042 u8 tx_lossy_overflow_oper[0x2];
9044 u8 reserved_at_60[0x100];
9048 u8 reserved_at_0[0x68];
9049 u8 fec_50G_per_lane_in_pplm[0x1];
9050 u8 reserved_at_69[0x4];
9051 u8 rx_icrc_encapsulated_counter[0x1];
9052 u8 reserved_at_6e[0x4];
9053 u8 ptys_extended_ethernet[0x1];
9054 u8 reserved_at_73[0x3];
9055 u8 pfcc_mask[0x1];
9056 u8 reserved_at_77[0x3];
9057 u8 per_lane_error_counters[0x1];
9058 u8 rx_buffer_fullness_counters[0x1];
9059 u8 ptys_connector_type[0x1];
9060 u8 reserved_at_7d[0x1];
9061 u8 ppcnt_discard_group[0x1];
9062 u8 ppcnt_statistical_group[0x1];
9066 u8 port_access_reg_cap_mask_127_to_96[0x20];
9067 u8 port_access_reg_cap_mask_95_to_64[0x20];
9069 u8 port_access_reg_cap_mask_63_to_36[0x1c];
9070 u8 pplm[0x1];
9071 u8 port_access_reg_cap_mask_34_to_32[0x3];
9073 u8 port_access_reg_cap_mask_31_to_13[0x13];
9074 u8 pbmc[0x1];
9075 u8 pptb[0x1];
9076 u8 port_access_reg_cap_mask_10_to_09[0x2];
9077 u8 ppcnt[0x1];
9078 u8 port_access_reg_cap_mask_07_to_00[0x8];
9082 u8 reserved_at_0[0x8];
9083 u8 feature_group[0x8];
9084 u8 reserved_at_10[0x8];
9085 u8 access_reg_group[0x8];
9087 u8 reserved_at_20[0x20];
9091 u8 reserved_at_0[0x80];
9094 u8 reserved_at_c0[0x80];
9098 u8 reserved_at_0[0x80];
9101 u8 reserved_at_1c0[0xc0];
9105 u8 reserved_at_0[0x6e];
9106 u8 pci_status_and_power[0x1];
9107 u8 reserved_at_6f[0x5];
9108 u8 mark_tx_action_cnp[0x1];
9109 u8 mark_tx_action_cqe[0x1];
9110 u8 dynamic_tx_overflow[0x1];
9111 u8 reserved_at_77[0x4];
9112 u8 pcie_outbound_stalled[0x1];
9113 u8 tx_overflow_buffer_pkt[0x1];
9114 u8 mtpps_enh_out_per_adj[0x1];
9115 u8 mtpps_fs[0x1];
9116 u8 pcie_performance_group[0x1];
9120 u8 reserved_at_0[0x1c];
9121 u8 mcda[0x1];
9122 u8 mcc[0x1];
9123 u8 mcqi[0x1];
9124 u8 mcqs[0x1];
9126 u8 regs_95_to_87[0x9];
9127 u8 mpegc[0x1];
9128 u8 regs_85_to_68[0x12];
9129 u8 tracer_registers[0x4];
9131 u8 regs_63_to_32[0x20];
9132 u8 regs_31_to_0[0x20];
9136 u8 regs_127_to_96[0x20];
9138 u8 regs_95_to_64[0x20];
9140 u8 regs_63_to_32[0x20];
9142 u8 regs_31_to_0[0x20];
9146 u8 regs_127_to_99[0x1d];
9147 u8 mirc[0x1];
9148 u8 regs_97_to_96[0x2];
9150 u8 regs_95_to_64[0x20];
9152 u8 regs_63_to_32[0x20];
9154 u8 regs_31_to_0[0x20];
9158 u8 reserved_at_0[0x8];
9159 u8 feature_group[0x8];
9160 u8 reserved_at_10[0x8];
9161 u8 access_reg_group[0x8];
9163 u8 reserved_at_20[0x20];
9169 u8 reserved_at_0[0x80];
9172 u8 reserved_at_c0[0x80];
9176 u8 reserved_at_0[0x80];
9179 u8 reserved_at_1c0[0x80];
9183 u8 qcam_access_reg_cap_mask_127_to_20[0x6C];
9184 u8 qpdpm[0x1];
9185 u8 qcam_access_reg_cap_mask_18_to_4[0x0F];
9186 u8 qdpm[0x1];
9187 u8 qpts[0x1];
9188 u8 qcap[0x1];
9189 u8 qcam_access_reg_cap_mask_0[0x1];
9193 u8 qcam_qos_feature_cap_mask_127_to_1[0x7F];
9194 u8 qpts_trust_both[0x1];
9198 u8 reserved_at_0[0x8];
9199 u8 feature_group[0x8];
9200 u8 reserved_at_10[0x8];
9201 u8 access_reg_group[0x8];
9202 u8 reserved_at_20[0x20];
9206 u8 reserved_at_0[0x80];
9209 u8 reserved_at_c0[0x80];
9213 u8 reserved_at_0[0x80];
9216 u8 reserved_at_1c0[0x80];
9220 u8 reserved_at_0[0x18];
9221 u8 core_dump_type[0x8];
9223 u8 reserved_at_20[0x30];
9224 u8 vhca_id[0x10];
9226 u8 reserved_at_60[0x8];
9227 u8 qpn[0x18];
9228 u8 reserved_at_80[0x180];
9232 u8 reserved_at_0[0x8];
9233 u8 local_port[0x8];
9234 u8 reserved_at_10[0x10];
9236 u8 port_capability_mask[4][0x20];
9240 u8 swid[0x8];
9241 u8 local_port[0x8];
9242 u8 reserved_at_10[0x4];
9243 u8 admin_status[0x4];
9244 u8 reserved_at_18[0x4];
9245 u8 oper_status[0x4];
9247 u8 ase[0x1];
9248 u8 ee[0x1];
9249 u8 reserved_at_22[0x1c];
9250 u8 e[0x2];
9252 u8 reserved_at_40[0x40];
9256 u8 reserved_at_0[0x8];
9257 u8 opamp_group[0x8];
9258 u8 reserved_at_10[0xc];
9259 u8 opamp_group_type[0x4];
9261 u8 start_index[0x10];
9262 u8 reserved_at_30[0x4];
9263 u8 num_of_indices[0xc];
9265 u8 index_data[18][0x10];
9269 u8 reserved_at_0[0x8];
9270 u8 local_port[0x8];
9271 u8 reserved_at_10[0x10];
9272 u8 entropy_force_cap[0x1];
9273 u8 entropy_calc_cap[0x1];
9274 u8 entropy_gre_calc_cap[0x1];
9275 u8 reserved_at_23[0x1b];
9276 u8 fcs_cap[0x1];
9277 u8 reserved_at_3f[0x1];
9278 u8 entropy_force[0x1];
9279 u8 entropy_calc[0x1];
9280 u8 entropy_gre_calc[0x1];
9281 u8 reserved_at_43[0x1b];
9282 u8 fcs_chk[0x1];
9283 u8 reserved_at_5f[0x1];
9287 u8 reserved_at_0[0x6];
9288 u8 rx_lane[0x2];
9289 u8 reserved_at_8[0x6];
9290 u8 tx_lane[0x2];
9291 u8 reserved_at_10[0x8];
9292 u8 module[0x8];
9296 u8 reserved_at_0[0x6];
9297 u8 lossy[0x1];
9298 u8 epsb[0x1];
9299 u8 reserved_at_8[0xc];
9300 u8 size[0xc];
9302 u8 xoff_threshold[0x10];
9303 u8 xon_threshold[0x10];
9307 u8 node_description[64][0x8];
9311 u8 reserved_at_0[0x18];
9312 u8 power_settings_level[0x8];
9314 u8 reserved_at_20[0x60];
9318 u8 he[0x1];
9319 u8 reserved_at_1[0x1f];
9321 u8 reserved_at_20[0x60];
9325 u8 reserved_at_0[0x20];
9327 u8 mkey[0x20];
9329 u8 addressh_63_32[0x20];
9331 u8 addressl_31_0[0x20];
9335 u8 dc_key[0x40];
9337 u8 ext[0x1];
9338 u8 reserved_at_41[0x7];
9339 u8 destination_qp_dct[0x18];
9341 u8 static_rate[0x4];
9342 u8 sl_eth_prio[0x4];
9343 u8 fl[0x1];
9344 u8 mlid[0x7];
9345 u8 rlid_udp_sport[0x10];
9347 u8 reserved_at_80[0x20];
9349 u8 rmac_47_16[0x20];
9351 u8 rmac_15_0[0x10];
9352 u8 tclass[0x8];
9353 u8 hop_limit[0x8];
9355 u8 reserved_at_e0[0x1];
9356 u8 grh[0x1];
9357 u8 reserved_at_e2[0x2];
9358 u8 src_addr_index[0x8];
9359 u8 flow_label[0x14];
9361 u8 rgid_rip[16][0x8];
9365 u8 reserved_at_0[0x10];
9366 u8 function_id[0x10];
9368 u8 num_pages[0x20];
9370 u8 reserved_at_40[0xa0];
9374 u8 reserved_at_0[0x8];
9375 u8 event_type[0x8];
9376 u8 reserved_at_10[0x8];
9377 u8 event_sub_type[0x8];
9379 u8 reserved_at_20[0xe0];
9383 u8 reserved_at_1e0[0x10];
9384 u8 signature[0x8];
9385 u8 reserved_at_1f8[0x7];
9386 u8 owner[0x1];
9390 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7,
9394 u8 type[0x8];
9395 u8 reserved_at_8[0x18];
9397 u8 input_length[0x20];
9399 u8 input_mailbox_pointer_63_32[0x20];
9401 u8 input_mailbox_pointer_31_9[0x17];
9402 u8 reserved_at_77[0x9];
9404 u8 command_input_inline_data[16][0x8];
9406 u8 command_output_inline_data[16][0x8];
9408 u8 output_mailbox_pointer_63_32[0x20];
9410 u8 output_mailbox_pointer_31_9[0x17];
9411 u8 reserved_at_1b7[0x9];
9413 u8 output_length[0x20];
9415 u8 token[0x8];
9416 u8 signature[0x8];
9417 u8 reserved_at_1f0[0x8];
9418 u8 status[0x7];
9419 u8 ownership[0x1];
9423 u8 status[0x8];
9424 u8 reserved_at_8[0x18];
9426 u8 syndrome[0x20];
9428 u8 command_output[0x20];
9432 u8 opcode[0x10];
9433 u8 reserved_at_10[0x10];
9435 u8 reserved_at_20[0x10];
9436 u8 op_mod[0x10];
9438 u8 command[][0x20];
9442 u8 mailbox_data[512][0x8];
9444 u8 reserved_at_1000[0x180];
9446 u8 next_pointer_63_32[0x20];
9448 u8 next_pointer_31_10[0x16];
9449 u8 reserved_at_11b6[0xa];
9451 u8 block_number[0x20];
9453 u8 reserved_at_11e0[0x8];
9454 u8 token[0x8];
9455 u8 ctrl_signature[0x8];
9456 u8 signature[0x8];
9460 u8 ptag_63_32[0x20];
9462 u8 ptag_31_8[0x18];
9463 u8 reserved_at_38[0x6];
9464 u8 wr_en[0x1];
9465 u8 rd_en[0x1];
9469 u8 status[0x8];
9470 u8 reserved_at_8[0x18];
9472 u8 syndrome[0x20];
9474 u8 reserved_at_40[0x10];
9475 u8 rol_mode[0x8];
9476 u8 wol_mode[0x8];
9478 u8 reserved_at_60[0x20];
9482 u8 opcode[0x10];
9483 u8 reserved_at_10[0x10];
9485 u8 reserved_at_20[0x10];
9486 u8 op_mod[0x10];
9488 u8 reserved_at_40[0x40];
9492 u8 status[0x8];
9493 u8 reserved_at_8[0x18];
9495 u8 syndrome[0x20];
9497 u8 reserved_at_40[0x40];
9501 u8 opcode[0x10];
9502 u8 reserved_at_10[0x10];
9504 u8 reserved_at_20[0x10];
9505 u8 op_mod[0x10];
9507 u8 rol_mode_valid[0x1];
9508 u8 wol_mode_valid[0x1];
9509 u8 reserved_at_42[0xe];
9510 u8 rol_mode[0x8];
9511 u8 wol_mode[0x8];
9513 u8 reserved_at_60[0x20];
9517 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0,
9518 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1,
9519 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2,
9523 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0,
9524 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1,
9525 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2,
9529 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1,
9530 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7,
9531 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8,
9532 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9,
9533 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa,
9534 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb,
9535 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc,
9536 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd,
9537 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe,
9538 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf,
9539 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10,
9543 u8 fw_rev_minor[0x10];
9544 u8 fw_rev_major[0x10];
9546 u8 cmd_interface_rev[0x10];
9547 u8 fw_rev_subminor[0x10];
9549 u8 reserved_at_40[0x40];
9551 u8 cmdq_phy_addr_63_32[0x20];
9553 u8 cmdq_phy_addr_31_12[0x14];
9554 u8 reserved_at_b4[0x2];
9555 u8 nic_interface[0x2];
9556 u8 log_cmdq_size[0x4];
9557 u8 log_cmdq_stride[0x4];
9559 u8 command_doorbell_vector[0x20];
9561 u8 reserved_at_e0[0xf00];
9563 u8 initializing[0x1];
9564 u8 reserved_at_fe1[0x4];
9565 u8 nic_interface_supported[0x3];
9566 u8 embedded_cpu[0x1];
9567 u8 reserved_at_fe9[0x17];
9571 u8 no_dram_nic_offset[0x20];
9573 u8 reserved_at_1220[0x6e40];
9575 u8 reserved_at_8060[0x1f];
9576 u8 clear_int[0x1];
9578 u8 health_syndrome[0x8];
9579 u8 health_counter[0x18];
9581 u8 reserved_at_80a0[0x17fc0];
9585 u8 reserved_at_0[0xc];
9586 u8 cap_number_of_pps_pins[0x4];
9587 u8 reserved_at_10[0x4];
9588 u8 cap_max_num_of_pps_in_pins[0x4];
9589 u8 reserved_at_18[0x4];
9590 u8 cap_max_num_of_pps_out_pins[0x4];
9592 u8 reserved_at_20[0x24];
9593 u8 cap_pin_3_mode[0x4];
9594 u8 reserved_at_48[0x4];
9595 u8 cap_pin_2_mode[0x4];
9596 u8 reserved_at_50[0x4];
9597 u8 cap_pin_1_mode[0x4];
9598 u8 reserved_at_58[0x4];
9599 u8 cap_pin_0_mode[0x4];
9601 u8 reserved_at_60[0x4];
9602 u8 cap_pin_7_mode[0x4];
9603 u8 reserved_at_68[0x4];
9604 u8 cap_pin_6_mode[0x4];
9605 u8 reserved_at_70[0x4];
9606 u8 cap_pin_5_mode[0x4];
9607 u8 reserved_at_78[0x4];
9608 u8 cap_pin_4_mode[0x4];
9610 u8 field_select[0x20];
9611 u8 reserved_at_a0[0x60];
9613 u8 enable[0x1];
9614 u8 reserved_at_101[0xb];
9615 u8 pattern[0x4];
9616 u8 reserved_at_110[0x4];
9617 u8 pin_mode[0x4];
9618 u8 pin[0x8];
9620 u8 reserved_at_120[0x20];
9622 u8 time_stamp[0x40];
9624 u8 out_pulse_duration[0x10];
9625 u8 out_periodic_adjustment[0x10];
9626 u8 enhanced_out_periodic_adjustment[0x20];
9628 u8 reserved_at_1c0[0x20];
9632 u8 reserved_at_0[0x18];
9633 u8 pin[0x8];
9634 u8 event_arm[0x1];
9635 u8 reserved_at_21[0x1b];
9636 u8 event_generation_mode[0x4];
9637 u8 reserved_at_40[0x40];
9641 u8 last_index_flag[0x1];
9642 u8 reserved_at_1[0x7];
9643 u8 fw_device[0x8];
9644 u8 component_index[0x10];
9646 u8 reserved_at_20[0x10];
9647 u8 identifier[0x10];
9649 u8 reserved_at_40[0x17];
9650 u8 component_status[0x5];
9651 u8 component_update_state[0x4];
9653 u8 last_update_state_changer_type[0x4];
9654 u8 last_update_state_changer_host_id[0x4];
9655 u8 reserved_at_68[0x18];
9659 u8 supported_info_bitmask[0x20];
9661 u8 component_size[0x20];
9663 u8 max_component_size[0x20];
9665 u8 log_mcda_word_size[0x4];
9666 u8 reserved_at_64[0xc];
9667 u8 mcda_max_write_size[0x10];
9669 u8 rd_en[0x1];
9670 u8 reserved_at_81[0x1];
9671 u8 match_chip_id[0x1];
9672 u8 match_psid[0x1];
9673 u8 check_user_timestamp[0x1];
9674 u8 match_base_guid_mac[0x1];
9675 u8 reserved_at_86[0x1a];
9679 u8 reserved_at_0[0x2];
9680 u8 build_time_valid[0x1];
9681 u8 user_defined_time_valid[0x1];
9682 u8 reserved_at_4[0x14];
9683 u8 version_string_length[0x8];
9685 u8 version[0x20];
9687 u8 build_time[0x40];
9689 u8 user_defined_time[0x40];
9691 u8 build_tool_version[0x20];
9693 u8 reserved_at_e0[0x20];
9695 u8 version_string[92][0x8];
9699 u8 pending_server_ac_power_cycle[0x1];
9700 u8 pending_server_dc_power_cycle[0x1];
9701 u8 pending_server_reboot[0x1];
9702 u8 pending_fw_reset[0x1];
9703 u8 auto_activate[0x1];
9704 u8 all_hosts_sync[0x1];
9705 u8 device_hw_reset[0x1];
9706 u8 reserved_at_7[0x19];
9716 u8 read_pending_component[0x1];
9717 u8 reserved_at_1[0xf];
9718 u8 component_index[0x10];
9720 u8 reserved_at_20[0x20];
9722 u8 reserved_at_40[0x1b];
9723 u8 info_type[0x5];
9725 u8 info_size[0x20];
9727 u8 offset[0x20];
9729 u8 reserved_at_a0[0x10];
9730 u8 data_size[0x10];
9736 u8 reserved_at_0[0x4];
9737 u8 time_elapsed_since_last_cmd[0xc];
9738 u8 reserved_at_10[0x8];
9739 u8 instruction[0x8];
9741 u8 reserved_at_20[0x10];
9742 u8 component_index[0x10];
9744 u8 reserved_at_40[0x8];
9745 u8 update_handle[0x18];
9747 u8 handle_owner_type[0x4];
9748 u8 handle_owner_host_id[0x4];
9749 u8 reserved_at_68[0x1];
9750 u8 control_progress[0x7];
9751 u8 error_code[0x8];
9752 u8 reserved_at_78[0x4];
9753 u8 control_state[0x4];
9755 u8 component_size[0x20];
9757 u8 reserved_at_a0[0x60];
9761 u8 reserved_at_0[0x8];
9762 u8 update_handle[0x18];
9764 u8 offset[0x20];
9766 u8 reserved_at_40[0x10];
9767 u8 size[0x10];
9769 u8 reserved_at_60[0x20];
9771 u8 data[][0x20];
9775 MLX5_MFRL_REG_RESET_TYPE_FULL_CHIP = BIT(0),
9780 MLX5_MFRL_REG_RESET_LEVEL0 = BIT(0),
9786 u8 reserved_at_0[0x20];
9788 u8 reserved_at_20[0x2];
9789 u8 pci_sync_for_fw_update_start[0x1];
9790 u8 pci_sync_for_fw_update_resp[0x2];
9791 u8 rst_type_sel[0x3];
9792 u8 reserved_at_28[0x8];
9793 u8 reset_type[0x8];
9794 u8 reset_level[0x8];
9798 u8 reserved_at_0[0x18];
9799 u8 status_code[0x8];
9801 u8 reserved_at_20[0x20];
9861 u8 reserved_at_0[0x60e0];
9866 u8 reserved_at_0[0x200];
9871 u8 reserved_at_0[0x20060];
9875 u8 status[0x8];
9876 u8 reserved_at_8[0x18];
9878 u8 syndrome[0x20];
9880 u8 reserved_at_40[0x40];
9884 u8 opcode[0x10];
9885 u8 reserved_at_10[0x10];
9887 u8 reserved_at_20[0x10];
9888 u8 op_mod[0x10];
9890 u8 other_vport[0x1];
9891 u8 reserved_at_41[0xf];
9892 u8 vport_number[0x10];
9894 u8 reserved_at_60[0x20];
9896 u8 table_type[0x8];
9897 u8 reserved_at_88[0x18];
9899 u8 reserved_at_a0[0x8];
9900 u8 table_id[0x18];
9902 u8 reserved_at_c0[0x8];
9903 u8 underlay_qpn[0x18];
9904 u8 reserved_at_e0[0x120];
9908 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = (1UL << 0),
9913 u8 status[0x8];
9914 u8 reserved_at_8[0x18];
9916 u8 syndrome[0x20];
9918 u8 reserved_at_40[0x40];
9922 u8 opcode[0x10];
9923 u8 reserved_at_10[0x10];
9925 u8 reserved_at_20[0x10];
9926 u8 op_mod[0x10];
9928 u8 other_vport[0x1];
9929 u8 reserved_at_41[0xf];
9930 u8 vport_number[0x10];
9932 u8 reserved_at_60[0x10];
9933 u8 modify_field_select[0x10];
9935 u8 table_type[0x8];
9936 u8 reserved_at_88[0x18];
9938 u8 reserved_at_a0[0x8];
9939 u8 table_id[0x18];
9945 u8 g[0x1];
9946 u8 b[0x1];
9947 u8 r[0x1];
9948 u8 reserved_at_3[0x9];
9949 u8 group[0x4];
9950 u8 reserved_at_10[0x9];
9951 u8 bw_allocation[0x7];
9953 u8 reserved_at_20[0xc];
9954 u8 max_bw_units[0x4];
9955 u8 reserved_at_30[0x8];
9956 u8 max_bw_value[0x8];
9960 u8 reserved_at_0[0x2];
9961 u8 r[0x1];
9962 u8 reserved_at_3[0x1d];
9964 u8 reserved_at_20[0xc];
9965 u8 max_bw_units[0x4];
9966 u8 reserved_at_30[0x8];
9967 u8 max_bw_value[0x8];
9971 u8 reserved_at_0[0x8];
9972 u8 port_number[0x8];
9973 u8 reserved_at_10[0x30];
9975 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8];
9980 u8 e[0x1];
9981 u8 reserved_at_01[0x0b];
9982 u8 prio[0x04];
9986 u8 reserved_at_0[0x8];
9987 u8 local_port[0x8];
9988 u8 reserved_at_10[0x10];
9993 u8 reserved_at_0[0x8];
9994 u8 local_port[0x8];
9995 u8 reserved_at_10[0x2d];
9996 u8 trust_state[0x3];
10000 u8 reserved_at_0[0x2];
10001 u8 mm[0x2];
10002 u8 reserved_at_4[0x4];
10003 u8 local_port[0x8];
10004 u8 reserved_at_10[0x6];
10005 u8 cm[0x1];
10006 u8 um[0x1];
10007 u8 pm[0x8];
10009 u8 prio_x_buff[0x20];
10011 u8 pm_msb[0x8];
10012 u8 reserved_at_48[0x10];
10013 u8 ctrl_buff[0x4];
10014 u8 untagged_buff[0x4];
10018 u8 reserved_at_0[0x8];
10019 u8 feature_group[0x8];
10020 u8 reserved_at_10[0x8];
10021 u8 access_reg_group[0x8];
10023 u8 reserved_at_20[0x20];
10025 u8 sb_access_reg_cap_mask[4][0x20];
10027 u8 reserved_at_c0[0x80];
10029 u8 sb_feature_cap_mask[4][0x20];
10031 u8 reserved_at_1c0[0x40];
10033 u8 cap_total_buffer_size[0x20];
10035 u8 cap_cell_size[0x10];
10036 u8 cap_max_pg_buffers[0x8];
10037 u8 cap_num_pool_supported[0x8];
10039 u8 reserved_at_240[0x8];
10040 u8 cap_sbsr_stat_size[0x8];
10041 u8 cap_max_tclass_data[0x8];
10042 u8 cap_max_cpu_ingress_tclass_sb[0x8];
10046 u8 reserved_at_0[0x8];
10047 u8 local_port[0x8];
10048 u8 reserved_at_10[0x10];
10050 u8 xoff_timer_value[0x10];
10051 u8 xoff_refresh[0x10];
10053 u8 reserved_at_40[0x9];
10054 u8 fullness_threshold[0x7];
10055 u8 port_buffer_size[0x10];
10059 u8 reserved_at_2e0[0x40];
10063 u8 reserved_at_0[0x8];
10064 u8 port_number[0x8];
10065 u8 reserved_at_10[0xd];
10066 u8 prio[0x3];
10068 u8 reserved_at_20[0x1d];
10069 u8 tclass[0x3];
10073 u8 l[0x1];
10074 u8 reserved_at_1[0x7];
10075 u8 module[0x8];
10076 u8 reserved_at_10[0x8];
10077 u8 status[0x8];
10079 u8 i2c_device_address[0x8];
10080 u8 page_number[0x8];
10081 u8 device_address[0x10];
10083 u8 reserved_at_40[0x10];
10084 u8 size[0x10];
10086 u8 reserved_at_60[0x20];
10088 u8 dword_0[0x20];
10089 u8 dword_1[0x20];
10090 u8 dword_2[0x20];
10091 u8 dword_3[0x20];
10092 u8 dword_4[0x20];
10093 u8 dword_5[0x20];
10094 u8 dword_6[0x20];
10095 u8 dword_7[0x20];
10096 u8 dword_8[0x20];
10097 u8 dword_9[0x20];
10098 u8 dword_10[0x20];
10099 u8 dword_11[0x20];
10103 u8 dcbx_cee_cap[0x1];
10104 u8 dcbx_ieee_cap[0x1];
10105 u8 dcbx_standby_cap[0x1];
10106 u8 reserved_at_3[0x5];
10107 u8 port_number[0x8];
10108 u8 reserved_at_10[0xa];
10110 u8 reserved_at_20[0x15];
10111 u8 version_oper[0x3];
10113 u8 version_admin[0x3];
10114 u8 willing_admin[0x1];
10115 u8 reserved_at_41[0x3];
10116 u8 pfc_cap_oper[0x4];
10117 u8 reserved_at_48[0x4];
10118 u8 pfc_cap_admin[0x4];
10119 u8 reserved_at_50[0x4];
10120 u8 num_of_tc_oper[0x4];
10121 u8 reserved_at_58[0x4];
10122 u8 num_of_tc_admin[0x4];
10123 u8 remote_willing[0x1];
10126 u8 reserved_at_68[0x14];
10127 u8 remote_num_of_tc[0x4];
10128 u8 reserved_at_80[0x18];
10129 u8 error[0x8];
10130 u8 reserved_at_a0[0x160];
10134 u8 reserved_at_0[0x1d];
10135 u8 lag_state[0x3];
10137 u8 reserved_at_20[0x14];
10138 u8 tx_remap_affinity_2[0x4];
10139 u8 reserved_at_38[0x4];
10140 u8 tx_remap_affinity_1[0x4];
10144 u8 status[0x8];
10145 u8 reserved_at_8[0x18];
10147 u8 syndrome[0x20];
10149 u8 reserved_at_40[0x40];
10153 u8 opcode[0x10];
10154 u8 reserved_at_10[0x10];
10156 u8 reserved_at_20[0x10];
10157 u8 op_mod[0x10];
10163 u8 status[0x8];
10164 u8 reserved_at_8[0x18];
10166 u8 syndrome[0x20];
10168 u8 reserved_at_40[0x40];
10172 u8 opcode[0x10];
10173 u8 reserved_at_10[0x10];
10175 u8 reserved_at_20[0x10];
10176 u8 op_mod[0x10];
10178 u8 reserved_at_40[0x20];
10179 u8 field_select[0x20];
10185 u8 status[0x8];
10186 u8 reserved_at_8[0x18];
10188 u8 syndrome[0x20];
10194 u8 opcode[0x10];
10195 u8 reserved_at_10[0x10];
10197 u8 reserved_at_20[0x10];
10198 u8 op_mod[0x10];
10200 u8 reserved_at_40[0x40];
10204 u8 status[0x8];
10205 u8 reserved_at_8[0x18];
10207 u8 syndrome[0x20];
10209 u8 reserved_at_40[0x40];
10213 u8 opcode[0x10];
10214 u8 reserved_at_10[0x10];
10216 u8 reserved_at_20[0x10];
10217 u8 op_mod[0x10];
10219 u8 reserved_at_40[0x40];
10223 u8 status[0x8];
10224 u8 reserved_at_8[0x18];
10226 u8 syndrome[0x20];
10228 u8 reserved_at_40[0x40];
10232 u8 opcode[0x10];
10233 u8 reserved_at_10[0x10];
10235 u8 reserved_at_20[0x10];
10236 u8 op_mod[0x10];
10238 u8 reserved_at_40[0x40];
10242 u8 status[0x8];
10243 u8 reserved_at_8[0x18];
10245 u8 syndrome[0x20];
10247 u8 reserved_at_40[0x40];
10251 u8 opcode[0x10];
10252 u8 reserved_at_10[0x10];
10254 u8 reserved_at_20[0x10];
10255 u8 op_mod[0x10];
10257 u8 reserved_at_40[0x40];
10261 u8 opcode[0x10];
10262 u8 reserved_at_10[0x10];
10264 u8 reserved_at_20[0x10];
10265 u8 op_mod[0x10];
10267 u8 reserved_at_30[0x20];
10269 u8 reserved_at_40[0x18];
10270 u8 log_memic_addr_alignment[0x8];
10272 u8 range_start_addr[0x40];
10274 u8 range_size[0x20];
10276 u8 memic_size[0x20];
10280 u8 status[0x8];
10281 u8 reserved_at_8[0x18];
10283 u8 syndrome[0x20];
10285 u8 memic_start_addr[0x40];
10289 u8 opcode[0x10];
10290 u8 reserved_at_10[0x10];
10292 u8 reserved_at_20[0x10];
10293 u8 op_mod[0x10];
10295 u8 reserved_at_40[0x40];
10297 u8 memic_start_addr[0x40];
10299 u8 memic_size[0x20];
10301 u8 reserved_at_e0[0x20];
10305 u8 status[0x8];
10306 u8 reserved_at_8[0x18];
10308 u8 syndrome[0x20];
10310 u8 reserved_at_40[0x40];
10314 u8 opcode[0x10];
10315 u8 uid[0x10];
10317 u8 vhca_tunnel_id[0x10];
10318 u8 obj_type[0x10];
10320 u8 obj_id[0x20];
10322 u8 reserved_at_60[0x20];
10326 u8 status[0x8];
10327 u8 reserved_at_8[0x18];
10329 u8 syndrome[0x20];
10331 u8 obj_id[0x20];
10333 u8 reserved_at_60[0x20];
10337 u8 reserved_at_0[0x80];
10339 u8 reserved_at_80[0x1b];
10340 u8 log_page_size[0x5];
10342 u8 page_offset[0x20];
10344 u8 num_of_mtt[0x40];
10350 u8 cap[0x20];
10352 u8 reserved_at_20[0x160];
10356 u8 modify_field_select[0x40];
10358 u8 reserved_at_40[0x18];
10359 u8 log_sw_icm_size[0x8];
10361 u8 reserved_at_60[0x20];
10363 u8 sw_icm_start_addr[0x40];
10365 u8 reserved_at_c0[0x140];
10369 u8 modify_field_select[0x40];
10371 u8 reserved_at_40[0x18];
10372 u8 geneve_option_fte_index[0x8];
10374 u8 option_class[0x10];
10375 u8 option_type[0x8];
10376 u8 reserved_at_78[0x3];
10377 u8 option_data_length[0x5];
10379 u8 reserved_at_80[0x180];
10383 u8 opcode[0x10];
10384 u8 uid[0x10];
10386 u8 reserved_at_20[0x10];
10387 u8 op_mod[0x10];
10389 u8 reserved_at_40[0x40];
10395 u8 status[0x8];
10396 u8 reserved_at_8[0x18];
10398 u8 syndrome[0x20];
10400 u8 reserved_at_40[0x8];
10401 u8 umem_id[0x18];
10403 u8 reserved_at_60[0x20];
10407 u8 opcode[0x10];
10408 u8 uid[0x10];
10410 u8 reserved_at_20[0x10];
10411 u8 op_mod[0x10];
10413 u8 reserved_at_40[0x8];
10414 u8 umem_id[0x18];
10416 u8 reserved_at_60[0x20];
10420 u8 status[0x8];
10421 u8 reserved_at_8[0x18];
10423 u8 syndrome[0x20];
10425 u8 reserved_at_40[0x40];
10429 u8 opcode[0x10];
10430 u8 reserved_at_10[0x10];
10432 u8 reserved_at_20[0x10];
10433 u8 op_mod[0x10];
10435 u8 reserved_at_40[0x40];
10441 u8 status[0x8];
10442 u8 reserved_at_8[0x18];
10444 u8 syndrome[0x20];
10446 u8 reserved_at_40[0x10];
10447 u8 uid[0x10];
10449 u8 reserved_at_60[0x20];
10453 u8 opcode[0x10];
10454 u8 reserved_at_10[0x10];
10456 u8 reserved_at_20[0x10];
10457 u8 op_mod[0x10];
10459 u8 reserved_at_40[0x10];
10460 u8 uid[0x10];
10462 u8 reserved_at_60[0x20];
10466 u8 status[0x8];
10467 u8 reserved_at_8[0x18];
10469 u8 syndrome[0x20];
10471 u8 reserved_at_40[0x40];
10485 u8 string_db_base_address[0x20];
10487 u8 reserved_at_20[0x8];
10488 u8 string_db_size[0x18];
10492 u8 trace_owner[0x1];
10493 u8 trace_to_memory[0x1];
10494 u8 reserved_at_2[0x4];
10495 u8 trc_ver[0x2];
10496 u8 reserved_at_8[0x14];
10497 u8 num_string_db[0x4];
10499 u8 first_string_trace[0x8];
10500 u8 num_string_trace[0x8];
10501 u8 reserved_at_30[0x28];
10503 u8 log_max_trace_buffer_size[0x8];
10505 u8 reserved_at_60[0x20];
10509 u8 reserved_at_280[0x180];
10513 u8 reserved_at_0[0x1c];
10514 u8 trace_mode[0x4];
10515 u8 reserved_at_20[0x18];
10516 u8 log_trace_buffer_size[0x8];
10517 u8 trace_mkey[0x20];
10518 u8 reserved_at_60[0x3a0];
10522 u8 string_db_index[0x4];
10523 u8 reserved_at_4[0x4];
10524 u8 read_size[0x18];
10525 u8 start_offset[0x20];
10530 u8 trace_status[0x2];
10531 u8 reserved_at_2[0x2];
10532 u8 arm_event[0x1];
10533 u8 reserved_at_5[0xb];
10534 u8 modify_field_select[0x10];
10535 u8 reserved_at_20[0x2b];
10536 u8 current_timestamp52_32[0x15];
10537 u8 current_timestamp31_0[0x20];
10538 u8 reserved_at_80[0x180];
10542 u8 host_number[0x8];
10543 u8 reserved_at_8[0x7];
10544 u8 host_pf_disabled[0x1];
10545 u8 host_num_of_vfs[0x10];
10547 u8 host_total_vfs[0x10];
10548 u8 host_pci_bus[0x10];
10550 u8 reserved_at_40[0x10];
10551 u8 host_pci_device[0x10];
10553 u8 reserved_at_60[0x10];
10554 u8 host_pci_function[0x10];
10556 u8 reserved_at_80[0x180];
10560 u8 opcode[0x10];
10561 u8 reserved_at_10[0x10];
10563 u8 reserved_at_20[0x10];
10564 u8 op_mod[0x10];
10566 u8 reserved_at_40[0x40];
10570 u8 status[0x8];
10571 u8 reserved_at_8[0x18];
10573 u8 syndrome[0x20];
10575 u8 reserved_at_40[0x40];
10579 u8 reserved_at_280[0x180];
10580 u8 host_sf_enable[][0x40];
10584 u8 reserved_at_0[0x10];
10585 u8 log_num_sf[0x8];
10586 u8 log_sf_bar_size[0x8];
10590 u8 status[0x8];
10591 u8 reserved_at_8[0x18];
10593 u8 syndrome[0x20];
10595 u8 reserved_at_40[0x18];
10596 u8 num_sf_partitions[0x8];
10598 u8 reserved_at_60[0x20];
10604 u8 opcode[0x10];
10605 u8 reserved_at_10[0x10];
10607 u8 reserved_at_20[0x10];
10608 u8 op_mod[0x10];
10610 u8 reserved_at_40[0x40];
10614 u8 status[0x8];
10615 u8 reserved_at_8[0x18];
10617 u8 syndrome[0x20];
10619 u8 reserved_at_40[0x40];
10623 u8 opcode[0x10];
10624 u8 reserved_at_10[0x10];
10626 u8 reserved_at_20[0x10];
10627 u8 op_mod[0x10];
10629 u8 reserved_at_40[0x10];
10630 u8 function_id[0x10];
10632 u8 reserved_at_60[0x20];
10636 u8 status[0x8];
10637 u8 reserved_at_8[0x18];
10639 u8 syndrome[0x20];
10641 u8 reserved_at_40[0x40];
10645 u8 opcode[0x10];
10646 u8 reserved_at_10[0x10];
10648 u8 reserved_at_20[0x10];
10649 u8 op_mod[0x10];
10651 u8 reserved_at_40[0x10];
10652 u8 function_id[0x10];
10654 u8 reserved_at_60[0x20];
10658 u8 reserved_at_0[0x10];
10659 u8 obj_type[0x10];
10661 u8 obj_id[0x20];
10665 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = BIT(0xc),
10666 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_IPSEC = BIT(0x13),
10670 MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = 0xc,
10671 MLX5_GENERAL_OBJECT_TYPES_IPSEC = 0x13,
10681 u8 modify_field_select[0x40];
10682 u8 full_offload[0x1];
10683 u8 reserved_at_41[0x1];
10684 u8 esn_en[0x1];
10685 u8 esn_overlap[0x1];
10686 u8 reserved_at_44[0x2];
10687 u8 icv_length[0x2];
10688 u8 reserved_at_48[0x4];
10689 u8 aso_return_reg[0x4];
10690 u8 reserved_at_50[0x10];
10692 u8 esn_msb[0x20];
10694 u8 reserved_at_80[0x8];
10695 u8 dekn[0x18];
10697 u8 salt[0x20];
10699 u8 implicit_iv[0x40];
10701 u8 reserved_at_100[0x700];
10710 MLX5_MODIFY_IPSEC_BITMASK_ESN_OVERLAP = BIT(0),
10725 u8 modify_field_select[0x40];
10727 u8 reserved_at_40[0x14];
10728 u8 key_size[0x4];
10729 u8 reserved_at_58[0x4];
10730 u8 key_type[0x4];
10732 u8 reserved_at_60[0x8];
10733 u8 pd[0x18];
10735 u8 reserved_at_80[0x180];
10736 u8 key[8][0x20];
10738 u8 reserved_at_300[0x500];
10747 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_128 = 0x0,
10748 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_256 = 0x1,
10752 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_TLS = 0x1,
10753 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_IPSEC = 0x2,
10757 u8 const_2[0x2];
10758 u8 tls_version[0x4];
10759 u8 const_1[0x2];
10760 u8 reserved_at_8[0x14];
10761 u8 encryption_standard[0x4];
10763 u8 reserved_at_20[0x20];
10765 u8 initial_record_number[0x40];
10767 u8 resync_tcp_sn[0x20];
10769 u8 gcm_iv[0x20];
10771 u8 implicit_iv[0x40];
10773 u8 reserved_at_100[0x8];
10774 u8 dek_index[0x18];
10776 u8 reserved_at_120[0xe0];
10780 u8 next_record_tcp_sn[0x20];
10782 u8 hw_resync_tcp_sn[0x20];
10784 u8 record_tracker_state[0x2];
10785 u8 auth_state[0x2];
10786 u8 reserved_at_44[0x4];
10787 u8 hw_offset_record_number[0x18];
10791 MLX5_MTT_PERM_READ = 1 << 0,