Lines Matching +full:interrupt +full:- +full:affinity
1 /* SPDX-License-Identifier: GPL-2.0 */
10 * Thanks. --rmk
36 * Bits 0-7 are the same as the IRQF_* bits in linux/interrupt.h
38 * IRQ_TYPE_NONE - default, unspecified type
39 * IRQ_TYPE_EDGE_RISING - rising edge triggered
40 * IRQ_TYPE_EDGE_FALLING - falling edge triggered
41 * IRQ_TYPE_EDGE_BOTH - rising and falling edge triggered
42 * IRQ_TYPE_LEVEL_HIGH - high level triggered
43 * IRQ_TYPE_LEVEL_LOW - low level triggered
44 * IRQ_TYPE_LEVEL_MASK - Mask to filter out the level bits
45 * IRQ_TYPE_SENSE_MASK - Mask for all the above bits
46 * IRQ_TYPE_DEFAULT - For use by some PICs to ask irq_set_type
52 * IRQ_TYPE_PROBE - Special flag for probing in progress
55 * IRQ_LEVEL - Interrupt is level type. Will be also
58 * IRQ_PER_CPU - Mark an interrupt PER_CPU. Will protect
59 * it from affinity setting
60 * IRQ_NOPROBE - Interrupt cannot be probed by autoprobing
61 * IRQ_NOREQUEST - Interrupt cannot be requested via
63 * IRQ_NOTHREAD - Interrupt cannot be threaded
64 * IRQ_NOAUTOEN - Interrupt is not automatically enabled in
66 * IRQ_NO_BALANCING - Interrupt cannot be balanced (affinity set)
67 * IRQ_MOVE_PCNTXT - Interrupt can be migrated from process context
68 * IRQ_NESTED_THREAD - Interrupt nests into another thread
69 * IRQ_PER_CPU_DEVID - Dev_id is a per-cpu variable
70 * IRQ_IS_POLLED - Always polled by another interrupt. Exclude
71 * it from the spurious interrupt detection
73 * IRQ_DISABLE_UNLAZY - Disable lazy irq disable
74 * IRQ_HIDDEN - Don't show up in /proc/interrupts
113 * Return value for chip->irq_set_affinity()
115 * IRQ_SET_MASK_OK - OK, core updates irq_common_data.affinity
116 * IRQ_SET_MASK_NOCPY - OK, chip did update irq_common_data.affinity
117 * IRQ_SET_MASK_OK_DONE - Same as IRQ_SET_MASK_OK for core. Special code to
131 * struct irq_common_data - per irq data shared by all irqchips
135 * @handler_data: per-IRQ data for the irq_chip methods
136 * @affinity: IRQ affinity on SMP. If this is an IPI
139 * @effective_affinity: The effective IRQ affinity on SMP as some irq
141 * A subset of @affinity.
143 * @ipi_offset: Offset of first IPI target cpu in @affinity. Optional.
152 cpumask_var_t affinity; member
162 * struct irq_data - per irq chip data passed down to chip functions
164 * @irq: interrupt number
165 * @hwirq: hardware interrupt number, local to the interrupt domain
167 * @chip: low level interrupt hardware access
168 * @domain: Interrupt translation domain; responsible for mapping
172 * @chip_data: platform-specific per-chip private data for the chip
191 * IRQD_TRIGGER_MASK - Mask for the trigger type bits
192 * IRQD_SETAFFINITY_PENDING - Affinity setting is pending
193 * IRQD_ACTIVATED - Interrupt has already been activated
194 * IRQD_NO_BALANCING - Balancing disabled for this IRQ
195 * IRQD_PER_CPU - Interrupt is per cpu
196 * IRQD_AFFINITY_SET - Interrupt affinity was set
197 * IRQD_LEVEL - Interrupt is level triggered
198 * IRQD_WAKEUP_STATE - Interrupt is configured for wakeup
200 * IRQD_MOVE_PCNTXT - Interrupt can be moved in process
202 * IRQD_IRQ_DISABLED - Disabled state of the interrupt
203 * IRQD_IRQ_MASKED - Masked state of the interrupt
204 * IRQD_IRQ_INPROGRESS - In progress state of the interrupt
205 * IRQD_WAKEUP_ARMED - Wakeup mode armed
206 * IRQD_FORWARDED_TO_VCPU - The interrupt is forwarded to a VCPU
207 * IRQD_AFFINITY_MANAGED - Affinity is auto-managed by the kernel
208 * IRQD_IRQ_STARTED - Startup state of the interrupt
209 * IRQD_MANAGED_SHUTDOWN - Interrupt was shutdown due to empty affinity
210 * mask. Applies only to affinity managed irqs.
211 * IRQD_SINGLE_TARGET - IRQ allows only a single affinity target
212 * IRQD_DEFAULT_TRIGGER_SET - Expected trigger already been set
213 * IRQD_CAN_RESERVE - Can use reservation mode
214 * IRQD_MSI_NOMASK_QUIRK - Non-maskable MSI quirk for affinity change
216 * IRQD_HANDLE_ENFORCE_IRQCTX - Enforce that handle_irq_*() is only invoked
217 * from actual interrupt context.
218 * IRQD_AFFINITY_ON_ACTIVATE - Affinity is set on activation. Don't call
220 * IRQD_IRQ_ENABLED_ON_SUSPEND - Interrupt is enabled on suspend by irq pm if
250 #define __irqd_to_state(d) ACCESS_PRIVATE((d)->common, state_use_accessors)
451 return d->hwirq; in irqd_to_hwirq()
455 * struct irq_chip - hardware interrupt chip descriptor
459 * @irq_startup: start up the interrupt (defaults to ->enable if NULL)
460 * @irq_shutdown: shut down the interrupt (defaults to ->disable if NULL)
461 * @irq_enable: enable the interrupt (defaults to chip->unmask if NULL)
462 * @irq_disable: disable the interrupt
463 * @irq_ack: start of a new interrupt
464 * @irq_mask: mask an interrupt source
465 * @irq_mask_ack: ack and mask an interrupt source
466 * @irq_unmask: unmask an interrupt source
467 * @irq_eoi: end of interrupt
468 * @irq_set_affinity: Set the CPU affinity on SMP machines. If the force
470 * unconditionally apply the affinity setting. Sanity
471 * checks against the supplied affinity mask are not
476 * @irq_set_wake: enable/disable power-management wake-on of an IRQ
479 * @irq_cpu_online: configure an interrupt source for a secondary CPU
480 * @irq_cpu_offline: un-configure an interrupt source for a secondary CPU
494 * @irq_get_irqchip_state: return the internal state of an interrupt
495 * @irq_set_irqchip_state: set the internal state of a interrupt
587 * Pick up the arch-dependent methods:
645 * Built-in IRQ handlers for various IRQ types,
646 * callable via desc->handle_irq()
701 /* Checks whether the interrupt can be requested by request_irq(): */
704 /* Dummy irq-chip implementations: */
720 const struct cpumask *affinity);
722 struct cpumask *affinity);
814 return d ? d->chip : NULL; in irq_get_chip()
819 return d->chip; in irq_data_get_irq_chip()
825 return d ? d->chip_data : NULL; in irq_get_chip_data()
830 return d->chip_data; in irq_data_get_irq_chip_data()
836 return d ? d->common->handler_data : NULL; in irq_get_handler_data()
841 return d->common->handler_data; in irq_data_get_irq_handler_data()
847 return d ? d->common->msi_desc : NULL; in irq_get_msi_desc()
852 return d->common->msi_desc; in irq_data_get_msi_desc()
864 return d->node; in irq_common_data_get_node()
872 return irq_common_data_get_node(d->common); in irq_data_get_node()
879 return d ? d->common->affinity : NULL; in irq_get_affinity_mask()
884 return d->common->affinity; in irq_data_get_affinity_mask()
891 return d->common->effective_affinity; in irq_data_get_effective_affinity_mask()
896 cpumask_copy(d->common->effective_affinity, m); in irq_data_update_effective_affinity()
906 return d->common->affinity; in irq_data_get_effective_affinity_mask()
914 const struct irq_affinity_desc *affinity);
918 const struct irq_affinity_desc *affinity);
925 irq_alloc_descs(-1, 0, 1, node)
931 irq_alloc_descs(-1, from, 1, node)
934 irq_alloc_descs(-1, from, cnt, node)
940 devm_irq_alloc_descs(dev, -1, 0, 1, node)
946 devm_irq_alloc_descs(dev, -1, from, 1, node)
949 devm_irq_alloc_descs(dev, -1, from, cnt, node)
977 * struct irq_chip_regs - register offsets for struct irq_gci
997 * struct irq_chip_type - Generic interrupt chip instance for a flow type
998 * @chip: The real interrupt chip which provides the callbacks
1019 * struct irq_chip_generic - Generic irq chip data structure
1030 * @irq_base: Interrupt base nr for this chip
1035 * @wake_enabled: Interrupt can wakeup from suspend
1036 * @wake_active: Interrupt is marked as an wakeup from suspend source
1043 * @chip_types: Array of interrupt irq_chip_types
1075 * enum irq_gc_flags - Initialization flags for generic irq chips
1081 * @IRQ_GC_NO_MASK: Do not calculate irq_data->mask
1082 * @IRQ_GC_BE_IO: Use big-endian register accesses (default: LE)
1093 * struct irq_domain_chip_generic - Generic irq chip data structure for irq domains
1099 * @gc: Array of pointers to generic interrupt chips
1174 return container_of(d->chip, struct irq_chip_type, chip); in irq_data_get_chip_type()
1177 #define IRQ_MSK(n) (u32)((n) < 32 ? ((1 << (n)) - 1) : UINT_MAX)
1182 raw_spin_lock(&gc->lock); in irq_gc_lock()
1187 raw_spin_unlock(&gc->lock); in irq_gc_unlock()
1195 * The irqsave variants are for usage in non interrupt code. Do not use
1199 raw_spin_lock_irqsave(&(gc)->lock, flags)
1202 raw_spin_unlock_irqrestore(&(gc)->lock, flags)
1207 if (gc->reg_writel) in irq_reg_writel()
1208 gc->reg_writel(val, gc->reg_base + reg_offset); in irq_reg_writel()
1210 writel(val, gc->reg_base + reg_offset); in irq_reg_writel()
1216 if (gc->reg_readl) in irq_reg_readl()
1217 return gc->reg_readl(gc->reg_base + reg_offset); in irq_reg_readl()
1219 return readl(gc->reg_base + reg_offset); in irq_reg_readl()
1255 * Registers a generic IRQ handling function as the top-level IRQ handler in
1257 * architecture-specific interrupt handler.
1259 * Returns 0 on success, or -EBUSY if an IRQ handler has already been
1265 * Allows interrupt handlers to find the irqchip that's been registered as the
1266 * top-level IRQ handler.