Lines Matching defs:intel_iommu
568 struct intel_iommu { struct
569 void __iomem *reg; /* Pointer to hardware regs, virtual addr */
570 u64 reg_phys; /* physical address of hw register set */
571 u64 reg_size; /* size of hw register set */
572 u64 cap;
573 u64 ecap;
574 u64 vccap;
575 u32 gcmd; /* Holds TE, EAFL. Don't need SRTP, SFL, WBF */
576 raw_spinlock_t register_lock; /* protect register handling */
577 int seq_id; /* sequence id of the iommu */
578 int agaw; /* agaw of this iommu */
579 int msagaw; /* max sagaw of this iommu */
580 unsigned int irq, pr_irq;
581 u16 segment; /* PCI segment# */
582 unsigned char name[13]; /* Device Name */
585 unsigned long *domain_ids; /* bitmap of domains */
586 struct dmar_domain ***domains; /* ptr to domains */
587 spinlock_t lock; /* protect context, domain ids */
588 struct root_entry *root_entry; /* virtual address */
590 struct iommu_flush flush;
593 struct page_req_dsc *prq;
594 unsigned char prq_name[16]; /* Name for PRQ interrupt */
595 struct completion prq_complete;
596 struct ioasid_allocator_ops pasid_allocator; /* Custom allocator for PASIDs */
598 struct q_inval *qi; /* Queued invalidation info */
599 u32 *iommu_state; /* Store iommu states between suspend and resume.*/
602 struct ir_table *ir_table; /* Interrupt remapping info */
603 struct irq_domain *ir_domain;
604 struct irq_domain *ir_msi_domain;
606 struct iommu_device iommu; /* IOMMU core code handle */
607 int node;
608 u32 flags; /* Software defined flags */
610 struct dmar_drhd_unit *drhd;