1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3  * Copyright(c) 2004 - 2006 Intel Corporation. All rights reserved.
18  * typedef dma_cookie_t - an opaque DMA cookie
31  * enum dma_status - DMA transaction status
46  * enum dma_transaction_type - DMA transaction types/indexes
73  * enum dma_transfer_direction - dma transfer mode and direction indicator
89  * ----------------------------
91  * The gap(in bytes) between two chunks is called inter-chunk-gap(ICG).
96  *  it is to be repeated and other per-transfer attributes.
103  *  |      Frame-1        |       Frame-2       | ~ |       Frame-'numf'  |
111  * struct data_chunk - Element of scatter-gather list that makes a frame.
133  * struct dma_interleaved_template - Template to convey DMAC the transfer pattern
164  * enum dma_ctrl_flags - DMA flags to augment operation preparation,
166  * @DMA_PREP_INTERRUPT - trigger an interrupt (callback) upon completion of
168  * @DMA_CTRL_ACK - if clear, the descriptor cannot be reused until the client
171  * @DMA_PREP_PQ_DISABLE_P - prevent generation of P while generating Q
172  * @DMA_PREP_PQ_DISABLE_Q - prevent generation of Q while generating P
173  * @DMA_PREP_CONTINUE - indicate to a driver that it is reusing buffers as
176  * @DMA_PREP_FENCE - tell the driver that subsequent operations depend
208  * enum sum_check_bits - bit position of pq_check_flags
216  * enum pq_check_flags - result of async_{xor,pq}_zero_sum operations
217  * @SUM_CHECK_P_RESULT - 1 if xor zero sum error, 0 otherwise
218  * @SUM_CHECK_Q_RESULT - 1 if reed-solomon zero sum error, 0 otherwise
227  * dma_cap_mask_t - capabilities bitmap modeled after cpumask_t.
233  * struct dma_chan_percpu - the per-CPU part of struct dma_chan
239  * enum dma_desc_metadata_mode - per descriptor metadata mode types supported
240  * @DESC_METADATA_CLIENT - the metadata buffer is allocated/provided by the
245  * - DMA_MEM_TO_DEV / DEV_MEM_TO_MEM:
251  * - DMA_DEV_TO_MEM:
259  * @DESC_METADATA_ENGINE - the metadata buffer is allocated/managed by the DMA
270  * - DMA_MEM_TO_DEV / DEV_MEM_TO_MEM:
278  * - DMA_DEV_TO_MEM:
301  * struct dma_router - DMA router structure
311  * struct dma_chan - devices supply DMA channels, clients use them
322  * @local: per-cpu pointer to a struct dma_chan_percpu
324  * @table_count: number of appearances in the mem-to-mem allocation table
327  * @private: private data for certain client-channel associations
356  * struct dma_chan_dev - relate sysfs device node to backing channel device
368  * enum dma_slave_buswidth - defines bus width of the DMA slave
384  * struct dma_slave_config - dma slave channel runtime config
404  * in one burst to the device. Typically something like half the
449  * enum dma_residue_granularity - Granularity of the reported transfer residue
459  *  the hardware supports scatter-gather and the segment descriptor has a field
463  *  burst. This is typically only supported if the hardware has a progress
475  * struct dma_slave_caps - expose capabilities of a slave channel only
484  * @min_burst: min burst capability per-transfer
485  * @max_burst: max burst capability per-transfer
486  * @max_sg_burst: max number of SG list entries executed in a single burst
513 	return dev_name(&chan->dev->device);  in dma_chan_name()
519  * typedef dma_filter_fn - callback filter for dma_request_channel
525  * being returned.  Where 'suitable' indicates a non-busy channel that
576  * struct dma_async_tx_descriptor - async transaction descriptor
577  * ---dma generic offload fields---
578  * @cookie: tracking cookie for this transaction, set to -EBUSY if
588  * @desc_metadata_mode: core managed metadata mode to protect mixed use of
593  * ---async_tx api specific fields---
622 	kref_get(&unmap->kref);  in dma_set_unmap()
623 	tx->unmap = unmap;  in dma_set_unmap()
646 	if (!tx->unmap)  in dma_descriptor_unmap()
649 	dmaengine_unmap_put(tx->unmap);  in dma_descriptor_unmap()
650 	tx->unmap = NULL;  in dma_descriptor_unmap()
682 	spin_lock_bh(&txd->lock);  in txd_lock()
686 	spin_unlock_bh(&txd->lock);  in txd_unlock()
690 	txd->next = next;  in txd_chain()
691 	next->parent = txd;  in txd_chain()
695 	txd->parent = NULL;  in txd_clear_parent()
699 	txd->next = NULL;  in txd_clear_next()
703 	return txd->parent;  in txd_parent()
707 	return txd->next;  in txd_next()
712  * struct dma_tx_state - filled in to report the status of
729  * enum dmaengine_alignment - defines alignment of the DMA async tx
743  * struct dma_slave_map - associates slave device and it's slave channel with
756  * struct dma_filter - information for slave device/channel to filter_fn/param
769  * struct dma_device - info on the entity supplying DMA services
778  * @max_pq: maximum number of PQ sources and PQ-continue capability
794  * @min_burst: min burst capability per-transfer
795  * @max_burst: max burst capability per-transfer
796  * @max_sg_burst: max number of SG list entries executed in a single burst
819  *	with per-channel specific ones
944 	if (chan->device->device_config)  in dmaengine_slave_config()
945 		return chan->device->device_config(chan, config);  in dmaengine_slave_config()
947 	return -ENOSYS;  in dmaengine_slave_config()
964 	if (!chan || !chan->device || !chan->device->device_prep_slave_sg)  in dmaengine_prep_slave_single()
967 	return chan->device->device_prep_slave_sg(chan, &sg, 1,  in dmaengine_prep_slave_single()
975 	if (!chan || !chan->device || !chan->device->device_prep_slave_sg)  in dmaengine_prep_slave_sg()
978 	return chan->device->device_prep_slave_sg(chan, sgl, sg_len,  in dmaengine_prep_slave_sg()
989 	if (!chan || !chan->device || !chan->device->device_prep_slave_sg)  in dmaengine_prep_rio_sg()
992 	return chan->device->device_prep_slave_sg(chan, sgl, sg_len,  in dmaengine_prep_rio_sg()
1002 	if (!chan || !chan->device || !chan->device->device_prep_dma_cyclic)  in dmaengine_prep_dma_cyclic()
1005 	return chan->device->device_prep_dma_cyclic(chan, buf_addr, buf_len,  in dmaengine_prep_dma_cyclic()
1013 	if (!chan || !chan->device || !chan->device->device_prep_interleaved_dma)  in dmaengine_prep_interleaved_dma()
1016 	    !test_bit(DMA_REPEAT, chan->device->cap_mask.bits))  in dmaengine_prep_interleaved_dma()
1019 	return chan->device->device_prep_interleaved_dma(chan, xt, flags);  in dmaengine_prep_interleaved_dma()
1026 	if (!chan || !chan->device || !chan->device->device_prep_dma_memset)  in dmaengine_prep_dma_memset()
1029 	return chan->device->device_prep_dma_memset(chan, dest, value,  in dmaengine_prep_dma_memset()
1037 	if (!chan || !chan->device || !chan->device->device_prep_dma_memcpy)  in dmaengine_prep_dma_memcpy()
1040 	return chan->device->device_prep_dma_memcpy(chan, dest, src,  in dmaengine_prep_dma_memcpy()
1050 	return !!(chan->device->desc_metadata_modes & mode);  in dmaengine_is_metadata_mode_supported()
1064 	return -EINVAL;  in dmaengine_desc_attach_metadata()
1075 	return -EINVAL;  in dmaengine_desc_set_metadata_len()
1080  * dmaengine_terminate_all() - Terminate all active DMA transfers
1088 	if (chan->device->device_terminate_all)  in dmaengine_terminate_all()
1089 		return chan->device->device_terminate_all(chan);  in dmaengine_terminate_all()
1091 	return -ENOSYS;  in dmaengine_terminate_all()
1095  * dmaengine_terminate_async() - Terminate all active DMA transfers
1117 	if (chan->device->device_terminate_all)  in dmaengine_terminate_async()
1118 		return chan->device->device_terminate_all(chan);  in dmaengine_terminate_async()
1120 	return -EINVAL;  in dmaengine_terminate_async()
1124  * dmaengine_synchronize() - Synchronize DMA channel termination
1137  * This function must only be called from non-atomic context and must not be
1145 	if (chan->device->device_synchronize)  in dmaengine_synchronize()
1146 		chan->device->device_synchronize(chan);  in dmaengine_synchronize()
1150  * dmaengine_terminate_sync() - Terminate all active DMA transfers
1159  * This function must only be called from non-atomic context and must not be
1178 	if (chan->device->device_pause)  in dmaengine_pause()
1179 		return chan->device->device_pause(chan);  in dmaengine_pause()
1181 	return -ENOSYS;  in dmaengine_pause()
1186 	if (chan->device->device_resume)  in dmaengine_resume()
1187 		return chan->device->device_resume(chan);  in dmaengine_resume()
1189 	return -ENOSYS;  in dmaengine_resume()
1195 	return chan->device->device_tx_status(chan, cookie, state);  in dmaengine_tx_status()
1200 	return desc->tx_submit(desc);  in dmaengine_submit()
1206 	return !(((1 << align) - 1) & (off1 | off2 | len));  in dmaengine_check_align()
1212 	return dmaengine_check_align(dev->copy_align, off1, off2, len);  in is_dma_copy_aligned()
1218 	return dmaengine_check_align(dev->xor_align, off1, off2, len);  in is_dma_xor_aligned()
1224 	return dmaengine_check_align(dev->pq_align, off1, off2, len);  in is_dma_pq_aligned()
1230 	return dmaengine_check_align(dev->fill_align, off1, off2, len);  in is_dma_fill_aligned()
1236 	dma->max_pq = maxpq;  in dma_set_maxpq()
1238 		dma->max_pq |= DMA_HAS_PQ_CONTINUE;  in dma_set_maxpq()
1255 	return (dma->max_pq & DMA_HAS_PQ_CONTINUE) == DMA_HAS_PQ_CONTINUE;  in dma_dev_has_pq_continue()
1260 	return dma->max_pq & ~DMA_HAS_PQ_CONTINUE;  in dma_dev_to_maxpq()
1263 /* dma_maxpq - reduce maxpq in the face of continued operations
1264  * @dma - dma device with PQ capability
1265  * @flags - to check if DMA_PREP_CONTINUE and DMA_PREP_PQ_DISABLE_P are set
1281 		return dma_dev_to_maxpq(dma) - 1;  in dma_maxpq()
1283 		return dma_dev_to_maxpq(dma) - 3;  in dma_maxpq()
1303 	return dmaengine_get_icg(xt->dst_inc, xt->dst_sgl,  in dmaengine_get_dst_icg()
1304 				 chunk->icg, chunk->dst_icg);  in dmaengine_get_dst_icg()
1310 	return dmaengine_get_icg(xt->src_inc, xt->src_sgl,  in dmaengine_get_src_icg()
1311 				 chunk->icg, chunk->src_icg);  in dmaengine_get_src_icg()
1314 /* --- public DMA engine API --- */
1354 	tx->flags |= DMA_CTRL_ACK;  in async_tx_ack()
1359 	tx->flags &= ~DMA_CTRL_ACK;  in async_tx_clear_ack()
1364 	return (tx->flags & DMA_CTRL_ACK) == DMA_CTRL_ACK;  in async_tx_test_ack()
1371 	set_bit(tx_type, dstp->bits);  in __dma_cap_set()
1378 	clear_bit(tx_type, dstp->bits);  in __dma_cap_clear()
1384 	bitmap_zero(dstp->bits, DMA_TX_TYPE_END);  in __dma_cap_zero()
1391 	return test_bit(tx_type, srcp->bits);  in __dma_has_cap()
1398  * dma_async_issue_pending - flush pending transactions to HW
1406 	chan->device->device_issue_pending(chan);  in dma_async_issue_pending()
1410  * dma_async_is_tx_complete - poll for transaction completion
1418  * the status of multiple cookies without re-checking hardware state.
1426 	status = chan->device->device_tx_status(chan, cookie, &state);  in dma_async_is_tx_complete()
1435  * dma_async_is_complete - test a cookie against chan state
1462 	st->last = last;  in dma_set_tx_state()
1463 	st->used = used;  in dma_set_tx_state()
1464 	st->residue = residue;  in dma_set_tx_state()
1507 	return ERR_PTR(-ENODEV);  in dma_request_chan()
1512 	return ERR_PTR(-ENODEV);  in dma_request_chan_by_mask()
1520 	return -ENXIO;  in dma_get_slave_caps()
1529 	ret = dma_get_slave_caps(tx->chan, &caps);  in dmaengine_desc_set_reuse()
1534 		return -EPERM;  in dmaengine_desc_set_reuse()
1536 	tx->flags |= DMA_CTRL_REUSE;  in dmaengine_desc_set_reuse()
1542 	tx->flags &= ~DMA_CTRL_REUSE;  in dmaengine_desc_clear_reuse()
1547 	return (tx->flags & DMA_CTRL_REUSE) == DMA_CTRL_REUSE;  in dmaengine_desc_test_reuse()
1554 		return -EPERM;  in dmaengine_desc_free()
1556 	return desc->desc_free(desc);  in dmaengine_desc_free()
1559 /* --- DMA device --- */