Lines Matching full:dpll

34  * struct dpll_data - DPLL registers and integration data
35  * @mult_div1_reg: register containing the DPLL M and N bitfields
36  * @mult_mask: mask of the DPLL M bitfield in @mult_div1_reg
37  * @div1_mask: mask of the DPLL N bitfield in @mult_div1_reg
40  * @control_reg: register containing the DPLL mode bitfield
41  * @enable_mask: mask of the DPLL mode bitfield in @control_reg
52  * @max_rate: maximum clock rate for the DPLL
54  * @autoidle_reg: register containing the DPLL autoidle mode bitfield
55  * @idlest_reg: register containing the DPLL idle status bitfield
56  * @autoidle_mask: mask of the DPLL autoidle mode bitfield in @autoidle_reg
57  * @freqsel_mask: mask of the DPLL jitter correction bitfield in @control_reg
58  * @dcc_mask: mask of the DPLL DCC correction bitfield @mult_div1_reg
60  * @idlest_mask: mask of the DPLL idle status bitfield in @idlest_reg
61  * @lpmode_mask: mask of the DPLL low-power mode bitfield in @control_reg
62  * @m4xen_mask: mask of the DPLL M4X multiplier bitfield in @control_reg
66  * @flags: DPLL type/features (see below)
69  * DPLL_J_TYPE: "J-type DPLL" (only some 36xx, 4xxx DPLLs)
179  * CLOCK_CLKOUTX2: (OMAP4 only) DPLL CLKOUT and CLKOUTX2 GATE_CTRL
193 /* CM_CLKEN_PLL*.EN* bit values - not all are available for every DPLL */
198 /* DPLL Type and DCO Selection Flags */