Lines Matching full:only
23 #define AT91RM9200_PMC_UDP (1 << 1) /* USB Devcice Port Clock [AT91RM9200 only] */
24 …MCKUDP (1 << 2) /* USB Device Port Master Clock Automatic Disable on Suspend [AT91RM9200 only] */
25 #define AT91RM9200_PMC_UHP (1 << 4) /* USB Host Port Clock [AT91RM9200 only] */
26 #define AT91SAM926x_PMC_UHP (1 << 6) /* USB Host Port Clock [AT91SAM926x only] */
27 #define AT91SAM926x_PMC_UDP (1 << 7) /* USB Devcice Port Clock [AT91SAM926x only] */
32 #define AT91_PMC_PCK4 (1 << 12) /* Programmable Clock 4 [AT572D940HF only] */
33 #define AT91_PMC_HCK0 (1 << 16) /* AHB Clock (USB host) [AT91SAM9261 only] */
34 #define AT91_PMC_HCK1 (1 << 17) /* AHB Clock (LCD) [AT91SAM9261 only] */
87 #define AT91_PMC3_MUL (0x7f << 18) /* PLL Multiplier [SAMA5 only] */
89 #define AT91_PMC_USBDIV (3 << 28) /* USB Divisor (PLLB only) */
93 #define AT91_PMC_USB96M (1 << 28) /* Divider by 2 Enable (PLLB only) */
103 #define AT91_PMC_CSS_UPLL (3 << 0) /* [some SAM9 only] */
123 #define AT91RM9200_PMC_MDIV_1 (0 << 8) /* [AT91RM9200 only] */
127 #define AT91SAM9_PMC_MDIV_1 (0 << 8) /* [SAM9 only] */
130 #define AT91SAM9_PMC_MDIV_6 (3 << 8) /* [some SAM9 only] */
131 #define AT91SAM9_PMC_MDIV_3 (3 << 8) /* [some SAM9 only] */
132 #define AT91_PMC_PDIV (1 << 12) /* Processor Clock Division [some SAM9 only] */
135 #define AT91_PMC_PLLADIV2 (1 << 12) /* PLLA divisor by 2 [some SAM9 only] */
140 #define AT91_PMC_XTALF 0x34 /* Main XTAL Frequency Register [SAMA7G5 only] */
142 #define AT91_PMC_USB 0x38 /* USB Clock Register [some SAM9 only] */
146 #define AT91_PMC_USBS_PLLB (1 << 0) /* [AT91SAMN12 only] */
151 #define AT91_PMC_SMD 0x3c /* Soft Modem Clock Register [some SAM9 only] */
158 #define AT91_PMC_CSS_MASTER (4 << 0) /* [some SAM9 only] */
208 #define AT91_PMC_PLL_ISR0 0xEC /* PLL Interrupt Status Register 0 [SAM9X60 only] */
210 #define AT91_PMC_PCER1 0x100 /* Peripheral Clock Enable Register 1 [SAMA5 only]*/