1 /* SPDX-License-Identifier: GPL-2.0 */
3  *  Copyright (c) 2010-2011 Jeremy Kerr <jeremy.kerr@canonical.com>
4  *  Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org>
14  * top-level framework.  custom flags for dealing with hardware specifics
20 #define CLK_SET_PARENT_GATE	BIT(1) /* must be gated across re-parent */
26 #define CLK_SET_RATE_NO_REPARENT BIT(7) /* don't re-parent on rate change */
31 /* parents need enable during gate/ungate, set rate and re-parent */
42  * struct clk_rate_request - Structure encoding the clk constraints that
64  * struct clk_duty - Struture encoding the duty cycle ratio of a clock
75  * struct clk_ops -  Callback operations for hardware clocks; these are to
122  *		Returns the calculated rate.  Optional, but recommended - if
138  *		Returns 0 on success, -EERROR otherwise.
154  *		Returns 0 on success, -EERROR otherwise.
165  *		Returns 0 on success, -EERROR otherwise.
170  *		Returns the calculated accuracy.  Optional - if	this op is not
175  *		Returned values are 0-359 degrees on success, negative
180  *		0-359. Return 0 on success, otherwise -EERROR.
189  *              and >= numerator) Return 0 on success, otherwise -EERROR.
191  * @init:	Perform platform-specific initialization magic.
198  *		Returns 0 on success, -EERROR otherwise.
202  * @debug_init:	Set up type-specific debugfs entries for this clock.  This
206  *		prepare_lock held.  Returns 0 on success, -EERROR otherwise.
258  * struct clk_parent_data - clk parent information
272  * struct clk_init_data - holds init data that's common to all clocks and is
277  * @parent_names: array of string names for all possible parents
283  * @flags: framework-level hints and quirks
297  * struct clk_hw - handle for traversing from a struct clk to its corresponding
298  * hardware-specific structure.  struct clk_hw should be declared within struct
305  * @clk: pointer to the per-user struct clk instance that can be used to call
328  * struct clk_fixed_rate - fixed-rate clock
329  * @hw:		handle between common and hardware-specific interfaces
335  * * CLK_FIXED_RATE_PARENT_ACCURACY - Use the accuracy of the parent clk
358  * clk_hw_register_fixed_rate - register fixed-rate clock with the clock
363  * @flags: framework-specific flags
364  * @fixed_rate: non-adjustable clock rate
370  * clk_hw_register_fixed_rate_parent_hw - register fixed-rate clock with
375  * @flags: framework-specific flags
376  * @fixed_rate: non-adjustable clock rate
383  * clk_hw_register_fixed_rate_parent_data - register fixed-rate clock with
388  * @flags: framework-specific flags
389  * @fixed_rate: non-adjustable clock rate
397  * clk_hw_register_fixed_rate_with_accuracy - register fixed-rate clock with
402  * @flags: framework-specific flags
403  * @fixed_rate: non-adjustable clock rate
404  * @fixed_accuracy: non-adjustable clock accuracy
413  * clk_hw_register_fixed_rate_with_accuracy_parent_hw - register fixed-rate
418  * @flags: framework-specific flags
419  * @fixed_rate: non-adjustable clock rate
420  * @fixed_accuracy: non-adjustable clock accuracy
428  * clk_hw_register_fixed_rate_with_accuracy_parent_data - register fixed-rate
433  * @flags: framework-specific flags
434  * @fixed_rate: non-adjustable clock rate
435  * @fixed_accuracy: non-adjustable clock accuracy
449  * struct clk_gate - gating clock
451  * @hw:		handle between common and hardware-specific interfaces
452  * @reg:	register controlling gate
454  * @flags:	hardware-specific flags
460  * CLK_GATE_SET_TO_DISABLE - by default this clock sets the bit at bit_idx to
463  * CLK_GATE_HIWORD_MASK - The gate settings are only in lower 16-bit
464  *	of this register, and mask of gate bits are in higher 16-bit of this
465  *	register.  While setting the gate bits, higher 16-bit should also be
467  * CLK_GATE_BIG_ENDIAN - by default little endian register accesses are used for
473 	void __iomem	*reg;  member
491 		void __iomem *reg, u8 bit_idx,
495 		void __iomem *reg, u8 bit_idx,
498  * clk_hw_register_gate - register a gate clock with the clock framework
502  * @flags: framework-specific flags for this clock
503  * @reg: register address to control gating of this clock
505  * @clk_gate_flags: gate-specific flags for this clock
508 #define clk_hw_register_gate(dev, name, parent_name, flags, reg, bit_idx,     \  argument
511 			       NULL, (flags), (reg), (bit_idx),		      \
514  * clk_hw_register_gate_parent_hw - register a gate clock with the clock
519  * @flags: framework-specific flags for this clock
520  * @reg: register address to control gating of this clock
522  * @clk_gate_flags: gate-specific flags for this clock
525 #define clk_hw_register_gate_parent_hw(dev, name, parent_hw, flags, reg,      \  argument
528 			       NULL, (flags), (reg), (bit_idx),		      \
531  * clk_hw_register_gate_parent_data - register a gate clock with the clock
536  * @flags: framework-specific flags for this clock
537  * @reg: register address to control gating of this clock
539  * @clk_gate_flags: gate-specific flags for this clock
542 #define clk_hw_register_gate_parent_data(dev, name, parent_data, flags, reg,  \  argument
545 			       (flags), (reg), (bit_idx),		      \
557  * struct clk_divider - adjustable divider clock
559  * @hw:		handle between common and hardware-specific interfaces
560  * @reg:	register containing the divider
570  * CLK_DIVIDER_ONE_BASED - by default the divisor is the value read from the
574  * CLK_DIVIDER_POWER_OF_TWO - clock divisor is 2 raised to the value read from
576  * CLK_DIVIDER_ALLOW_ZERO - Allow zero divisors.  For dividers which have
581  * CLK_DIVIDER_HIWORD_MASK - The divider settings are only in lower 16-bit
582  *	of this register, and mask of divider bits are in higher 16-bit of this
583  *	register.  While setting the divider bits, higher 16-bit should also be
585  * CLK_DIVIDER_ROUND_CLOSEST - Makes the best calculated divider to be rounded
587  * CLK_DIVIDER_READ_ONLY - The divider settings are preconfigured and should
589  * CLK_DIVIDER_MAX_AT_ZERO - For dividers which are like CLK_DIVIDER_ONE_BASED
592  * CLK_DIVIDER_BIG_ENDIAN - By default little endian register accesses are used
598 	void __iomem	*reg;  member
606 #define clk_div_mask(width)	((1 << (width)) - 1)
640 		void __iomem *reg, u8 shift, u8 width, u8 clk_divider_flags,
644 		void __iomem *reg, u8 shift, u8 width,
648  * clk_register_divider - register a divider clock with the clock framework
652  * @flags: framework-specific flags
653  * @reg: register address to adjust divider
656  * @clk_divider_flags: divider-specific flags for this clock
659 #define clk_register_divider(dev, name, parent_name, flags, reg, shift, width, \  argument
662 				   (reg), (shift), (width),		       \
665  * clk_hw_register_divider - register a divider clock with the clock framework
669  * @flags: framework-specific flags
670  * @reg: register address to adjust divider
673  * @clk_divider_flags: divider-specific flags for this clock
676 #define clk_hw_register_divider(dev, name, parent_name, flags, reg, shift,    \  argument
679 				  NULL, (flags), (reg), (shift), (width),     \
682  * clk_hw_register_divider_parent_hw - register a divider clock with the clock
687  * @flags: framework-specific flags
688  * @reg: register address to adjust divider
691  * @clk_divider_flags: divider-specific flags for this clock
694 #define clk_hw_register_divider_parent_hw(dev, name, parent_hw, flags, reg,   \  argument
698 				  NULL, (flags), (reg), (shift), (width),     \
701  * clk_hw_register_divider_parent_data - register a divider clock with the clock
706  * @flags: framework-specific flags
707  * @reg: register address to adjust divider
710  * @clk_divider_flags: divider-specific flags for this clock
714 					    reg, shift, width,		      \
717 				  (parent_data), (flags), (reg), (shift),     \
720  * clk_hw_register_divider_table - register a table based divider clock with
725  * @flags: framework-specific flags
726  * @reg: register address to adjust divider
729  * @clk_divider_flags: divider-specific flags for this clock
733 #define clk_hw_register_divider_table(dev, name, parent_name, flags, reg,     \  argument
737 				  NULL, (flags), (reg), (shift), (width),     \
740  * clk_hw_register_divider_table_parent_hw - register a table based divider
745  * @flags: framework-specific flags
746  * @reg: register address to adjust divider
749  * @clk_divider_flags: divider-specific flags for this clock
754 						reg, shift, width,	      \
758 				  NULL, (flags), (reg), (shift), (width),     \
761  * clk_hw_register_divider_table_parent_data - register a table based divider
766  * @flags: framework-specific flags
767  * @reg: register address to adjust divider
770  * @clk_divider_flags: divider-specific flags for this clock
775 						  flags, reg, shift, width,   \
779 				  (parent_data), (flags), (reg), (shift),     \
787  * struct clk_mux - multiplexer clock
789  * @hw:		handle between common and hardware-specific interfaces
790  * @reg:	register controlling multiplexer
794  * @flags:	hardware-specific flags
801  * CLK_MUX_INDEX_ONE - register index starts at 1, not 0
802  * CLK_MUX_INDEX_BIT - register index is a single bit (power of two)
803  * CLK_MUX_HIWORD_MASK - The mux settings are only in lower 16-bit of this
804  *	register, and mask of mux bits are in higher 16-bit of this register.
805  *	While setting the mux bits, higher 16-bit should also be updated to
807  * CLK_MUX_READ_ONLY - The mux registers can't be written, only read in the
809  * CLK_MUX_ROUND_CLOSEST - Use the parent rate that is closest to the desired
811  * CLK_MUX_BIG_ENDIAN - By default little endian register accesses are used for
817 	void __iomem	*reg;  member
842 		unsigned long flags, void __iomem *reg, u8 shift, u32 mask,
846 		unsigned long flags, void __iomem *reg, u8 shift, u32 mask,
849 #define clk_register_mux(dev, name, parent_names, num_parents, flags, reg,    \  argument
852 			       (flags), (reg), (shift), BIT((width)) - 1,     \
855 				  flags, reg, shift, mask, clk_mux_flags,     \
858 			      (parent_names), NULL, NULL, (flags), (reg),     \
861 #define clk_hw_register_mux(dev, name, parent_names, num_parents, flags, reg, \  argument
864 			      (parent_names), NULL, NULL, (flags), (reg),     \
865 			      (shift), BIT((width)) - 1, (clk_mux_flags),     \
868 				reg, shift, width, clk_mux_flags, lock)	      \
870 			      (parent_hws), NULL, (flags), (reg), (shift),    \
871 			      BIT((width)) - 1, (clk_mux_flags), NULL, (lock))
873 					flags, reg, shift, width,	      \
876 			      (parent_data), (flags), (reg), (shift),	      \
877 			      BIT((width)) - 1, (clk_mux_flags), NULL, (lock))
889  * struct clk_fixed_factor - fixed multiplier and divider clock
891  * @hw:		handle between common and hardware-specific interfaces
919  * struct clk_fractional_divider - adjustable fractional divider clock
921  * @hw:		handle between common and hardware-specific interfaces
922  * @reg:	register containing the divider
932  * CLK_FRAC_DIVIDER_ZERO_BASED - by default the numerator and denominator
936  * CLK_FRAC_DIVIDER_BIG_ENDIAN - By default little endian register accesses are
942 	void __iomem	*reg;  member
964 		void __iomem *reg, u8 mshift, u8 mwidth, u8 nshift, u8 nwidth,
968 		void __iomem *reg, u8 mshift, u8 mwidth, u8 nshift, u8 nwidth,
973  * struct clk_multiplier - adjustable multiplier clock
975  * @hw:		handle between common and hardware-specific interfaces
976  * @reg:	register containing the multiplier
985  * CLK_MULTIPLIER_ZERO_BYPASS - By default, the multiplier is the value read
990  * CLK_MULTIPLIER_ROUND_CLOSEST - Makes the best calculated divider to be
992  * CLK_MULTIPLIER_BIG_ENDIAN - By default little endian register accesses are
998 	void __iomem	*reg;  member
1014  * struct clk_composite - aggregate clock of mux, divider and gate clocks
1016  * @hw:		handle between common and hardware-specific interfaces
1017  * @mux_hw:	handle between composite and hardware-specific mux clock
1018  * @rate_hw:	handle between composite and hardware-specific rate clock
1019  * @gate_hw:	handle between composite and hardware-specific gate clock
1122 	dst->clk = src->clk;  in __clk_hw_set_clk()
1123 	dst->core = src->core;  in __clk_hw_set_clk()
1357 	return ERR_PTR(-ENOENT);  in of_clk_src_simple_get()
1362 	return ERR_PTR(-ENOENT);  in of_clk_hw_simple_get()
1367 	return ERR_PTR(-ENOENT);  in of_clk_src_onecell_get()
1372 	return ERR_PTR(-ENOENT);  in of_clk_hw_onecell_get()