Lines Matching full:clear

22 #define UART01x_ECR		0x04	/* Error clear register (Write). */
31 #define UART010_ICR		0x1C	/* Interrupt clear register (Write). */
43 #define UART011_ICR		0x44	/* Interrupt clear register. */
53 #define ST_UART011_ABIMSC	0x15C	/* Autobaud interrupt mask/clear register. */
190 #define UART011_OEIC		(1 << 10)	/* overrun error interrupt clear */
191 #define UART011_BEIC		(1 << 9)	/* break error interrupt clear */
192 #define UART011_PEIC		(1 << 8)	/* parity error interrupt clear */
193 #define UART011_FEIC		(1 << 7)	/* framing error interrupt clear */
194 #define UART011_RTIC		(1 << 6)	/* receive timeout interrupt clear */
195 #define UART011_TXIC		(1 << 5)	/* transmit interrupt clear */
196 #define UART011_RXIC		(1 << 4)	/* receive interrupt clear */
197 #define UART011_DSRMIC		(1 << 3)	/* DSR interrupt clear */
198 #define UART011_DCDMIC		(1 << 2)	/* DCD interrupt clear */
199 #define UART011_CTSMIC		(1 << 1)	/* CTS interrupt clear */
200 #define UART011_RIMIC		(1 << 0)	/* RI interrupt clear */