Lines Matching +full:25 +full:- +full:18
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
28 #define CLK_RPLL0_GATE 18
52 #define CLK_TWPLL_12M 18
59 #define CLK_TWPLL_76M8 25
101 #define CLK_IIS1 18
124 #define CLK_PWM0 18
131 #define CLK_THM 25
182 #define CLK_AP_INTC1_EB 18
189 #define CLK_PIN_EB 25
327 #define CLK_ISP_PCLK_EB 18
334 #define CLK_MIPI_CSI1 25
385 #define CLK_GSP1_A_GATE 18
392 #define CLK_GSP_MTX_F_GATE 25
418 #define CLK_UART4_EB 18