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39 #define CLK_MOUT_SCLK_MMC0_D 35
240 #define CLK_MOUT_SCLK_DECON_TV_ECLK_B 35
436 #define CLK_SCLK_UART1 35
508 #define CLK_SCLK_TMU0 35
553 #define CLK_PHYCLK_UFS_TX1_SYMBOL_PHY 35
691 #define CLK_DIV_SCLK_DECON_ECLK_DISP 35
813 #define CLK_PCLK_AUD_I2S 35
978 #define CLK_HCLK_CSSYS 35
1106 #define CLK_ACLK_SMMU_DIS0 35
1189 #define CLK_DIV_PCLK_LITE_B 35
1328 #define CLK_ACLK_ASYNCAXIM_CA5 35
1411 #define CLK_PCLK_SLIMSSS 35