Lines Matching +full:25 +full:- +full:18
1 /* SPDX-License-Identifier: GPL-2.0 */
22 #define CLK_MOUT_ACLK_CAM1_552_B 18
29 #define CLK_MOUT_ACLK_GSCL_333 25
223 #define CLK_MOUT_CLK2X_PHY_C 18
230 #define CLK_MOUT_ACLK_MIFNM_400 25
419 #define CLK_PCLK_I2C0 18
426 #define CLK_PCLK_HSI2C7 25
491 #define CLK_PCLK_TZPC8 18
498 #define CLK_PCLK_TZPC1 25
536 #define CLK_MOUT_PHYCLK_UFS_RX1_SYMBOL_USER 18
543 #define CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_PHY 25
646 #define CLK_PCLK_SMMU_MDMA1 18
653 #define CLK_PCLK_G2D 25
677 #define CLK_MOUT_SCLK_DECON_TV_ECLK 18
684 #define CLK_MOUT_SCLK_DECON_TV_VCLK_A_DISP 25
796 #define CLK_ACLK_AXIDS0_LPASSP 18
803 #define CLK_PCLK_WDT1 25
865 #define CLK_PCLK_SYSREG_G3D 18
889 #define CLK_PCLK_BTS_GSCL2 18
896 #define CLK_PCLK_GSCL0 25
924 #define CLK_ACLK_ASATBSLV_APOLLO_3_CSSYS 18
931 #define CLK_PCLK_ASAPBMST_CSSYS_APOLLO 25
961 #define CLK_ACLK_ATB_APOLLO0_CSSYS 18
968 #define CLK_PCLK_ASYNCAPB_ISP_CSSYS 25
1006 #define CLK_PCLK_BTS_JPEG 18
1013 #define CLK_PCLK_M2MSCALER0 25
1041 #define CLK_PCLK_SMMU_MFC_0 18
1065 #define CLK_PCLK_SMMU_HEVC_0 18
1089 #define CLK_ACLK_ASYNCAHBM_ISP1P 18
1096 #define CLK_ACLK_AHB2APB_ISP2P 25
1171 #define CLK_MOUT_ACLK_CSIS0_A 18
1178 #define CLK_MOUT_SCLK_LITE_FREECNT_A 25
1310 #define CLK_DIV_PCLK_DBG_CAM1 18
1318 #define CLK_ACLK_ISP_GIC 25