Lines Matching +full:0 +full:x68000
49 #define DP_MSA_MISC_SYNC_CLOCK (1 << 0)
51 #define DP_MSA_MISC_STEREO_NO_3D (0 << 9)
55 #define DP_MSA_MISC_6_BPC (0 << 5)
71 #define DP_MSA_MISC_COLOR_RGB _DP_MSA_MISC_COLOR(0, 0, 0, 0)
72 #define DP_MSA_MISC_COLOR_CEA_RGB _DP_MSA_MISC_COLOR(0, 0, 1, 0)
73 #define DP_MSA_MISC_COLOR_RGB_WIDE_FIXED _DP_MSA_MISC_COLOR(0, 3, 0, 0)
74 #define DP_MSA_MISC_COLOR_RGB_WIDE_FLOAT _DP_MSA_MISC_COLOR(0, 3, 0, 1)
75 #define DP_MSA_MISC_COLOR_Y_ONLY _DP_MSA_MISC_COLOR(1, 0, 0, 0)
76 #define DP_MSA_MISC_COLOR_RAW _DP_MSA_MISC_COLOR(1, 1, 0, 0)
77 #define DP_MSA_MISC_COLOR_YCBCR_422_BT601 _DP_MSA_MISC_COLOR(0, 1, 1, 0)
78 #define DP_MSA_MISC_COLOR_YCBCR_422_BT709 _DP_MSA_MISC_COLOR(0, 1, 1, 1)
79 #define DP_MSA_MISC_COLOR_YCBCR_444_BT601 _DP_MSA_MISC_COLOR(0, 2, 1, 0)
80 #define DP_MSA_MISC_COLOR_YCBCR_444_BT709 _DP_MSA_MISC_COLOR(0, 2, 1, 1)
81 #define DP_MSA_MISC_COLOR_XVYCC_422_BT601 _DP_MSA_MISC_COLOR(0, 1, 0, 0)
82 #define DP_MSA_MISC_COLOR_XVYCC_422_BT709 _DP_MSA_MISC_COLOR(0, 1, 0, 1)
83 #define DP_MSA_MISC_COLOR_XVYCC_444_BT601 _DP_MSA_MISC_COLOR(0, 2, 0, 0)
84 #define DP_MSA_MISC_COLOR_XVYCC_444_BT709 _DP_MSA_MISC_COLOR(0, 2, 0, 1)
85 #define DP_MSA_MISC_COLOR_OPRGB _DP_MSA_MISC_COLOR(0, 0, 1, 1)
86 #define DP_MSA_MISC_COLOR_DCI_P3 _DP_MSA_MISC_COLOR(0, 3, 1, 0)
87 #define DP_MSA_MISC_COLOR_COLOR_PROFILE _DP_MSA_MISC_COLOR(0, 3, 1, 1)
92 #define DP_AUX_I2C_WRITE 0x0
93 #define DP_AUX_I2C_READ 0x1
94 #define DP_AUX_I2C_WRITE_STATUS_UPDATE 0x2
95 #define DP_AUX_I2C_MOT 0x4
96 #define DP_AUX_NATIVE_WRITE 0x8
97 #define DP_AUX_NATIVE_READ 0x9
99 #define DP_AUX_NATIVE_REPLY_ACK (0x0 << 0)
100 #define DP_AUX_NATIVE_REPLY_NACK (0x1 << 0)
101 #define DP_AUX_NATIVE_REPLY_DEFER (0x2 << 0)
102 #define DP_AUX_NATIVE_REPLY_MASK (0x3 << 0)
104 #define DP_AUX_I2C_REPLY_ACK (0x0 << 2)
105 #define DP_AUX_I2C_REPLY_NACK (0x1 << 2)
106 #define DP_AUX_I2C_REPLY_DEFER (0x2 << 2)
107 #define DP_AUX_I2C_REPLY_MASK (0x3 << 2)
111 #define DP_DPCD_REV 0x000
112 # define DP_DPCD_REV_10 0x10
113 # define DP_DPCD_REV_11 0x11
114 # define DP_DPCD_REV_12 0x12
115 # define DP_DPCD_REV_13 0x13
116 # define DP_DPCD_REV_14 0x14
118 #define DP_MAX_LINK_RATE 0x001
120 #define DP_MAX_LANE_COUNT 0x002
121 # define DP_MAX_LANE_COUNT_MASK 0x1f
125 #define DP_MAX_DOWNSPREAD 0x003
126 # define DP_MAX_DOWNSPREAD_0_5 (1 << 0)
130 #define DP_NORP 0x004
132 #define DP_DOWNSTREAMPORT_PRESENT 0x005
133 # define DP_DWN_STRM_PORT_PRESENT (1 << 0)
134 # define DP_DWN_STRM_PORT_TYPE_MASK 0x06
135 # define DP_DWN_STRM_PORT_TYPE_DP (0 << 1)
142 #define DP_MAIN_LINK_CHANNEL_CODING 0x006
143 # define DP_CAP_ANSI_8B10B (1 << 0)
145 #define DP_DOWN_STREAM_PORT_COUNT 0x007
146 # define DP_PORT_COUNT_MASK 0x0f
150 #define DP_RECEIVE_PORT_0_CAP_0 0x008
154 #define DP_RECEIVE_PORT_0_BUFFER_SIZE 0x009
156 #define DP_RECEIVE_PORT_1_CAP_0 0x00a
157 #define DP_RECEIVE_PORT_1_BUFFER_SIZE 0x00b
159 #define DP_I2C_SPEED_CAP 0x00c /* DPI */
160 # define DP_I2C_SPEED_1K 0x01
161 # define DP_I2C_SPEED_5K 0x02
162 # define DP_I2C_SPEED_10K 0x04
163 # define DP_I2C_SPEED_100K 0x08
164 # define DP_I2C_SPEED_400K 0x10
165 # define DP_I2C_SPEED_1M 0x20
167 #define DP_EDP_CONFIGURATION_CAP 0x00d /* XXX 1.2? */
168 # define DP_ALTERNATE_SCRAMBLER_RESET_CAP (1 << 0)
172 #define DP_TRAINING_AUX_RD_INTERVAL 0x00e /* XXX 1.2? */
173 # define DP_TRAINING_AUX_RD_MASK 0x7F /* DP 1.3 */
176 #define DP_ADAPTER_CAP 0x00f /* 1.2 */
177 # define DP_FORCE_LOAD_SENSE_CAP (1 << 0)
180 #define DP_SUPPORTED_LINK_RATES 0x010 /* eDP 1.4 */
184 #define DP_FAUX_CAP 0x020 /* 1.2 */
185 # define DP_FAUX_CAP_1 (1 << 0)
187 #define DP_MSTM_CAP 0x021 /* 1.2 */
188 # define DP_MST_CAP (1 << 0)
190 #define DP_NUMBER_OF_AUDIO_ENDPOINTS 0x022 /* 1.2 */
193 #define DP_AV_GRANULARITY 0x023
194 # define DP_AG_FACTOR_MASK (0xf << 0)
195 # define DP_AG_FACTOR_3MS (0 << 0)
196 # define DP_AG_FACTOR_2MS (1 << 0)
197 # define DP_AG_FACTOR_1MS (2 << 0)
198 # define DP_AG_FACTOR_500US (3 << 0)
199 # define DP_AG_FACTOR_200US (4 << 0)
200 # define DP_AG_FACTOR_100US (5 << 0)
201 # define DP_AG_FACTOR_10US (6 << 0)
202 # define DP_AG_FACTOR_1US (7 << 0)
203 # define DP_VG_FACTOR_MASK (0xf << 4)
204 # define DP_VG_FACTOR_3MS (0 << 4)
211 #define DP_AUD_DEC_LAT0 0x024
212 #define DP_AUD_DEC_LAT1 0x025
214 #define DP_AUD_PP_LAT0 0x026
215 #define DP_AUD_PP_LAT1 0x027
217 #define DP_VID_INTER_LAT 0x028
219 #define DP_VID_PROG_LAT 0x029
221 #define DP_REP_LAT 0x02a
223 #define DP_AUD_DEL_INS0 0x02b
224 #define DP_AUD_DEL_INS1 0x02c
225 #define DP_AUD_DEL_INS2 0x02d
228 #define DP_RECEIVER_ALPM_CAP 0x02e /* eDP 1.4 */
229 # define DP_ALPM_CAP (1 << 0)
231 #define DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP 0x02f /* eDP 1.4 */
232 # define DP_AUX_FRAME_SYNC_CAP (1 << 0)
234 #define DP_GUID 0x030 /* 1.2 */
236 #define DP_DSC_SUPPORT 0x060 /* DP 1.4 */
237 # define DP_DSC_DECOMPRESSION_IS_SUPPORTED (1 << 0)
239 #define DP_DSC_REV 0x061
240 # define DP_DSC_MAJOR_MASK (0xf << 0)
241 # define DP_DSC_MINOR_MASK (0xf << 4)
242 # define DP_DSC_MAJOR_SHIFT 0
245 #define DP_DSC_RC_BUF_BLK_SIZE 0x062
246 # define DP_DSC_RC_BUF_BLK_SIZE_1 0x0
247 # define DP_DSC_RC_BUF_BLK_SIZE_4 0x1
248 # define DP_DSC_RC_BUF_BLK_SIZE_16 0x2
249 # define DP_DSC_RC_BUF_BLK_SIZE_64 0x3
251 #define DP_DSC_RC_BUF_SIZE 0x063
253 #define DP_DSC_SLICE_CAP_1 0x064
254 # define DP_DSC_1_PER_DP_DSC_SINK (1 << 0)
262 #define DP_DSC_LINE_BUF_BIT_DEPTH 0x065
263 # define DP_DSC_LINE_BUF_BIT_DEPTH_MASK (0xf << 0)
264 # define DP_DSC_LINE_BUF_BIT_DEPTH_9 0x0
265 # define DP_DSC_LINE_BUF_BIT_DEPTH_10 0x1
266 # define DP_DSC_LINE_BUF_BIT_DEPTH_11 0x2
267 # define DP_DSC_LINE_BUF_BIT_DEPTH_12 0x3
268 # define DP_DSC_LINE_BUF_BIT_DEPTH_13 0x4
269 # define DP_DSC_LINE_BUF_BIT_DEPTH_14 0x5
270 # define DP_DSC_LINE_BUF_BIT_DEPTH_15 0x6
271 # define DP_DSC_LINE_BUF_BIT_DEPTH_16 0x7
272 # define DP_DSC_LINE_BUF_BIT_DEPTH_8 0x8
274 #define DP_DSC_BLK_PREDICTION_SUPPORT 0x066
275 # define DP_DSC_BLK_PREDICTION_IS_SUPPORTED (1 << 0)
277 #define DP_DSC_MAX_BITS_PER_PIXEL_LOW 0x067 /* eDP 1.4 */
279 #define DP_DSC_MAX_BITS_PER_PIXEL_HI 0x068 /* eDP 1.4 */
280 # define DP_DSC_MAX_BITS_PER_PIXEL_HI_MASK (0x3 << 0)
283 #define DP_DSC_DEC_COLOR_FORMAT_CAP 0x069
284 # define DP_DSC_RGB (1 << 0)
290 #define DP_DSC_DEC_COLOR_DEPTH_CAP 0x06A
295 #define DP_DSC_PEAK_THROUGHPUT 0x06B
296 # define DP_DSC_THROUGHPUT_MODE_0_MASK (0xf << 0)
297 # define DP_DSC_THROUGHPUT_MODE_0_SHIFT 0
298 # define DP_DSC_THROUGHPUT_MODE_0_UNSUPPORTED 0
299 # define DP_DSC_THROUGHPUT_MODE_0_340 (1 << 0)
300 # define DP_DSC_THROUGHPUT_MODE_0_400 (2 << 0)
301 # define DP_DSC_THROUGHPUT_MODE_0_450 (3 << 0)
302 # define DP_DSC_THROUGHPUT_MODE_0_500 (4 << 0)
303 # define DP_DSC_THROUGHPUT_MODE_0_550 (5 << 0)
304 # define DP_DSC_THROUGHPUT_MODE_0_600 (6 << 0)
305 # define DP_DSC_THROUGHPUT_MODE_0_650 (7 << 0)
306 # define DP_DSC_THROUGHPUT_MODE_0_700 (8 << 0)
307 # define DP_DSC_THROUGHPUT_MODE_0_750 (9 << 0)
308 # define DP_DSC_THROUGHPUT_MODE_0_800 (10 << 0)
309 # define DP_DSC_THROUGHPUT_MODE_0_850 (11 << 0)
310 # define DP_DSC_THROUGHPUT_MODE_0_900 (12 << 0)
311 # define DP_DSC_THROUGHPUT_MODE_0_950 (13 << 0)
312 # define DP_DSC_THROUGHPUT_MODE_0_1000 (14 << 0)
313 # define DP_DSC_THROUGHPUT_MODE_0_170 (15 << 0) /* 1.4a */
314 # define DP_DSC_THROUGHPUT_MODE_1_MASK (0xf << 4)
316 # define DP_DSC_THROUGHPUT_MODE_1_UNSUPPORTED 0
333 #define DP_DSC_MAX_SLICE_WIDTH 0x06C
337 #define DP_DSC_SLICE_CAP_2 0x06D
338 # define DP_DSC_16_PER_DP_DSC_SINK (1 << 0)
342 #define DP_DSC_BITS_PER_PIXEL_INC 0x06F
343 # define DP_DSC_BITS_PER_PIXEL_1_16 0x0
344 # define DP_DSC_BITS_PER_PIXEL_1_8 0x1
345 # define DP_DSC_BITS_PER_PIXEL_1_4 0x2
346 # define DP_DSC_BITS_PER_PIXEL_1_2 0x3
347 # define DP_DSC_BITS_PER_PIXEL_1 0x4
349 #define DP_PSR_SUPPORT 0x070 /* XXX 1.2? */
354 #define DP_PSR_CAPS 0x071 /* XXX 1.2? */
356 # define DP_PSR_SETUP_TIME_330 (0 << 1)
368 #define DP_PSR2_SU_X_GRANULARITY 0x072 /* eDP 1.4b */
369 #define DP_PSR2_SU_Y_GRANULARITY 0x074 /* eDP 1.4b */
372 * 0x80-0x8f describe downstream port capabilities, but there are two layouts
379 /* offset 0 */
380 #define DP_DOWNSTREAM_PORT_0 0x80
381 # define DP_DS_PORT_TYPE_MASK (7 << 0)
382 # define DP_DS_PORT_TYPE_DP 0
390 # define DP_DS_NON_EDID_MASK (0xf << 4)
400 # define DP_DS_MAX_BPC_MASK (3 << 0)
401 # define DP_DS_8BPC 0
409 # define DP_DS_HDMI_FRAME_SEQ_TO_FRAME_PACK (1 << 0)
415 #define DP_MAX_DOWNSTREAM_PORTS 0x10
418 #define DP_FEC_CAPABILITY 0x090 /* 1.4 */
419 # define DP_FEC_CAPABLE (1 << 0)
425 #define DP_DSC_BRANCH_OVERALL_THROUGHPUT_0 0x0a0 /* DP 1.4a SCR */
426 #define DP_DSC_BRANCH_OVERALL_THROUGHPUT_1 0x0a1
427 #define DP_DSC_BRANCH_MAX_LINE_WIDTH 0x0a2
430 #define DP_LINK_BW_SET 0x100
431 # define DP_LINK_RATE_TABLE 0x00 /* eDP 1.4 */
432 # define DP_LINK_BW_1_62 0x06
433 # define DP_LINK_BW_2_7 0x0a
434 # define DP_LINK_BW_5_4 0x14 /* 1.2 */
435 # define DP_LINK_BW_8_1 0x1e /* 1.4 */
437 #define DP_LANE_COUNT_SET 0x101
438 # define DP_LANE_COUNT_MASK 0x0f
441 #define DP_TRAINING_PATTERN_SET 0x102
442 # define DP_TRAINING_PATTERN_DISABLE 0
447 # define DP_TRAINING_PATTERN_MASK 0x3
448 # define DP_TRAINING_PATTERN_MASK_1_4 0xf
451 # define DP_LINK_QUAL_PATTERN_11_DISABLE (0 << 2)
460 # define DP_SYMBOL_ERROR_COUNT_BOTH (0 << 6)
465 #define DP_TRAINING_LANE0_SET 0x103
466 #define DP_TRAINING_LANE1_SET 0x104
467 #define DP_TRAINING_LANE2_SET 0x105
468 #define DP_TRAINING_LANE3_SET 0x106
470 # define DP_TRAIN_VOLTAGE_SWING_MASK 0x3
471 # define DP_TRAIN_VOLTAGE_SWING_SHIFT 0
473 # define DP_TRAIN_VOLTAGE_SWING_LEVEL_0 (0 << 0)
474 # define DP_TRAIN_VOLTAGE_SWING_LEVEL_1 (1 << 0)
475 # define DP_TRAIN_VOLTAGE_SWING_LEVEL_2 (2 << 0)
476 # define DP_TRAIN_VOLTAGE_SWING_LEVEL_3 (3 << 0)
479 # define DP_TRAIN_PRE_EMPH_LEVEL_0 (0 << 3)
487 #define DP_DOWNSPREAD_CTRL 0x107
491 #define DP_MAIN_LINK_CHANNEL_CODING_SET 0x108
492 # define DP_SET_ANSI_8B10B (1 << 0)
494 #define DP_I2C_SPEED_CONTROL_STATUS 0x109 /* DPI */
497 #define DP_EDP_CONFIGURATION_SET 0x10a /* XXX 1.2? */
498 # define DP_ALTERNATE_SCRAMBLER_RESET_ENABLE (1 << 0)
502 #define DP_LINK_QUAL_LANE0_SET 0x10b /* DPCD >= 1.2 */
503 #define DP_LINK_QUAL_LANE1_SET 0x10c
504 #define DP_LINK_QUAL_LANE2_SET 0x10d
505 #define DP_LINK_QUAL_LANE3_SET 0x10e
506 # define DP_LINK_QUAL_PATTERN_DISABLE 0
514 #define DP_TRAINING_LANE0_1_SET2 0x10f
515 #define DP_TRAINING_LANE2_3_SET2 0x110
516 # define DP_LANE02_POST_CURSOR2_SET_MASK (3 << 0)
521 #define DP_MSTM_CTRL 0x111 /* 1.2 */
522 # define DP_MST_EN (1 << 0)
526 #define DP_AUDIO_DELAY0 0x112 /* 1.2 */
527 #define DP_AUDIO_DELAY1 0x113
528 #define DP_AUDIO_DELAY2 0x114
530 #define DP_LINK_RATE_SET 0x115 /* eDP 1.4 */
531 # define DP_LINK_RATE_SET_SHIFT 0
532 # define DP_LINK_RATE_SET_MASK (7 << 0)
534 #define DP_RECEIVER_ALPM_CONFIG 0x116 /* eDP 1.4 */
535 # define DP_ALPM_ENABLE (1 << 0)
538 #define DP_SINK_DEVICE_AUX_FRAME_SYNC_CONF 0x117 /* eDP 1.4 */
539 # define DP_AUX_FRAME_SYNC_ENABLE (1 << 0)
542 #define DP_UPSTREAM_DEVICE_DP_PWR_NEED 0x118 /* 1.2 */
543 # define DP_PWR_NOT_NEEDED (1 << 0)
545 #define DP_FEC_CONFIGURATION 0x120 /* 1.4 */
546 # define DP_FEC_READY (1 << 0)
548 # define DP_FEC_ERR_COUNT_DIS (0 << 1)
553 # define DP_FEC_LANE_0_SELECT (0 << 4)
558 #define DP_AUX_FRAME_SYNC_VALUE 0x15c /* eDP 1.4 */
559 # define DP_AUX_FRAME_SYNC_VALID (1 << 0)
561 #define DP_DSC_ENABLE 0x160 /* DP 1.4 */
562 # define DP_DECOMPRESSION_EN (1 << 0)
564 #define DP_PSR_EN_CFG 0x170 /* XXX 1.2? */
565 # define DP_PSR_ENABLE (1 << 0)
573 #define DP_ADAPTER_CTRL 0x1a0
574 # define DP_ADAPTER_CTRL_FORCE_LOAD_SENSE (1 << 0)
576 #define DP_BRANCH_DEVICE_CTRL 0x1a1
577 # define DP_BRANCH_DEVICE_IRQ_HPD (1 << 0)
579 #define DP_PAYLOAD_ALLOCATE_SET 0x1c0
580 #define DP_PAYLOAD_ALLOCATE_START_TIME_SLOT 0x1c1
581 #define DP_PAYLOAD_ALLOCATE_TIME_SLOT_COUNT 0x1c2
583 #define DP_SINK_COUNT 0x200
585 # define DP_GET_SINK_COUNT(x) ((((x) & 0x80) >> 1) | ((x) & 0x3f))
588 #define DP_DEVICE_SERVICE_IRQ_VECTOR 0x201
589 # define DP_REMOTE_CONTROL_COMMAND_PENDING (1 << 0)
597 #define DP_LANE0_1_STATUS 0x202
598 #define DP_LANE2_3_STATUS 0x203
599 # define DP_LANE_CR_DONE (1 << 0)
607 #define DP_LANE_ALIGN_STATUS_UPDATED 0x204
609 #define DP_INTERLANE_ALIGN_DONE (1 << 0)
613 #define DP_SINK_STATUS 0x205
615 #define DP_RECEIVE_PORT_0_STATUS (1 << 0)
618 #define DP_ADJUST_REQUEST_LANE0_1 0x206
619 #define DP_ADJUST_REQUEST_LANE2_3 0x207
620 # define DP_ADJUST_VOLTAGE_SWING_LANE0_MASK 0x03
621 # define DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT 0
622 # define DP_ADJUST_PRE_EMPHASIS_LANE0_MASK 0x0c
624 # define DP_ADJUST_VOLTAGE_SWING_LANE1_MASK 0x30
626 # define DP_ADJUST_PRE_EMPHASIS_LANE1_MASK 0xc0
629 #define DP_ADJUST_REQUEST_POST_CURSOR2 0x20c
630 # define DP_ADJUST_POST_CURSOR2_LANE0_MASK 0x03
631 # define DP_ADJUST_POST_CURSOR2_LANE0_SHIFT 0
632 # define DP_ADJUST_POST_CURSOR2_LANE1_MASK 0x0c
634 # define DP_ADJUST_POST_CURSOR2_LANE2_MASK 0x30
636 # define DP_ADJUST_POST_CURSOR2_LANE3_MASK 0xc0
639 #define DP_TEST_REQUEST 0x218
640 # define DP_TEST_LINK_TRAINING (1 << 0)
648 #define DP_TEST_LINK_RATE 0x219
649 # define DP_LINK_RATE_162 (0x6)
650 # define DP_LINK_RATE_27 (0xa)
652 #define DP_TEST_LANE_COUNT 0x220
654 #define DP_TEST_PATTERN 0x221
655 # define DP_NO_TEST_PATTERN 0x0
656 # define DP_COLOR_RAMP 0x1
657 # define DP_BLACK_AND_WHITE_VERTICAL_LINES 0x2
658 # define DP_COLOR_SQUARE 0x3
660 #define DP_TEST_H_TOTAL_HI 0x222
661 #define DP_TEST_H_TOTAL_LO 0x223
663 #define DP_TEST_V_TOTAL_HI 0x224
664 #define DP_TEST_V_TOTAL_LO 0x225
666 #define DP_TEST_H_START_HI 0x226
667 #define DP_TEST_H_START_LO 0x227
669 #define DP_TEST_V_START_HI 0x228
670 #define DP_TEST_V_START_LO 0x229
672 #define DP_TEST_HSYNC_HI 0x22A
674 # define DP_TEST_HSYNC_WIDTH_HI_MASK (127 << 0)
675 #define DP_TEST_HSYNC_WIDTH_LO 0x22B
677 #define DP_TEST_VSYNC_HI 0x22C
679 # define DP_TEST_VSYNC_WIDTH_HI_MASK (127 << 0)
680 #define DP_TEST_VSYNC_WIDTH_LO 0x22D
682 #define DP_TEST_H_WIDTH_HI 0x22E
683 #define DP_TEST_H_WIDTH_LO 0x22F
685 #define DP_TEST_V_HEIGHT_HI 0x230
686 #define DP_TEST_V_HEIGHT_LO 0x231
688 #define DP_TEST_MISC0 0x232
689 # define DP_TEST_SYNC_CLOCK (1 << 0)
692 # define DP_COLOR_FORMAT_RGB (0 << 1)
695 # define DP_TEST_DYNAMIC_RANGE_VESA (0 << 3)
698 # define DP_YCBCR_COEFFICIENTS_ITU601 (0 << 4)
702 # define DP_TEST_BIT_DEPTH_6 (0 << 5)
708 #define DP_TEST_MISC1 0x233
709 # define DP_TEST_REFRESH_DENOMINATOR (1 << 0)
712 #define DP_TEST_REFRESH_RATE_NUMERATOR 0x234
714 #define DP_TEST_MISC0 0x232
716 #define DP_TEST_CRC_R_CR 0x240
717 #define DP_TEST_CRC_G_Y 0x242
718 #define DP_TEST_CRC_B_CB 0x244
720 #define DP_TEST_SINK_MISC 0x246
722 # define DP_TEST_COUNT_MASK 0xf
724 #define DP_PHY_TEST_PATTERN 0x248
725 # define DP_PHY_TEST_PATTERN_SEL_MASK 0x7
726 # define DP_PHY_TEST_PATTERN_NONE 0x0
727 # define DP_PHY_TEST_PATTERN_D10_2 0x1
728 # define DP_PHY_TEST_PATTERN_ERROR_COUNT 0x2
729 # define DP_PHY_TEST_PATTERN_PRBS7 0x3
730 # define DP_PHY_TEST_PATTERN_80BIT_CUSTOM 0x4
731 # define DP_PHY_TEST_PATTERN_CP2520 0x5
733 #define DP_TEST_HBR2_SCRAMBLER_RESET 0x24A
734 #define DP_TEST_80BIT_CUSTOM_PATTERN_7_0 0x250
735 #define DP_TEST_80BIT_CUSTOM_PATTERN_15_8 0x251
736 #define DP_TEST_80BIT_CUSTOM_PATTERN_23_16 0x252
737 #define DP_TEST_80BIT_CUSTOM_PATTERN_31_24 0x253
738 #define DP_TEST_80BIT_CUSTOM_PATTERN_39_32 0x254
739 #define DP_TEST_80BIT_CUSTOM_PATTERN_47_40 0x255
740 #define DP_TEST_80BIT_CUSTOM_PATTERN_55_48 0x256
741 #define DP_TEST_80BIT_CUSTOM_PATTERN_63_56 0x257
742 #define DP_TEST_80BIT_CUSTOM_PATTERN_71_64 0x258
743 #define DP_TEST_80BIT_CUSTOM_PATTERN_79_72 0x259
745 #define DP_TEST_RESPONSE 0x260
746 # define DP_TEST_ACK (1 << 0)
750 #define DP_TEST_EDID_CHECKSUM 0x261
752 #define DP_TEST_SINK 0x270
753 # define DP_TEST_SINK_START (1 << 0)
754 #define DP_TEST_AUDIO_MODE 0x271
755 #define DP_TEST_AUDIO_PATTERN_TYPE 0x272
756 #define DP_TEST_AUDIO_PERIOD_CH1 0x273
757 #define DP_TEST_AUDIO_PERIOD_CH2 0x274
758 #define DP_TEST_AUDIO_PERIOD_CH3 0x275
759 #define DP_TEST_AUDIO_PERIOD_CH4 0x276
760 #define DP_TEST_AUDIO_PERIOD_CH5 0x277
761 #define DP_TEST_AUDIO_PERIOD_CH6 0x278
762 #define DP_TEST_AUDIO_PERIOD_CH7 0x279
763 #define DP_TEST_AUDIO_PERIOD_CH8 0x27A
765 #define DP_FEC_STATUS 0x280 /* 1.4 */
766 # define DP_FEC_DECODE_EN_DETECTED (1 << 0)
769 #define DP_FEC_ERROR_COUNT_LSB 0x0281 /* 1.4 */
771 #define DP_FEC_ERROR_COUNT_MSB 0x0282 /* 1.4 */
772 # define DP_FEC_ERROR_COUNT_MASK 0x7F
775 #define DP_PAYLOAD_TABLE_UPDATE_STATUS 0x2c0 /* 1.2 MST */
776 # define DP_PAYLOAD_TABLE_UPDATED (1 << 0)
779 #define DP_VC_PAYLOAD_ID_SLOT_1 0x2c1 /* 1.2 MST */
780 /* up to ID_SLOT_63 at 0x2ff */
782 #define DP_SOURCE_OUI 0x300
783 #define DP_SINK_OUI 0x400
784 #define DP_BRANCH_OUI 0x500
785 #define DP_BRANCH_ID 0x503
786 #define DP_BRANCH_REVISION_START 0x509
787 #define DP_BRANCH_HW_REV 0x509
788 #define DP_BRANCH_SW_REV 0x50A
790 #define DP_SET_POWER 0x600
791 # define DP_SET_POWER_D0 0x1
792 # define DP_SET_POWER_D3 0x2
793 # define DP_SET_POWER_MASK 0x3
794 # define DP_SET_POWER_D3_AUX_ON 0x5
796 #define DP_EDP_DPCD_REV 0x700 /* eDP 1.2 */
797 # define DP_EDP_11 0x00
798 # define DP_EDP_12 0x01
799 # define DP_EDP_13 0x02
800 # define DP_EDP_14 0x03
801 # define DP_EDP_14a 0x04 /* eDP 1.4a */
802 # define DP_EDP_14b 0x05 /* eDP 1.4b */
804 #define DP_EDP_GENERAL_CAP_1 0x701
805 # define DP_EDP_TCON_BACKLIGHT_ADJUSTMENT_CAP (1 << 0)
814 #define DP_EDP_BACKLIGHT_ADJUSTMENT_CAP 0x702
815 # define DP_EDP_BACKLIGHT_BRIGHTNESS_PWM_PIN_CAP (1 << 0)
824 #define DP_EDP_GENERAL_CAP_2 0x703
825 # define DP_EDP_OVERDRIVE_ENGINE_ENABLED (1 << 0)
827 #define DP_EDP_GENERAL_CAP_3 0x704 /* eDP 1.4 */
828 # define DP_EDP_X_REGION_CAP_MASK (0xf << 0)
829 # define DP_EDP_X_REGION_CAP_SHIFT 0
830 # define DP_EDP_Y_REGION_CAP_MASK (0xf << 4)
833 #define DP_EDP_DISPLAY_CONTROL_REGISTER 0x720
834 # define DP_EDP_BACKLIGHT_ENABLE (1 << 0)
840 #define DP_EDP_BACKLIGHT_MODE_SET_REGISTER 0x721
841 # define DP_EDP_BACKLIGHT_CONTROL_MODE_MASK (3 << 0)
842 # define DP_EDP_BACKLIGHT_CONTROL_MODE_PWM (0 << 0)
843 # define DP_EDP_BACKLIGHT_CONTROL_MODE_PRESET (1 << 0)
844 # define DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD (2 << 0)
845 # define DP_EDP_BACKLIGHT_CONTROL_MODE_PRODUCT (3 << 0)
852 #define DP_EDP_BACKLIGHT_BRIGHTNESS_MSB 0x722
853 #define DP_EDP_BACKLIGHT_BRIGHTNESS_LSB 0x723
855 #define DP_EDP_PWMGEN_BIT_COUNT 0x724
856 #define DP_EDP_PWMGEN_BIT_COUNT_CAP_MIN 0x725
857 #define DP_EDP_PWMGEN_BIT_COUNT_CAP_MAX 0x726
858 # define DP_EDP_PWMGEN_BIT_COUNT_MASK (0x1f << 0)
860 #define DP_EDP_BACKLIGHT_CONTROL_STATUS 0x727
862 #define DP_EDP_BACKLIGHT_FREQ_SET 0x728
865 #define DP_EDP_BACKLIGHT_FREQ_CAP_MIN_MSB 0x72a
866 #define DP_EDP_BACKLIGHT_FREQ_CAP_MIN_MID 0x72b
867 #define DP_EDP_BACKLIGHT_FREQ_CAP_MIN_LSB 0x72c
869 #define DP_EDP_BACKLIGHT_FREQ_CAP_MAX_MSB 0x72d
870 #define DP_EDP_BACKLIGHT_FREQ_CAP_MAX_MID 0x72e
871 #define DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB 0x72f
873 #define DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET 0x732
874 #define DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET 0x733
876 #define DP_EDP_REGIONAL_BACKLIGHT_BASE 0x740 /* eDP 1.4 */
877 #define DP_EDP_REGIONAL_BACKLIGHT_0 0x741 /* eDP 1.4 */
879 #define DP_SIDEBAND_MSG_DOWN_REQ_BASE 0x1000 /* 1.2 MST */
880 #define DP_SIDEBAND_MSG_UP_REP_BASE 0x1200 /* 1.2 MST */
881 #define DP_SIDEBAND_MSG_DOWN_REP_BASE 0x1400 /* 1.2 MST */
882 #define DP_SIDEBAND_MSG_UP_REQ_BASE 0x1600 /* 1.2 MST */
884 #define DP_SINK_COUNT_ESI 0x2002 /* 1.2 */
885 /* 0-5 sink count */
888 #define DP_DEVICE_SERVICE_IRQ_VECTOR_ESI0 0x2003 /* 1.2 */
890 #define DP_DEVICE_SERVICE_IRQ_VECTOR_ESI1 0x2004 /* 1.2 */
891 # define DP_RX_GTC_MSTR_REQ_STATUS_CHANGE (1 << 0)
895 #define DP_LINK_SERVICE_IRQ_VECTOR_ESI0 0x2005 /* 1.2 */
897 #define DP_PSR_ERROR_STATUS 0x2006 /* XXX 1.2? */
898 # define DP_PSR_LINK_CRC_ERROR (1 << 0)
902 #define DP_PSR_ESI 0x2007 /* XXX 1.2? */
903 # define DP_PSR_CAPS_CHANGE (1 << 0)
905 #define DP_PSR_STATUS 0x2008 /* XXX 1.2? */
906 # define DP_PSR_SINK_INACTIVE 0
912 # define DP_PSR_SINK_STATE_MASK 0x07
914 #define DP_SYNCHRONIZATION_LATENCY_IN_SINK 0x2009 /* edp 1.4 */
915 # define DP_MAX_RESYNC_FRAME_COUNT_MASK (0xf << 0)
916 # define DP_MAX_RESYNC_FRAME_COUNT_SHIFT 0
917 # define DP_LAST_ACTUAL_SYNCHRONIZATION_LATENCY_MASK (0xf << 4)
920 #define DP_LAST_RECEIVED_PSR_SDP 0x200a /* eDP 1.2 */
921 # define DP_PSR_STATE_BIT (1 << 0) /* eDP 1.2 */
929 #define DP_RECEIVER_ALPM_STATUS 0x200b /* eDP 1.4 */
930 # define DP_ALPM_LOCK_TIMEOUT_ERROR (1 << 0)
932 #define DP_LANE0_1_STATUS_ESI 0x200c /* status same as 0x202 */
933 #define DP_LANE2_3_STATUS_ESI 0x200d /* status same as 0x203 */
934 #define DP_LANE_ALIGN_STATUS_UPDATED_ESI 0x200e /* status same as 0x204 */
935 #define DP_SINK_STATUS_ESI 0x200f /* status same as 0x205 */
937 #define DP_DP13_DPCD_REV 0x2200
938 #define DP_DP13_MAX_LINK_RATE 0x2201
940 #define DP_DPRX_FEATURE_ENUMERATION_LIST 0x2210 /* DP 1.3 */
941 # define DP_GTC_CAP (1 << 0) /* DP 1.3 */
951 #define DP_CEC_TUNNELING_CAPABILITY 0x3000
952 # define DP_CEC_TUNNELING_CAPABLE (1 << 0)
956 #define DP_CEC_TUNNELING_CONTROL 0x3001
957 # define DP_CEC_TUNNELING_ENABLE (1 << 0)
960 #define DP_CEC_RX_MESSAGE_INFO 0x3002
961 # define DP_CEC_RX_MESSAGE_LEN_MASK (0xf << 0)
962 # define DP_CEC_RX_MESSAGE_LEN_SHIFT 0
968 #define DP_CEC_TX_MESSAGE_INFO 0x3003
969 # define DP_CEC_TX_MESSAGE_LEN_MASK (0xf << 0)
970 # define DP_CEC_TX_MESSAGE_LEN_SHIFT 0
971 # define DP_CEC_TX_RETRY_COUNT_MASK (0x7 << 4)
975 #define DP_CEC_TUNNELING_IRQ_FLAGS 0x3004
976 # define DP_CEC_RX_MESSAGE_INFO_VALID (1 << 0)
983 #define DP_CEC_LOGICAL_ADDRESS_MASK 0x300E /* 0x300F word */
984 # define DP_CEC_LOGICAL_ADDRESS_0 (1 << 0)
992 #define DP_CEC_LOGICAL_ADDRESS_MASK_2 0x300F /* 0x300E word */
993 # define DP_CEC_LOGICAL_ADDRESS_8 (1 << 0)
1002 #define DP_CEC_RX_MESSAGE_BUFFER 0x3010
1003 #define DP_CEC_TX_MESSAGE_BUFFER 0x3020
1004 #define DP_CEC_MESSAGE_BUFFER_LENGTH 0x10
1006 #define DP_PROTOCOL_CONVERTER_CONTROL_0 0x3050 /* DP 1.3 */
1007 # define DP_HDMI_DVI_OUTPUT_CONFIG (1 << 0) /* DP 1.3 */
1008 #define DP_PROTOCOL_CONVERTER_CONTROL_1 0x3051 /* DP 1.3 */
1009 # define DP_CONVERSION_TO_YCBCR420_ENABLE (1 << 0) /* DP 1.3 */
1013 #define DP_PROTOCOL_CONVERTER_CONTROL_2 0x3052 /* DP 1.3 */
1014 # define DP_CONVERSION_TO_YCBCR422_ENABLE (1 << 0) /* DP 1.3 */
1016 #define DP_AUX_HDCP_BKSV 0x68000
1017 #define DP_AUX_HDCP_RI_PRIME 0x68005
1018 #define DP_AUX_HDCP_AKSV 0x68007
1019 #define DP_AUX_HDCP_AN 0x6800C
1020 #define DP_AUX_HDCP_V_PRIME(h) (0x68014 + h * 4)
1021 #define DP_AUX_HDCP_BCAPS 0x68028
1023 # define DP_BCAPS_HDCP_CAPABLE BIT(0)
1024 #define DP_AUX_HDCP_BSTATUS 0x68029
1028 # define DP_BSTATUS_READY BIT(0)
1029 #define DP_AUX_HDCP_BINFO 0x6802A
1030 #define DP_AUX_HDCP_KSV_FIFO 0x6802C
1031 #define DP_AUX_HDCP_AINFO 0x6803B
1034 #define DP_HDCP_2_2_REG_RTX_OFFSET 0x69000
1035 #define DP_HDCP_2_2_REG_TXCAPS_OFFSET 0x69008
1036 #define DP_HDCP_2_2_REG_CERT_RX_OFFSET 0x6900B
1037 #define DP_HDCP_2_2_REG_RRX_OFFSET 0x69215
1038 #define DP_HDCP_2_2_REG_RX_CAPS_OFFSET 0x6921D
1039 #define DP_HDCP_2_2_REG_EKPUB_KM_OFFSET 0x69220
1040 #define DP_HDCP_2_2_REG_EKH_KM_WR_OFFSET 0x692A0
1041 #define DP_HDCP_2_2_REG_M_OFFSET 0x692B0
1042 #define DP_HDCP_2_2_REG_HPRIME_OFFSET 0x692C0
1043 #define DP_HDCP_2_2_REG_EKH_KM_RD_OFFSET 0x692E0
1044 #define DP_HDCP_2_2_REG_RN_OFFSET 0x692F0
1045 #define DP_HDCP_2_2_REG_LPRIME_OFFSET 0x692F8
1046 #define DP_HDCP_2_2_REG_EDKEY_KS_OFFSET 0x69318
1047 #define DP_HDCP_2_2_REG_RIV_OFFSET 0x69328
1048 #define DP_HDCP_2_2_REG_RXINFO_OFFSET 0x69330
1049 #define DP_HDCP_2_2_REG_SEQ_NUM_V_OFFSET 0x69332
1050 #define DP_HDCP_2_2_REG_VPRIME_OFFSET 0x69335
1051 #define DP_HDCP_2_2_REG_RECV_ID_LIST_OFFSET 0x69345
1052 #define DP_HDCP_2_2_REG_V_OFFSET 0x693E0
1053 #define DP_HDCP_2_2_REG_SEQ_NUM_M_OFFSET 0x693F0
1054 #define DP_HDCP_2_2_REG_K_OFFSET 0x693F3
1055 #define DP_HDCP_2_2_REG_STREAM_ID_TYPE_OFFSET 0x693F5
1056 #define DP_HDCP_2_2_REG_MPRIME_OFFSET 0x69473
1057 #define DP_HDCP_2_2_REG_RXSTATUS_OFFSET 0x69493
1058 #define DP_HDCP_2_2_REG_STREAM_TYPE_OFFSET 0x69494
1059 #define DP_HDCP_2_2_REG_DBG_OFFSET 0x69518
1062 #define DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV 0xf0000 /* 1.3 */
1063 #define DP_MAX_LINK_RATE_PHY_REPEATER 0xf0001 /* 1.4a */
1064 #define DP_PHY_REPEATER_CNT 0xf0002 /* 1.3 */
1065 #define DP_PHY_REPEATER_MODE 0xf0003 /* 1.3 */
1066 #define DP_MAX_LANE_COUNT_PHY_REPEATER 0xf0004 /* 1.4a */
1067 #define DP_Repeater_FEC_CAPABILITY 0xf0004 /* 1.4 */
1068 #define DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT 0xf0005 /* 1.4a */
1069 #define DP_TRAINING_PATTERN_SET_PHY_REPEATER1 0xf0010 /* 1.3 */
1070 #define DP_TRAINING_LANE0_SET_PHY_REPEATER1 0xf0011 /* 1.3 */
1071 #define DP_TRAINING_LANE1_SET_PHY_REPEATER1 0xf0012 /* 1.3 */
1072 #define DP_TRAINING_LANE2_SET_PHY_REPEATER1 0xf0013 /* 1.3 */
1073 #define DP_TRAINING_LANE3_SET_PHY_REPEATER1 0xf0014 /* 1.3 */
1074 #define DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1 0xf0020 /* 1.4a */
1075 #define DP_TRANSMITTER_CAPABILITY_PHY_REPEATER1 0xf0021 /* 1.4a */
1076 #define DP_LANE0_1_STATUS_PHY_REPEATER1 0xf0030 /* 1.3 */
1077 #define DP_LANE2_3_STATUS_PHY_REPEATER1 0xf0031 /* 1.3 */
1078 #define DP_LANE_ALIGN_STATUS_UPDATED_PHY_REPEATER1 0xf0032 /* 1.3 */
1079 #define DP_ADJUST_REQUEST_LANE0_1_PHY_REPEATER1 0xf0033 /* 1.3 */
1080 #define DP_ADJUST_REQUEST_LANE2_3_PHY_REPEATER1 0xf0034 /* 1.3 */
1081 #define DP_SYMBOL_ERROR_COUNT_LANE0_PHY_REPEATER1 0xf0035 /* 1.3 */
1082 #define DP_SYMBOL_ERROR_COUNT_LANE1_PHY_REPEATER1 0xf0037 /* 1.3 */
1083 #define DP_SYMBOL_ERROR_COUNT_LANE2_PHY_REPEATER1 0xf0039 /* 1.3 */
1084 #define DP_SYMBOL_ERROR_COUNT_LANE3_PHY_REPEATER1 0xf003b /* 1.3 */
1085 #define DP_FEC_STATUS_PHY_REPEATER1 0xf0290 /* 1.4 */
1086 #define DP_FEC_ERROR_COUNT_PHY_REPEATER1 0xf0291 /* 1.4 */
1087 #define DP_FEC_CAPABILITY_PHY_REPEATER1 0xf0294 /* 1.4a */
1090 #define DP_PHY_REPEATER_MODE_TRANSPARENT 0x55 /* 1.3 */
1091 #define DP_PHY_REPEATER_MODE_NON_TRANSPARENT 0xaa /* 1.3 */
1110 #define HDCP_2_2_DP_RXSTATUS_READY(x) ((x) & BIT(0))
1118 #define DP_PEER_DEVICE_NONE 0x0
1119 #define DP_PEER_DEVICE_SOURCE_OR_SST 0x1
1120 #define DP_PEER_DEVICE_MST_BRANCHING 0x2
1121 #define DP_PEER_DEVICE_SST_SINK 0x3
1122 #define DP_PEER_DEVICE_DP_LEGACY_CONV 0x4
1125 #define DP_GET_MSG_TRANSACTION_VERSION 0x00 /* DP 1.3 */
1126 #define DP_LINK_ADDRESS 0x01
1127 #define DP_CONNECTION_STATUS_NOTIFY 0x02
1128 #define DP_ENUM_PATH_RESOURCES 0x10
1129 #define DP_ALLOCATE_PAYLOAD 0x11
1130 #define DP_QUERY_PAYLOAD 0x12
1131 #define DP_RESOURCE_STATUS_NOTIFY 0x13
1132 #define DP_CLEAR_PAYLOAD_ID_TABLE 0x14
1133 #define DP_REMOTE_DPCD_READ 0x20
1134 #define DP_REMOTE_DPCD_WRITE 0x21
1135 #define DP_REMOTE_I2C_READ 0x22
1136 #define DP_REMOTE_I2C_WRITE 0x23
1137 #define DP_POWER_UP_PHY 0x24
1138 #define DP_POWER_DOWN_PHY 0x25
1139 #define DP_SINK_EVENT_NOTIFY 0x30
1140 #define DP_QUERY_STREAM_ENC_STATUS 0x38
1141 #define DP_QUERY_STREAM_ENC_STATUS_STATE_NO_EXIST 0
1146 #define DP_SIDEBAND_REPLY_ACK 0x00
1147 #define DP_SIDEBAND_REPLY_NAK 0x01
1150 #define DP_NAK_WRITE_FAILURE 0x01
1151 #define DP_NAK_INVALID_READ 0x02
1152 #define DP_NAK_CRC_FAILURE 0x03
1153 #define DP_NAK_BAD_PARAM 0x04
1154 #define DP_NAK_DEFER 0x05
1155 #define DP_NAK_LINK_FAILURE 0x06
1156 #define DP_NAK_NO_RESOURCES 0x07
1157 #define DP_NAK_DPCD_FAIL 0x08
1158 #define DP_NAK_I2C_NAK 0x09
1159 #define DP_NAK_ALLOCATE_FAIL 0x0a
1167 #define DP_MST_PHYSICAL_PORT_0 0
1170 #define DP_LINK_CONSTANT_N_VALUE 0x8000
1183 #define DP_BRANCH_OUI_HEADER_SIZE 0xc
1184 #define DP_RECEIVER_CAP_SIZE 0xf
1185 #define DP_DSC_RECEIVER_CAP_SIZE 0xf
1195 #define DP_SDP_AUDIO_TIMESTAMP 0x01
1196 #define DP_SDP_AUDIO_STREAM 0x02
1197 #define DP_SDP_EXTENSION 0x04 /* DP 1.1 */
1198 #define DP_SDP_AUDIO_COPYMANAGEMENT 0x05 /* DP 1.2 */
1199 #define DP_SDP_ISRC 0x06 /* DP 1.2 */
1200 #define DP_SDP_VSC 0x07 /* DP 1.2 */
1201 #define DP_SDP_CAMERA_GENERIC(i) (0x08 + (i)) /* 0-7, DP 1.3 */
1202 #define DP_SDP_PPS 0x10 /* DP 1.4 */
1203 #define DP_SDP_VSC_EXT_VESA 0x20 /* DP 1.4 */
1204 #define DP_SDP_VSC_EXT_CEA 0x21 /* DP 1.4 */
1205 /* 0x80+ CEA-861 infoframe types */
1211 * @HB2: Secondary Data Packet Specific header, Byte 0
1221 #define EDP_SDP_HEADER_REVISION_MASK 0x1F
1222 #define EDP_SDP_HEADER_VALID_PAYLOAD_BYTES 0x1F
1223 #define DP_SDP_PPS_HEADER_PAYLOAD_BYTES_MINUS_1 0x7F
1230 * db[0]: Stereo Interface
1231 * db[1]: 0 - PSR State; 1 - Update RFB; 2 - CRC Valid
1232 * db[2]: CRC value bits 7:0 of the R or Cr component
1234 * db[4]: CRC value bits 7:0 of the G or Y component
1236 * db[6]: CRC value bits 7:0 of the B or Cb component
1240 * db[0] - db[15]: Reserved
1251 #define EDP_VSC_PSR_STATE_ACTIVE (1<<0)
1265 * @DP_PIXELFORMAT_YUV420: YCbCr 4:2:0 pixel encoding format
1271 DP_PIXELFORMAT_RGB = 0,
1272 DP_PIXELFORMAT_YUV444 = 0x1,
1273 DP_PIXELFORMAT_YUV422 = 0x2,
1274 DP_PIXELFORMAT_YUV420 = 0x3,
1275 DP_PIXELFORMAT_Y_ONLY = 0x4,
1276 DP_PIXELFORMAT_RAW = 0x5,
1277 DP_PIXELFORMAT_RESERVED = 0x6,
1305 DP_COLORIMETRY_DEFAULT = 0,
1306 DP_COLORIMETRY_RGB_WIDE_FIXED = 0x1,
1307 DP_COLORIMETRY_BT709_YCC = 0x1,
1308 DP_COLORIMETRY_RGB_WIDE_FLOAT = 0x2,
1309 DP_COLORIMETRY_XVYCC_601 = 0x2,
1310 DP_COLORIMETRY_OPRGB = 0x3,
1311 DP_COLORIMETRY_XVYCC_709 = 0x3,
1312 DP_COLORIMETRY_DCI_P3_RGB = 0x4,
1313 DP_COLORIMETRY_SYCC_601 = 0x4,
1314 DP_COLORIMETRY_RGB_CUSTOM = 0x5,
1315 DP_COLORIMETRY_OPYCC_601 = 0x5,
1316 DP_COLORIMETRY_BT2020_RGB = 0x6,
1317 DP_COLORIMETRY_BT2020_CYCC = 0x6,
1318 DP_COLORIMETRY_BT2020_YCC = 0x7,
1332 DP_DYNAMIC_RANGE_VESA = 0,
1351 DP_CONTENT_TYPE_NOT_DEFINED = 0x00,
1352 DP_CONTENT_TYPE_GRAPHICS = 0x01,
1353 DP_CONTENT_TYPE_PHOTO = 0x02,
1354 DP_CONTENT_TYPE_VIDEO = 0x03,
1355 DP_CONTENT_TYPE_GAME = 0x04,
1405 return dpcd[DP_DPCD_REV] >= 0x11 && in drm_dp_enhanced_frame_cap()
1412 return dpcd[DP_DPCD_REV] >= 0x11 && in drm_dp_fast_training_cap()
1419 return dpcd[DP_DPCD_REV] >= 0x12 && in drm_dp_tps3_supported()
1426 return dpcd[DP_DPCD_REV] >= 0x14 && in drm_dp_tps4_supported()
1433 return (dpcd[DP_DPCD_REV] >= 0x14) ? DP_TRAINING_PATTERN_MASK_1_4 : in drm_dp_training_pattern_mask()
1716 * @ident: DP device identification from DPCD 0x400 (sink) or 0x500 (branch).
1742 * to 16 bits. So will give a constant value (0x8000) for compatability.
1780 * The device supports a link rate of 3.24 Gbps (multiplier 0xc) despite
1836 * @link_rate: Requested Link rate from DPCD 0x219
1837 * @num_lanes: Number of lanes requested by sing through DPCD 0x220
1838 * @phy_pattern: DP Phy test pattern from DPCD 0x248
1839 * @hbr2_reset: DP HBR2_COMPLIANCE_SCRAMBLER_RESET from DCPD 0x24A and 0x24B
1840 * @custom80: DP Test_80BIT_CUSTOM_PATTERN from DPCDs 0x250 through 0x259