44 #define ZF_IOBASE	0x218
45 #define INDEX		0x218
46 #define DATA_B		0x219
47 #define DATA_W		0x21A
48 #define DATA_D		0x21A
51 #define ZFL_VERSION	0x02	/* 16   */
52 #define CONTROL		0x10	/* 16   */
53 #define STATUS		0x12	/* 8    */
54 #define COUNTER_1	0x0C	/* 16   */
55 #define COUNTER_2	0x0E	/* 8    */
56 #define PULSE_LEN	0x0F	/* 8    */
59 #define ENABLE_WD1	0x0001
60 #define ENABLE_WD2	0x0002
61 #define RESET_WD1	0x0010
62 #define RESET_WD2	0x0020
63 #define GEN_SCI		0x0100
64 #define GEN_NMI		0x0200
65 #define GEN_SMI		0x0400
66 #define GEN_RESET	0x0800
71 #define WD1	0
91 module_param(nowayout, bool, 0);
107  * 0 = GEN_RESET
111  * defaults to GEN_RESET (0)
114 module_param(action, int, 0);
116 				"0 = RESET(*)  1 = SMI  2 = NMI  3 = SCI");
135 #define ZF_CTIMEOUT 0xffff
176 		zf_writeb(COUNTER_2, new > 0xff ? 0xff : new);  in zf_set_timer()
187 	unsigned int ctrl_reg = 0;  in zf_timer_off()
210 	unsigned int ctrl_reg = 0;  in zf_timer_on()
215 	zf_writeb(PULSE_LEN, 0xff);  in zf_timer_on()
237 	unsigned int ctrl_reg = 0;  in zf_ping()
240 	zf_writeb(COUNTER_2, 0xff);  in zf_ping()
245 		 * reset event is activated by transition from 0 to 1 on  in zf_ping()
279 			zf_expect_close = 0;  in zf_write()
282 			for (ofs = 0; ofs != count; ofs++) {  in zf_write()
314 		return put_user(0, p);  in zf_ioctl()
321 	return 0;  in zf_ioctl()
326 	if (test_and_set_bit(0, &zf_is_open))  in zf_open()
342 	clear_bit(0, &zf_is_open);  in zf_close()
343 	zf_expect_close = 0;  in zf_close()
344 	return 0;  in zf_close()
398 	if (!ret || ret == 0xffff) {  in zf_init()
403 	if (action <= 3 && action >= 0)  in zf_init()
406 		action = 0;  in zf_init()
428 	zf_set_status(0);  in zf_init()
429 	zf_set_control(0);  in zf_init()
431 	return 0;  in zf_init()