1 // SPDX-License-Identifier: GPL-2.0-or-later
3  * Copyright 2010-2011 Picochip Ltd., Jamie Iles
7  * in the many subsystems. The watchdog has 16 different timeout periods
52 /* There are sixteen TOPs (timeout periods) that can be set in the watchdog. */
79 	unsigned int sec;  member
94 	u32			timeout;  member
105 	return readl(dw_wdt->regs + WDOG_CONTROL_REG_OFFSET) &  in dw_wdt_is_enabled()
113 	val = readl(dw_wdt->regs + WDOG_CONTROL_REG_OFFSET);  in dw_wdt_update_mode()
118 	writel(val, dw_wdt->regs + WDOG_CONTROL_REG_OFFSET);  in dw_wdt_update_mode()
120 	dw_wdt->rmod = rmod;  in dw_wdt_update_mode()
124 					 unsigned int timeout, u32 *top_val)  in dw_wdt_find_best_top()  argument
129 	 * Find a TOP with timeout greater or equal to the requested number.  in dw_wdt_find_best_top()
130 	 * Note we'll select a TOP with maximum timeout if the requested  in dw_wdt_find_best_top()
131 	 * timeout couldn't be reached.  in dw_wdt_find_best_top()
134 		if (dw_wdt->timeouts[idx].sec >= timeout)  in dw_wdt_find_best_top()
139 		--idx;  in dw_wdt_find_best_top()
141 	*top_val = dw_wdt->timeouts[idx].top_val;  in dw_wdt_find_best_top()
143 	return dw_wdt->timeouts[idx].sec;  in dw_wdt_find_best_top()
151 	 * We'll find a timeout greater or equal to one second anyway because  in dw_wdt_get_min_timeout()
155 		if (dw_wdt->timeouts[idx].sec)  in dw_wdt_get_min_timeout()
159 	return dw_wdt->timeouts[idx].sec;  in dw_wdt_get_min_timeout()
164 	struct dw_wdt_timeout *timeout = &dw_wdt->timeouts[DW_WDT_NUM_TOPS - 1];  in dw_wdt_get_max_timeout_ms()  local
167 	msec = (u64)timeout->sec * MSEC_PER_SEC + timeout->msec;  in dw_wdt_get_max_timeout_ms()
174 	int top_val = readl(dw_wdt->regs + WDOG_TIMEOUT_RANGE_REG_OFFSET) & 0xF;  in dw_wdt_get_timeout()
178 		if (dw_wdt->timeouts[idx].top_val == top_val)  in dw_wdt_get_timeout()
183 	 * In IRQ mode due to the two stages counter, the actual timeout is  in dw_wdt_get_timeout()
186 	return dw_wdt->timeouts[idx].sec * dw_wdt->rmod;  in dw_wdt_get_timeout()
193 	writel(WDOG_COUNTER_RESTART_KICK_VALUE, dw_wdt->regs +  in dw_wdt_ping()
202 	unsigned int timeout;  in dw_wdt_set_timeout()  local
206 	 * Note IRQ mode being enabled means having a non-zero pre-timeout  in dw_wdt_set_timeout()
208 	 * requested timeout as possible since DW Watchdog IRQ mode is designed  in dw_wdt_set_timeout()
209 	 * in two stages way - first timeout rises the pre-timeout interrupt,  in dw_wdt_set_timeout()
210 	 * second timeout performs the system reset. So basically the effective  in dw_wdt_set_timeout()
211 	 * watchdog-caused reset happens after two watchdog TOPs elapsed.  in dw_wdt_set_timeout()
213 	timeout = dw_wdt_find_best_top(dw_wdt, DIV_ROUND_UP(top_s, dw_wdt->rmod),  in dw_wdt_set_timeout()
215 	if (dw_wdt->rmod == DW_WDT_RMOD_IRQ)  in dw_wdt_set_timeout()
216 		wdd->pretimeout = timeout;  in dw_wdt_set_timeout()
218 		wdd->pretimeout = 0;  in dw_wdt_set_timeout()
227 	       dw_wdt->regs + WDOG_TIMEOUT_RANGE_REG_OFFSET);  in dw_wdt_set_timeout()
234 	 * In case users set bigger timeout value than HW can support,  in dw_wdt_set_timeout()
236 	 * wdd->max_hw_heartbeat_ms  in dw_wdt_set_timeout()
238 	if (top_s * 1000 <= wdd->max_hw_heartbeat_ms)  in dw_wdt_set_timeout()
239 		wdd->timeout = timeout * dw_wdt->rmod;  in dw_wdt_set_timeout()
241 		wdd->timeout = top_s;  in dw_wdt_set_timeout()
251 	 * We ignore actual value of the timeout passed from user-space  in dw_wdt_set_pretimeout()
256 	dw_wdt_set_timeout(wdd, wdd->timeout);  in dw_wdt_set_pretimeout()
263 	u32 val = readl(dw_wdt->regs + WDOG_CONTROL_REG_OFFSET);  in dw_wdt_arm_system_reset()
266 	if (dw_wdt->rmod == DW_WDT_RMOD_IRQ)  in dw_wdt_arm_system_reset()
272 	writel(val, dw_wdt->regs + WDOG_CONTROL_REG_OFFSET);  in dw_wdt_arm_system_reset()
279 	dw_wdt_set_timeout(wdd, wdd->timeout);  in dw_wdt_start()
280 	dw_wdt_ping(&dw_wdt->wdd);  in dw_wdt_start()
290 	if (!dw_wdt->rst) {  in dw_wdt_stop()
291 		set_bit(WDOG_HW_RUNNING, &wdd->status);  in dw_wdt_stop()
295 	reset_control_assert(dw_wdt->rst);  in dw_wdt_stop()
296 	reset_control_deassert(dw_wdt->rst);  in dw_wdt_stop()
306 	writel(0, dw_wdt->regs + WDOG_TIMEOUT_RANGE_REG_OFFSET);  in dw_wdt_restart()
310 		       dw_wdt->regs + WDOG_COUNTER_RESTART_REG_OFFSET);  in dw_wdt_restart()
323 	unsigned int sec;  in dw_wdt_get_timeleft()  local
326 	val = readl(dw_wdt->regs + WDOG_CURRENT_COUNT_REG_OFFSET);  in dw_wdt_get_timeleft()
327 	sec = val / dw_wdt->rate;  in dw_wdt_get_timeleft()
329 	if (dw_wdt->rmod == DW_WDT_RMOD_IRQ) {  in dw_wdt_get_timeleft()
330 		val = readl(dw_wdt->regs + WDOG_INTERRUPT_STATUS_REG_OFFSET);  in dw_wdt_get_timeleft()
332 			sec += wdd->pretimeout;  in dw_wdt_get_timeleft()
335 	return sec;  in dw_wdt_get_timeleft()
370 	val = readl(dw_wdt->regs + WDOG_INTERRUPT_STATUS_REG_OFFSET);  in dw_wdt_irq()
374 	watchdog_notify_pretimeout(&dw_wdt->wdd);  in dw_wdt_irq()
384 	dw_wdt->control = readl(dw_wdt->regs + WDOG_CONTROL_REG_OFFSET);  in dw_wdt_suspend()
385 	dw_wdt->timeout = readl(dw_wdt->regs + WDOG_TIMEOUT_RANGE_REG_OFFSET);  in dw_wdt_suspend()
387 	clk_disable_unprepare(dw_wdt->pclk);  in dw_wdt_suspend()
388 	clk_disable_unprepare(dw_wdt->clk);  in dw_wdt_suspend()
396 	int err = clk_prepare_enable(dw_wdt->clk);  in dw_wdt_resume()
401 	err = clk_prepare_enable(dw_wdt->pclk);  in dw_wdt_resume()
403 		clk_disable_unprepare(dw_wdt->clk);  in dw_wdt_resume()
407 	writel(dw_wdt->timeout, dw_wdt->regs + WDOG_TIMEOUT_RANGE_REG_OFFSET);  in dw_wdt_resume()
408 	writel(dw_wdt->control, dw_wdt->regs + WDOG_CONTROL_REG_OFFSET);  in dw_wdt_resume()
410 	dw_wdt_ping(&dw_wdt->wdd);  in dw_wdt_resume()
422  * passed TOPs array to pre-calculate the effective timeouts and to sort the
440 		tout.sec = tops[val] / dw_wdt->rate;  in dw_wdt_handle_tops()
442 		do_div(msec, dw_wdt->rate);  in dw_wdt_handle_tops()
443 		tout.msec = msec - ((u64)tout.sec * MSEC_PER_SEC);  in dw_wdt_handle_tops()
450 			dst = &dw_wdt->timeouts[tidx];  in dw_wdt_handle_tops()
451 			if (tout.sec > dst->sec || (tout.sec == dst->sec &&  in dw_wdt_handle_tops()
452 			    tout.msec >= dst->msec))  in dw_wdt_handle_tops()
458 		dw_wdt->timeouts[val] = tout;  in dw_wdt_handle_tops()
473 	data = readl(dw_wdt->regs + WDOG_COMP_PARAMS_1_REG_OFFSET);  in dw_wdt_init_timeouts()
478 			"snps,watchdog-tops", of_tops, DW_WDT_NUM_TOPS,  in dw_wdt_init_timeouts()
490 	if (!dw_wdt->timeouts[DW_WDT_NUM_TOPS - 1].sec) {  in dw_wdt_init_timeouts()
492 		return -EINVAL;  in dw_wdt_init_timeouts()
523 	struct device *dev = dw_wdt->wdd.parent;  in dw_wdt_dbgfs_init()
530 	regset->regs = dw_wdt_dbgfs_regs;  in dw_wdt_dbgfs_init()
531 	regset->nregs = ARRAY_SIZE(dw_wdt_dbgfs_regs);  in dw_wdt_dbgfs_init()
532 	regset->base = dw_wdt->regs;  in dw_wdt_dbgfs_init()
534 	dw_wdt->dbgfs_dir = debugfs_create_dir(dev_name(dev), NULL);  in dw_wdt_dbgfs_init()
536 	debugfs_create_regset32("registers", 0444, dw_wdt->dbgfs_dir, regset);  in dw_wdt_dbgfs_init()
541 	debugfs_remove_recursive(dw_wdt->dbgfs_dir);  in dw_wdt_dbgfs_clear()
553 	struct device *dev = &pdev->dev;  in dw_wdt_drv_probe()
560 		return -ENOMEM;  in dw_wdt_drv_probe()
562 	dw_wdt->regs = devm_platform_ioremap_resource(pdev, 0);  in dw_wdt_drv_probe()
563 	if (IS_ERR(dw_wdt->regs))  in dw_wdt_drv_probe()
564 		return PTR_ERR(dw_wdt->regs);  in dw_wdt_drv_probe()
572 	dw_wdt->clk = devm_clk_get(dev, "tclk");  in dw_wdt_drv_probe()
573 	if (IS_ERR(dw_wdt->clk)) {  in dw_wdt_drv_probe()
574 		dw_wdt->clk = devm_clk_get(dev, NULL);  in dw_wdt_drv_probe()
575 		if (IS_ERR(dw_wdt->clk))  in dw_wdt_drv_probe()
576 			return PTR_ERR(dw_wdt->clk);  in dw_wdt_drv_probe()
579 	ret = clk_prepare_enable(dw_wdt->clk);  in dw_wdt_drv_probe()
583 	dw_wdt->rate = clk_get_rate(dw_wdt->clk);  in dw_wdt_drv_probe()
584 	if (dw_wdt->rate == 0) {  in dw_wdt_drv_probe()
585 		ret = -EINVAL;  in dw_wdt_drv_probe()
596 	dw_wdt->pclk = devm_clk_get_optional(dev, "pclk");  in dw_wdt_drv_probe()
597 	if (IS_ERR(dw_wdt->pclk)) {  in dw_wdt_drv_probe()
598 		ret = PTR_ERR(dw_wdt->pclk);  in dw_wdt_drv_probe()
602 	ret = clk_prepare_enable(dw_wdt->pclk);  in dw_wdt_drv_probe()
606 	dw_wdt->rst = devm_reset_control_get_optional_shared(&pdev->dev, NULL);  in dw_wdt_drv_probe()
607 	if (IS_ERR(dw_wdt->rst)) {  in dw_wdt_drv_probe()
608 		ret = PTR_ERR(dw_wdt->rst);  in dw_wdt_drv_probe()
612 	/* Enable normal reset without pre-timeout by default. */  in dw_wdt_drv_probe()
616 	 * Pre-timeout IRQ is optional, since some hardware may lack support  in dw_wdt_drv_probe()
617 	 * of it. Note we must request rising-edge IRQ, since the lane is left  in dw_wdt_drv_probe()
625 				       pdev->name, dw_wdt);  in dw_wdt_drv_probe()
629 		dw_wdt->wdd.info = &dw_wdt_pt_ident;  in dw_wdt_drv_probe()
631 		if (ret == -EPROBE_DEFER)  in dw_wdt_drv_probe()
634 		dw_wdt->wdd.info = &dw_wdt_ident;  in dw_wdt_drv_probe()
637 	reset_control_deassert(dw_wdt->rst);  in dw_wdt_drv_probe()
643 	wdd = &dw_wdt->wdd;  in dw_wdt_drv_probe()
644 	wdd->ops = &dw_wdt_ops;  in dw_wdt_drv_probe()
645 	wdd->min_timeout = dw_wdt_get_min_timeout(dw_wdt);  in dw_wdt_drv_probe()
646 	wdd->max_hw_heartbeat_ms = dw_wdt_get_max_timeout_ms(dw_wdt);  in dw_wdt_drv_probe()
647 	wdd->parent = dev;  in dw_wdt_drv_probe()
655 	 * timeout. Otherwise use the default or the value provided through  in dw_wdt_drv_probe()
659 		wdd->timeout = dw_wdt_get_timeout(dw_wdt);  in dw_wdt_drv_probe()
660 		set_bit(WDOG_HW_RUNNING, &wdd->status);  in dw_wdt_drv_probe()
662 		wdd->timeout = DW_WDT_DEFAULT_SECONDS;  in dw_wdt_drv_probe()
679 	clk_disable_unprepare(dw_wdt->pclk);  in dw_wdt_drv_probe()
682 	clk_disable_unprepare(dw_wdt->clk);  in dw_wdt_drv_probe()
692 	watchdog_unregister_device(&dw_wdt->wdd);  in dw_wdt_drv_remove()
693 	reset_control_assert(dw_wdt->rst);  in dw_wdt_drv_remove()
694 	clk_disable_unprepare(dw_wdt->pclk);  in dw_wdt_drv_remove()
695 	clk_disable_unprepare(dw_wdt->clk);  in dw_wdt_drv_remove()
702 	{ .compatible = "snps,dw-wdt", },