Lines Matching +full:flash +full:- +full:max +full:- +full:timeout +full:- +full:us
1 // SPDX-License-Identifier: GPL-2.0-or-later
35 { .compatible = "aspeed,ast2400-wdt", .data = &ast2400_config },
36 { .compatible = "aspeed,ast2500-wdt", .data = &ast2500_config },
37 { .compatible = "aspeed,ast2600-wdt", .data = &ast2500_config },
65 * * Drive mode: push-pull vs open-drain
78 * and bit 30 represents push-pull or open-drain. With respect to write, magic
106 wdt->ctrl |= WDT_CTRL_ENABLE; in aspeed_wdt_enable()
108 writel(0, wdt->base + WDT_CTRL); in aspeed_wdt_enable()
109 writel(count, wdt->base + WDT_RELOAD_VALUE); in aspeed_wdt_enable()
110 writel(WDT_RESTART_MAGIC, wdt->base + WDT_RESTART); in aspeed_wdt_enable()
111 writel(wdt->ctrl, wdt->base + WDT_CTRL); in aspeed_wdt_enable()
118 aspeed_wdt_enable(wdt, wdd->timeout * WDT_RATE_1MHZ); in aspeed_wdt_start()
127 wdt->ctrl &= ~WDT_CTRL_ENABLE; in aspeed_wdt_stop()
128 writel(wdt->ctrl, wdt->base + WDT_CTRL); in aspeed_wdt_stop()
137 writel(WDT_RESTART_MAGIC, wdt->base + WDT_RESTART); in aspeed_wdt_ping()
143 unsigned int timeout) in aspeed_wdt_set_timeout() argument
148 wdd->timeout = timeout; in aspeed_wdt_set_timeout()
150 actual = min(timeout, wdd->max_hw_heartbeat_ms * 1000); in aspeed_wdt_set_timeout()
152 writel(actual * WDT_RATE_1MHZ, wdt->base + WDT_RELOAD_VALUE); in aspeed_wdt_set_timeout()
153 writel(WDT_RESTART_MAGIC, wdt->base + WDT_RESTART); in aspeed_wdt_set_timeout()
163 wdt->ctrl &= ~WDT_CTRL_BOOT_SECONDARY; in aspeed_wdt_restart()
176 u32 status = readl(wdt->base + WDT_TIMEOUT_STATUS); in access_cs0_show()
190 return -EINVAL; in access_cs0_store()
194 wdt->base + WDT_CLEAR_TIMEOUT_STATUS); in access_cs0_store()
201 * flash with 'alt-boot' option.
203 * At alternate flash the 'access_cs0' sysfs node provides:
204 * ast2400: a way to get access to the primary SPI flash chip at CS0
207 * (CS0->CS1, CS1->CS0) to (CS0->CS0, CS1->CS1).
209 * Clearing the boot code selection and timeout counter also resets to the
243 struct device *dev = &pdev->dev; in aspeed_wdt_probe()
255 return -ENOMEM; in aspeed_wdt_probe()
257 wdt->base = devm_platform_ioremap_resource(pdev, 0); in aspeed_wdt_probe()
258 if (IS_ERR(wdt->base)) in aspeed_wdt_probe()
259 return PTR_ERR(wdt->base); in aspeed_wdt_probe()
261 wdt->wdd.info = &aspeed_wdt_info; in aspeed_wdt_probe()
262 wdt->wdd.ops = &aspeed_wdt_ops; in aspeed_wdt_probe()
263 wdt->wdd.max_hw_heartbeat_ms = WDT_MAX_TIMEOUT_MS; in aspeed_wdt_probe()
264 wdt->wdd.parent = dev; in aspeed_wdt_probe()
266 wdt->wdd.timeout = WDT_DEFAULT_TIMEOUT; in aspeed_wdt_probe()
267 watchdog_init_timeout(&wdt->wdd, 0, dev); in aspeed_wdt_probe()
269 np = dev->of_node; in aspeed_wdt_probe()
273 return -EINVAL; in aspeed_wdt_probe()
274 config = ofdid->data; in aspeed_wdt_probe()
278 * - ast2400 wdt can run at PCLK, or 1MHz in aspeed_wdt_probe()
279 * - ast2500 only runs at 1MHz, hard coding bit 4 to 1 in aspeed_wdt_probe()
280 * - ast2600 always runs at 1MHz in aspeed_wdt_probe()
284 if (of_device_is_compatible(np, "aspeed,ast2400-wdt")) in aspeed_wdt_probe()
285 wdt->ctrl = WDT_CTRL_1MHZ_CLK; in aspeed_wdt_probe()
288 * Control reset on a per-device basis to ensure the in aspeed_wdt_probe()
291 ret = of_property_read_string(np, "aspeed,reset-type", &reset_type); in aspeed_wdt_probe()
293 wdt->ctrl |= WDT_CTRL_RESET_MODE_SOC | WDT_CTRL_RESET_SYSTEM; in aspeed_wdt_probe()
296 wdt->ctrl |= WDT_CTRL_RESET_MODE_ARM_CPU | in aspeed_wdt_probe()
299 wdt->ctrl |= WDT_CTRL_RESET_MODE_SOC | in aspeed_wdt_probe()
302 wdt->ctrl |= WDT_CTRL_RESET_MODE_FULL_CHIP | in aspeed_wdt_probe()
305 return -EINVAL; in aspeed_wdt_probe()
307 if (of_property_read_bool(np, "aspeed,external-signal")) in aspeed_wdt_probe()
308 wdt->ctrl |= WDT_CTRL_WDT_EXT; in aspeed_wdt_probe()
309 if (of_property_read_bool(np, "aspeed,alt-boot")) in aspeed_wdt_probe()
310 wdt->ctrl |= WDT_CTRL_BOOT_SECONDARY; in aspeed_wdt_probe()
312 if (readl(wdt->base + WDT_CTRL) & WDT_CTRL_ENABLE) { in aspeed_wdt_probe()
315 * write wdt->ctrl to WDT_CTRL to ensure the watchdog's in aspeed_wdt_probe()
319 aspeed_wdt_start(&wdt->wdd); in aspeed_wdt_probe()
320 set_bit(WDOG_HW_RUNNING, &wdt->wdd.status); in aspeed_wdt_probe()
323 if ((of_device_is_compatible(np, "aspeed,ast2500-wdt")) || in aspeed_wdt_probe()
324 (of_device_is_compatible(np, "aspeed,ast2600-wdt"))) { in aspeed_wdt_probe()
325 u32 reg = readl(wdt->base + WDT_RESET_WIDTH); in aspeed_wdt_probe()
327 reg &= config->ext_pulse_width_mask; in aspeed_wdt_probe()
328 if (of_property_read_bool(np, "aspeed,ext-push-pull")) in aspeed_wdt_probe()
333 writel(reg, wdt->base + WDT_RESET_WIDTH); in aspeed_wdt_probe()
335 reg &= config->ext_pulse_width_mask; in aspeed_wdt_probe()
336 if (of_property_read_bool(np, "aspeed,ext-active-high")) in aspeed_wdt_probe()
341 writel(reg, wdt->base + WDT_RESET_WIDTH); in aspeed_wdt_probe()
344 if (!of_property_read_u32(np, "aspeed,ext-pulse-duration", &duration)) { in aspeed_wdt_probe()
345 u32 max_duration = config->ext_pulse_width_mask + 1; in aspeed_wdt_probe()
350 duration = max(1U, min(max_duration, duration)); in aspeed_wdt_probe()
358 * need to offset it - from the datasheet: in aspeed_wdt_probe()
363 * 256us." in aspeed_wdt_probe()
365 * This implies a value of 0 gives a 1us pulse. in aspeed_wdt_probe()
367 writel(duration - 1, wdt->base + WDT_RESET_WIDTH); in aspeed_wdt_probe()
370 status = readl(wdt->base + WDT_TIMEOUT_STATUS); in aspeed_wdt_probe()
372 wdt->wdd.bootstatus = WDIOF_CARDRESET; in aspeed_wdt_probe()
374 if (of_device_is_compatible(np, "aspeed,ast2400-wdt") || in aspeed_wdt_probe()
375 of_device_is_compatible(np, "aspeed,ast2500-wdt")) in aspeed_wdt_probe()
376 wdt->wdd.groups = bswitch_groups; in aspeed_wdt_probe()
381 return devm_watchdog_register_device(dev, &wdt->wdd); in aspeed_wdt_probe()