473 	dma_addr_t pci_base, u32 aspace, u32 cycle)  in tsi148_slave_set()  argument
561 	switch (cycle & (VME_2eSST160 | VME_2eSST267 | VME_2eSST320)) {  in tsi148_slave_set()
573 	/* Setup cycle types */  in tsi148_slave_set()
575 	if (cycle & VME_BLT)  in tsi148_slave_set()
577 	if (cycle & VME_MBLT)  in tsi148_slave_set()
579 	if (cycle & VME_2eVME)  in tsi148_slave_set()
581 	if (cycle & VME_2eSST)  in tsi148_slave_set()
583 	if (cycle & VME_2eSSTB)  in tsi148_slave_set()
591 	if (cycle & VME_SUPER)  in tsi148_slave_set()
593 	if (cycle & VME_USER)  in tsi148_slave_set()
595 	if (cycle & VME_PROG)  in tsi148_slave_set()
597 	if (cycle & VME_DATA)  in tsi148_slave_set()
618 	dma_addr_t *pci_base, u32 *aspace, u32 *cycle)  in tsi148_slave_get()  argument
657 	*cycle = 0;  in tsi148_slave_get()
684 		*cycle |= VME_2eSST160;  in tsi148_slave_get()
686 		*cycle |= VME_2eSST267;  in tsi148_slave_get()
688 		*cycle |= VME_2eSST320;  in tsi148_slave_get()
691 		*cycle |= VME_BLT;  in tsi148_slave_get()
693 		*cycle |= VME_MBLT;  in tsi148_slave_get()
695 		*cycle |= VME_2eVME;  in tsi148_slave_get()
697 		*cycle |= VME_2eSST;  in tsi148_slave_get()
699 		*cycle |= VME_2eSSTB;  in tsi148_slave_get()
702 		*cycle |= VME_SUPER;  in tsi148_slave_get()
704 		*cycle |= VME_USER;  in tsi148_slave_get()
706 		*cycle |= VME_PROG;  in tsi148_slave_get()
708 		*cycle |= VME_DATA;  in tsi148_slave_get()
809 	u32 cycle, u32 dwidth)  in tsi148_master_set()  argument
911 	switch (cycle & (VME_2eSST160 | VME_2eSST267 | VME_2eSST320)) {  in tsi148_master_set()
923 	/* Setup cycle types */  in tsi148_master_set()
924 	if (cycle & VME_BLT) {  in tsi148_master_set()
928 	if (cycle & VME_MBLT) {  in tsi148_master_set()
932 	if (cycle & VME_2eVME) {  in tsi148_master_set()
936 	if (cycle & VME_2eSST) {  in tsi148_master_set()
940 	if (cycle & VME_2eSSTB) {  in tsi148_master_set()
1002 	if (cycle & VME_SUPER)  in tsi148_master_set()
1004 	if (cycle & VME_PROG)  in tsi148_master_set()
1051 	u32 *cycle, u32 *dwidth)  in __tsi148_master_get()  argument
1091 	*cycle = 0;  in __tsi148_master_get()
1119 		*cycle |= VME_2eSST160;  in __tsi148_master_get()
1121 		*cycle |= VME_2eSST267;  in __tsi148_master_get()
1123 		*cycle |= VME_2eSST320;  in __tsi148_master_get()
1125 	/* Setup cycle types */  in __tsi148_master_get()
1127 		*cycle |= VME_SCT;  in __tsi148_master_get()
1129 		*cycle |= VME_BLT;  in __tsi148_master_get()
1131 		*cycle |= VME_MBLT;  in __tsi148_master_get()
1133 		*cycle |= VME_2eVME;  in __tsi148_master_get()
1135 		*cycle |= VME_2eSST;  in __tsi148_master_get()
1137 		*cycle |= VME_2eSSTB;  in __tsi148_master_get()
1140 		*cycle |= VME_SUPER;  in __tsi148_master_get()
1142 		*cycle |= VME_USER;  in __tsi148_master_get()
1145 		*cycle |= VME_PROG;  in __tsi148_master_get()
1147 		*cycle |= VME_DATA;  in __tsi148_master_get()
1161 	u32 *cycle, u32 *dwidth)  in tsi148_master_get()  argument
1168 		cycle, dwidth);  in tsi148_master_get()
1180 	u32 aspace, cycle, dwidth;  in tsi148_master_read()  local
1193 				    &cycle, &dwidth);  in tsi148_master_read()
1206 	 * cycle configured for the transfer is used and splits it  in tsi148_master_read()
1208 	 * overhead of needlessly forcing small transfers for the entire cycle.  in tsi148_master_read()
1266 	u32 aspace, cycle, dwidth;  in tsi148_master_write()  local
1283 				    &cycle, &dwidth);  in tsi148_master_write()
1359  * Perform an RMW cycle on the VME bus.
1420 	u32 aspace, u32 cycle, u32 dwidth)  in tsi148_dma_set_vme_src_attributes()  argument
1427 	switch (cycle & (VME_2eSST160 | VME_2eSST267 | VME_2eSST320)) {  in tsi148_dma_set_vme_src_attributes()
1439 	/* Setup cycle types */  in tsi148_dma_set_vme_src_attributes()
1440 	if (cycle & VME_SCT)  in tsi148_dma_set_vme_src_attributes()
1443 	if (cycle & VME_BLT)  in tsi148_dma_set_vme_src_attributes()
1446 	if (cycle & VME_MBLT)  in tsi148_dma_set_vme_src_attributes()
1449 	if (cycle & VME_2eVME)  in tsi148_dma_set_vme_src_attributes()
1452 	if (cycle & VME_2eSST)  in tsi148_dma_set_vme_src_attributes()
1455 	if (cycle & VME_2eSSTB) {  in tsi148_dma_set_vme_src_attributes()
1509 	if (cycle & VME_SUPER)  in tsi148_dma_set_vme_src_attributes()
1511 	if (cycle & VME_PROG)  in tsi148_dma_set_vme_src_attributes()
1520 	u32 aspace, u32 cycle, u32 dwidth)  in tsi148_dma_set_vme_dest_attributes()  argument
1527 	switch (cycle & (VME_2eSST160 | VME_2eSST267 | VME_2eSST320)) {  in tsi148_dma_set_vme_dest_attributes()
1539 	/* Setup cycle types */  in tsi148_dma_set_vme_dest_attributes()
1540 	if (cycle & VME_SCT)  in tsi148_dma_set_vme_dest_attributes()
1543 	if (cycle & VME_BLT)  in tsi148_dma_set_vme_dest_attributes()
1546 	if (cycle & VME_MBLT)  in tsi148_dma_set_vme_dest_attributes()
1549 	if (cycle & VME_2eVME)  in tsi148_dma_set_vme_dest_attributes()
1552 	if (cycle & VME_2eSST)  in tsi148_dma_set_vme_dest_attributes()
1555 	if (cycle & VME_2eSSTB) {  in tsi148_dma_set_vme_dest_attributes()
1609 	if (cycle & VME_SUPER)  in tsi148_dma_set_vme_dest_attributes()
1611 	if (cycle & VME_PROG)  in tsi148_dma_set_vme_dest_attributes()
1696 			vme_attr->aspace, vme_attr->cycle, vme_attr->dwidth);  in tsi148_dma_list_add()
1733 			vme_attr->aspace, vme_attr->cycle, vme_attr->dwidth);  in tsi148_dma_list_add()
1927 	u32 aspace, u32 cycle)  in tsi148_lm_set()  argument
1970 	if (cycle & VME_SUPER)  in tsi148_lm_set()
1972 	if (cycle & VME_USER)  in tsi148_lm_set()
1974 	if (cycle & VME_PROG)  in tsi148_lm_set()
1976 	if (cycle & VME_DATA)  in tsi148_lm_set()
1994 	unsigned long long *lm_base, u32 *aspace, u32 *cycle)  in tsi148_lm_get()  argument
2026 		*cycle |= VME_SUPER;  in tsi148_lm_get()
2028 		*cycle |= VME_USER;  in tsi148_lm_get()
2030 		*cycle |= VME_PROG;  in tsi148_lm_get()
2032 		*cycle |= VME_DATA;  in tsi148_lm_get()