Lines Matching +full:0 +full:x1100
35 ({ if (status < 0) pr_warn(fmt, ##args); })
38 ({ if (status < 0) { pr_warn(fmt, ##args); return status; } })
41 ({ if (status < 0) { pr_warn(fmt, ##args); goto error; } })
45 #define USB_VENDOR_REQUEST_WRITE_REGISTER 0xA0
46 #define USB_VENDOR_REQUEST_READ_REGISTER 0xA1
55 #define UFX_IOCTL_RETURN_EDID (0xAD)
56 #define UFX_IOCTL_REPORT_DAMAGE (0xAA)
101 atomic_t usb_active; /* 0 = update virtual buffer, but no usb traffic */
112 .xpanstep = 0,
113 .ypanstep = 0,
114 .ywrapstep = 0,
123 {USB_DEVICE(0x0424, 0x9d00),},
124 {USB_DEVICE(0x0424, 0x9d01),},
151 ret = usb_control_msg(dev->udev, usb_rcvctrlpipe(dev->udev, 0), in ufx_reg_read()
160 if (unlikely(ret < 0)) in ufx_reg_read()
161 pr_warn("Failed to read register index 0x%08x\n", index); in ufx_reg_read()
180 ret = usb_control_msg(dev->udev, usb_sndctrlpipe(dev->udev, 0), in ufx_reg_write()
187 if (unlikely(ret < 0)) in ufx_reg_write()
188 pr_warn("Failed to write register index 0x%08x with value " in ufx_reg_write()
189 "0x%08x\n", index, data); in ufx_reg_write()
200 "0x%x", index); in ufx_reg_clear_and_set_bits()
207 "0x%x", index); in ufx_reg_clear_and_set_bits()
209 return 0; in ufx_reg_clear_and_set_bits()
214 return ufx_reg_clear_and_set_bits(dev, index, 0, bits); in ufx_reg_set_bits()
219 return ufx_reg_clear_and_set_bits(dev, index, bits, 0); in ufx_reg_clear_bits()
227 status = ufx_reg_write(dev, 0x3008, 0x00000001); in ufx_lite_reset()
228 check_warn_return(status, "ufx_lite_reset error writing 0x3008"); in ufx_lite_reset()
230 status = ufx_reg_read(dev, 0x3008, &value); in ufx_lite_reset()
231 check_warn_return(status, "ufx_lite_reset error reading 0x3008"); in ufx_lite_reset()
233 return (value == 0) ? 0 : -EIO; in ufx_lite_reset()
242 int status = ufx_reg_read(dev, 0x2004, &dc_sts); in ufx_blank()
243 check_warn_return(status, "ufx_blank error reading 0x2004"); in ufx_blank()
245 status = ufx_reg_read(dev, 0x2000, &dc_ctrl); in ufx_blank()
246 check_warn_return(status, "ufx_blank error reading 0x2000"); in ufx_blank()
249 if ((dc_sts & 0x00000100) || (dc_ctrl & 0x00000100)) in ufx_blank()
250 return 0; in ufx_blank()
253 dc_ctrl |= 0x00000100; in ufx_blank()
254 status = ufx_reg_write(dev, 0x2000, dc_ctrl); in ufx_blank()
255 check_warn_return(status, "ufx_blank error writing 0x2000"); in ufx_blank()
259 return 0; in ufx_blank()
261 for (i = 0; i < 250; i++) { in ufx_blank()
262 status = ufx_reg_read(dev, 0x2004, &dc_sts); in ufx_blank()
263 check_warn_return(status, "ufx_blank error reading 0x2004"); in ufx_blank()
265 if (dc_sts & 0x00000100) in ufx_blank()
266 return 0; in ufx_blank()
279 int status = ufx_reg_read(dev, 0x2004, &dc_sts); in ufx_unblank()
280 check_warn_return(status, "ufx_unblank error reading 0x2004"); in ufx_unblank()
282 status = ufx_reg_read(dev, 0x2000, &dc_ctrl); in ufx_unblank()
283 check_warn_return(status, "ufx_unblank error reading 0x2000"); in ufx_unblank()
286 if (((dc_sts & 0x00000100) == 0) || ((dc_ctrl & 0x00000100) == 0)) in ufx_unblank()
287 return 0; in ufx_unblank()
290 dc_ctrl &= ~0x00000100; in ufx_unblank()
291 status = ufx_reg_write(dev, 0x2000, dc_ctrl); in ufx_unblank()
292 check_warn_return(status, "ufx_unblank error writing 0x2000"); in ufx_unblank()
296 return 0; in ufx_unblank()
298 for (i = 0; i < 250; i++) { in ufx_unblank()
299 status = ufx_reg_read(dev, 0x2004, &dc_sts); in ufx_unblank()
300 check_warn_return(status, "ufx_unblank error reading 0x2004"); in ufx_unblank()
302 if ((dc_sts & 0x00000100) == 0) in ufx_unblank()
303 return 0; in ufx_unblank()
316 int status = ufx_reg_read(dev, 0x2004, &dc_sts); in ufx_disable()
317 check_warn_return(status, "ufx_disable error reading 0x2004"); in ufx_disable()
319 status = ufx_reg_read(dev, 0x2000, &dc_ctrl); in ufx_disable()
320 check_warn_return(status, "ufx_disable error reading 0x2000"); in ufx_disable()
323 if (((dc_sts & 0x00000001) == 0) || ((dc_ctrl & 0x00000001) == 0)) in ufx_disable()
324 return 0; in ufx_disable()
327 dc_ctrl &= ~(0x00000001); in ufx_disable()
328 status = ufx_reg_write(dev, 0x2000, dc_ctrl); in ufx_disable()
329 check_warn_return(status, "ufx_disable error writing 0x2000"); in ufx_disable()
333 return 0; in ufx_disable()
335 for (i = 0; i < 250; i++) { in ufx_disable()
336 status = ufx_reg_read(dev, 0x2004, &dc_sts); in ufx_disable()
337 check_warn_return(status, "ufx_disable error reading 0x2004"); in ufx_disable()
339 if ((dc_sts & 0x00000001) == 0) in ufx_disable()
340 return 0; in ufx_disable()
353 int status = ufx_reg_read(dev, 0x2004, &dc_sts); in ufx_enable()
354 check_warn_return(status, "ufx_enable error reading 0x2004"); in ufx_enable()
356 status = ufx_reg_read(dev, 0x2000, &dc_ctrl); in ufx_enable()
357 check_warn_return(status, "ufx_enable error reading 0x2000"); in ufx_enable()
360 if ((dc_sts & 0x00000001) || (dc_ctrl & 0x00000001)) in ufx_enable()
361 return 0; in ufx_enable()
364 dc_ctrl |= 0x00000001; in ufx_enable()
365 status = ufx_reg_write(dev, 0x2000, dc_ctrl); in ufx_enable()
366 check_warn_return(status, "ufx_enable error writing 0x2000"); in ufx_enable()
370 return 0; in ufx_enable()
372 for (i = 0; i < 250; i++) { in ufx_enable()
373 status = ufx_reg_read(dev, 0x2004, &dc_sts); in ufx_enable()
374 check_warn_return(status, "ufx_enable error reading 0x2004"); in ufx_enable()
376 if (dc_sts & 0x00000001) in ufx_enable()
377 return 0; in ufx_enable()
386 int status = ufx_reg_write(dev, 0x700C, 0x8000000F); in ufx_config_sys_clk()
387 check_warn_return(status, "error writing 0x700C"); in ufx_config_sys_clk()
389 status = ufx_reg_write(dev, 0x7014, 0x0010024F); in ufx_config_sys_clk()
390 check_warn_return(status, "error writing 0x7014"); in ufx_config_sys_clk()
392 status = ufx_reg_write(dev, 0x7010, 0x00000000); in ufx_config_sys_clk()
393 check_warn_return(status, "error writing 0x7010"); in ufx_config_sys_clk()
395 status = ufx_reg_clear_bits(dev, 0x700C, 0x0000000A); in ufx_config_sys_clk()
396 check_warn_return(status, "error clearing PLL1 bypass in 0x700C"); in ufx_config_sys_clk()
399 status = ufx_reg_clear_bits(dev, 0x700C, 0x80000000); in ufx_config_sys_clk()
400 check_warn_return(status, "error clearing output gate in 0x700C"); in ufx_config_sys_clk()
402 return 0; in ufx_config_sys_clk()
407 int status, i = 0; in ufx_config_ddr2()
410 status = ufx_reg_write(dev, 0x0004, 0x001F0F77); in ufx_config_ddr2()
411 check_warn_return(status, "error writing 0x0004"); in ufx_config_ddr2()
413 status = ufx_reg_write(dev, 0x0008, 0xFFF00000); in ufx_config_ddr2()
414 check_warn_return(status, "error writing 0x0008"); in ufx_config_ddr2()
416 status = ufx_reg_write(dev, 0x000C, 0x0FFF2222); in ufx_config_ddr2()
417 check_warn_return(status, "error writing 0x000C"); in ufx_config_ddr2()
419 status = ufx_reg_write(dev, 0x0010, 0x00030814); in ufx_config_ddr2()
420 check_warn_return(status, "error writing 0x0010"); in ufx_config_ddr2()
422 status = ufx_reg_write(dev, 0x0014, 0x00500019); in ufx_config_ddr2()
423 check_warn_return(status, "error writing 0x0014"); in ufx_config_ddr2()
425 status = ufx_reg_write(dev, 0x0018, 0x020D0F15); in ufx_config_ddr2()
426 check_warn_return(status, "error writing 0x0018"); in ufx_config_ddr2()
428 status = ufx_reg_write(dev, 0x001C, 0x02532305); in ufx_config_ddr2()
429 check_warn_return(status, "error writing 0x001C"); in ufx_config_ddr2()
431 status = ufx_reg_write(dev, 0x0020, 0x0B030905); in ufx_config_ddr2()
432 check_warn_return(status, "error writing 0x0020"); in ufx_config_ddr2()
434 status = ufx_reg_write(dev, 0x0024, 0x00000827); in ufx_config_ddr2()
435 check_warn_return(status, "error writing 0x0024"); in ufx_config_ddr2()
437 status = ufx_reg_write(dev, 0x0028, 0x00000000); in ufx_config_ddr2()
438 check_warn_return(status, "error writing 0x0028"); in ufx_config_ddr2()
440 status = ufx_reg_write(dev, 0x002C, 0x00000042); in ufx_config_ddr2()
441 check_warn_return(status, "error writing 0x002C"); in ufx_config_ddr2()
443 status = ufx_reg_write(dev, 0x0030, 0x09520000); in ufx_config_ddr2()
444 check_warn_return(status, "error writing 0x0030"); in ufx_config_ddr2()
446 status = ufx_reg_write(dev, 0x0034, 0x02223314); in ufx_config_ddr2()
447 check_warn_return(status, "error writing 0x0034"); in ufx_config_ddr2()
449 status = ufx_reg_write(dev, 0x0038, 0x00430043); in ufx_config_ddr2()
450 check_warn_return(status, "error writing 0x0038"); in ufx_config_ddr2()
452 status = ufx_reg_write(dev, 0x003C, 0xF00F000F); in ufx_config_ddr2()
453 check_warn_return(status, "error writing 0x003C"); in ufx_config_ddr2()
455 status = ufx_reg_write(dev, 0x0040, 0xF380F00F); in ufx_config_ddr2()
456 check_warn_return(status, "error writing 0x0040"); in ufx_config_ddr2()
458 status = ufx_reg_write(dev, 0x0044, 0xF00F0496); in ufx_config_ddr2()
459 check_warn_return(status, "error writing 0x0044"); in ufx_config_ddr2()
461 status = ufx_reg_write(dev, 0x0048, 0x03080406); in ufx_config_ddr2()
462 check_warn_return(status, "error writing 0x0048"); in ufx_config_ddr2()
464 status = ufx_reg_write(dev, 0x004C, 0x00001000); in ufx_config_ddr2()
465 check_warn_return(status, "error writing 0x004C"); in ufx_config_ddr2()
467 status = ufx_reg_write(dev, 0x005C, 0x00000007); in ufx_config_ddr2()
468 check_warn_return(status, "error writing 0x005C"); in ufx_config_ddr2()
470 status = ufx_reg_write(dev, 0x0100, 0x54F00012); in ufx_config_ddr2()
471 check_warn_return(status, "error writing 0x0100"); in ufx_config_ddr2()
473 status = ufx_reg_write(dev, 0x0104, 0x00004012); in ufx_config_ddr2()
474 check_warn_return(status, "error writing 0x0104"); in ufx_config_ddr2()
476 status = ufx_reg_write(dev, 0x0118, 0x40404040); in ufx_config_ddr2()
477 check_warn_return(status, "error writing 0x0118"); in ufx_config_ddr2()
479 status = ufx_reg_write(dev, 0x0000, 0x00000001); in ufx_config_ddr2()
480 check_warn_return(status, "error writing 0x0000"); in ufx_config_ddr2()
483 status = ufx_reg_read(dev, 0x0000, &tmp); in ufx_config_ddr2()
484 check_warn_return(status, "error reading 0x0000"); in ufx_config_ddr2()
486 if (all_bits_set(tmp, 0xC0000000)) in ufx_config_ddr2()
487 return 0; in ufx_config_ddr2()
490 pr_err("DDR2 initialisation timed out, reg 0x0000=0x%08x", tmp); in ufx_config_ddr2()
552 for (div_q0 = 0; div_q0 < 7; div_q0++) { in ufx_calc_pll_values()
576 for (div_q1 = 0; div_q1 < 7; div_q1++) { in ufx_calc_pll_values()
590 * because a value of 0 = divide by 1 */ in ufx_calc_pll_values()
601 if (min_error == 0) in ufx_calc_pll_values()
615 struct pll_values asic_pll = {0}; in ufx_config_pix_clk()
629 status = ufx_reg_write(dev, 0x7000, 0x8000000F); in ufx_config_pix_clk()
630 check_warn_return(status, "error writing 0x7000"); in ufx_config_pix_clk()
634 status = ufx_reg_write(dev, 0x7008, value); in ufx_config_pix_clk()
635 check_warn_return(status, "error writing 0x7008"); in ufx_config_pix_clk()
639 status = ufx_reg_write(dev, 0x7004, value); in ufx_config_pix_clk()
640 check_warn_return(status, "error writing 0x7004"); in ufx_config_pix_clk()
642 status = ufx_reg_clear_bits(dev, 0x7000, 0x00000005); in ufx_config_pix_clk()
644 "error clearing PLL0 bypass bits in 0x7000"); in ufx_config_pix_clk()
647 status = ufx_reg_clear_bits(dev, 0x7000, 0x0000000A); in ufx_config_pix_clk()
649 "error clearing PLL1 bypass bits in 0x7000"); in ufx_config_pix_clk()
652 status = ufx_reg_clear_bits(dev, 0x7000, 0x80000000); in ufx_config_pix_clk()
653 check_warn_return(status, "error clearing gate bits in 0x7000"); in ufx_config_pix_clk()
655 return 0; in ufx_config_pix_clk()
664 int status = ufx_reg_write(dev, 0x8028, 0); in ufx_set_vid_mode()
667 status = ufx_reg_write(dev, 0x8024, 0); in ufx_set_vid_mode()
680 status = ufx_reg_write(dev, 0x2000, 0x00000104); in ufx_set_vid_mode()
681 check_warn_return(status, "ufx_set_vid_mode error writing 0x2000"); in ufx_set_vid_mode()
692 status = ufx_reg_write(dev, 0x2008, temp); in ufx_set_vid_mode()
693 check_warn_return(status, "ufx_set_vid_mode error writing 0x2008"); in ufx_set_vid_mode()
696 status = ufx_reg_write(dev, 0x200C, temp); in ufx_set_vid_mode()
697 check_warn_return(status, "ufx_set_vid_mode error writing 0x200C"); in ufx_set_vid_mode()
700 status = ufx_reg_write(dev, 0x2010, temp); in ufx_set_vid_mode()
701 check_warn_return(status, "ufx_set_vid_mode error writing 0x2010"); in ufx_set_vid_mode()
712 status = ufx_reg_write(dev, 0x2014, temp); in ufx_set_vid_mode()
713 check_warn_return(status, "ufx_set_vid_mode error writing 0x2014"); in ufx_set_vid_mode()
716 status = ufx_reg_write(dev, 0x2018, temp); in ufx_set_vid_mode()
717 check_warn_return(status, "ufx_set_vid_mode error writing 0x2018"); in ufx_set_vid_mode()
720 status = ufx_reg_write(dev, 0x201C, temp); in ufx_set_vid_mode()
721 check_warn_return(status, "ufx_set_vid_mode error writing 0x201C"); in ufx_set_vid_mode()
723 status = ufx_reg_write(dev, 0x2020, 0x00000000); in ufx_set_vid_mode()
724 check_warn_return(status, "ufx_set_vid_mode error writing 0x2020"); in ufx_set_vid_mode()
726 status = ufx_reg_write(dev, 0x2024, 0x00000000); in ufx_set_vid_mode()
727 check_warn_return(status, "ufx_set_vid_mode error writing 0x2024"); in ufx_set_vid_mode()
731 temp = (temp + 7) & (~0x7); in ufx_set_vid_mode()
732 status = ufx_reg_write(dev, 0x2028, temp); in ufx_set_vid_mode()
733 check_warn_return(status, "ufx_set_vid_mode error writing 0x2028"); in ufx_set_vid_mode()
736 status = ufx_reg_write(dev, 0x2040, 0); in ufx_set_vid_mode()
737 check_warn_return(status, "ufx_set_vid_mode error writing 0x2040"); in ufx_set_vid_mode()
739 status = ufx_reg_write(dev, 0x2044, 0); in ufx_set_vid_mode()
740 check_warn_return(status, "ufx_set_vid_mode error writing 0x2044"); in ufx_set_vid_mode()
742 status = ufx_reg_write(dev, 0x2048, 0); in ufx_set_vid_mode()
743 check_warn_return(status, "ufx_set_vid_mode error writing 0x2048"); in ufx_set_vid_mode()
746 temp = 0x00000001; in ufx_set_vid_mode()
748 temp |= 0x00000010; in ufx_set_vid_mode()
751 temp |= 0x00000008; in ufx_set_vid_mode()
753 status = ufx_reg_write(dev, 0x2040, temp); in ufx_set_vid_mode()
754 check_warn_return(status, "ufx_set_vid_mode error writing 0x2040"); in ufx_set_vid_mode()
765 status = ufx_reg_write(dev, 0x8028, 0x00000003); in ufx_set_vid_mode()
769 status = ufx_reg_write(dev, 0x8024, 0x00000007); in ufx_set_vid_mode()
772 return 0; in ufx_set_vid_mode()
782 if (vma->vm_pgoff > (~0UL >> PAGE_SHIFT)) in ufx_ops_mmap()
794 while (size > 0) { in ufx_ops_mmap()
804 size = 0; in ufx_ops_mmap()
807 return 0; in ufx_ops_mmap()
821 *((u32 *)&cmd[0]) = cpu_to_le32(0x01); in ufx_raw_rect()
832 *((u32 *)&cmd[8]) = cpu_to_le32(0); in ufx_raw_rect()
835 cmd[10] = cpu_to_le16(0x4000 | dev->info->var.xres); in ufx_raw_rect()
841 for (line = 0; line < height; line++) { in ufx_raw_rect()
853 int len, status, urb_lines, start_line = 0; in ufx_handle_damage()
855 if ((width <= 0) || (height <= 0) || in ufx_handle_damage()
861 return 0; in ufx_handle_damage()
867 return 0; in ufx_handle_damage()
879 memset(urb->transfer_buffer, 0, urb->transfer_buffer_length); in ufx_handle_damage()
890 return 0; in ufx_handle_damage()
906 if (result > 0) { in ufx_ops_write()
907 int start = max((int)(offset / info->fix.line_length), 0); in ufx_ops_write()
911 ufx_handle_damage(dev, 0, start, info->var.xres, lines); in ufx_ops_write()
972 const int x = 0; in ufx_dpy_deferred_io()
992 return 0; in ufx_ops_ioctl()
999 return 0; in ufx_ops_ioctl()
1015 if (area->x < 0) in ufx_ops_ioctl()
1016 area->x = 0; in ufx_ops_ioctl()
1021 if (area->y < 0) in ufx_ops_ioctl()
1022 area->y = 0; in ufx_ops_ioctl()
1030 return 0; in ufx_ops_ioctl()
1038 int err = 0; in ufx_ops_setcolreg()
1047 ((red & 0xf800) >> 1) | in ufx_ops_setcolreg()
1048 ((green & 0xf800) >> 6) | ((blue & 0xf800) >> 11); in ufx_ops_setcolreg()
1050 /* 0:5:6:5 */ in ufx_ops_setcolreg()
1052 ((red & 0xf800)) | in ufx_ops_setcolreg()
1053 ((green & 0xfc00) >> 5) | ((blue & 0xf800) >> 11); in ufx_ops_setcolreg()
1070 if (user == 0 && !console) in ufx_ops_open()
1099 return 0; in ufx_ops_open()
1112 if (dev->urbs.count > 0) in ufx_free()
1137 if (info->cmap.len != 0) in ufx_free_framebuffer_work()
1166 if (dev->virtualized && (dev->fb_count == 0)) in ufx_ops_release()
1169 if ((dev->fb_count == 0) && (info->fbdefio)) { in ufx_ops_release()
1180 return 0; in ufx_ops_release()
1191 return 0; in ufx_is_valid_mode()
1197 return 0; in ufx_is_valid_mode()
1207 const struct fb_bitfield red = { 11, 5, 0 }; in ufx_var_color_format()
1208 const struct fb_bitfield green = { 5, 6, 0 }; in ufx_var_color_format()
1209 const struct fb_bitfield blue = { 0, 5, 0 }; in ufx_var_color_format()
1234 return 0; in ufx_ops_check_var()
1247 if ((result == 0) && (dev->fb_count == 0)) { in ufx_ops_set_par()
1250 for (i = 0; i < info->fix.smem_len / 2; i++) in ufx_ops_set_par()
1251 pix_framebuffer[i] = 0x37e6; in ufx_ops_set_par()
1253 ufx_handle_damage(dev, 0, 0, info->var.xres, info->var.yres); in ufx_ops_set_par()
1268 return 0; in ufx_ops_blank()
1319 return 0; in ufx_realloc_framebuffer()
1329 int status = ufx_reg_write(dev, 0x106C, 0x00); in ufx_i2c_init()
1334 status = ufx_reg_write(dev, 0x1018, 12); in ufx_i2c_init()
1335 check_warn_return(status, "error writing 0x1018"); in ufx_i2c_init()
1338 status = ufx_reg_write(dev, 0x1014, 6); in ufx_i2c_init()
1339 check_warn_return(status, "error writing 0x1014"); in ufx_i2c_init()
1341 status = ufx_reg_read(dev, 0x1000, &tmp); in ufx_i2c_init()
1342 check_warn_return(status, "error reading 0x1000"); in ufx_i2c_init()
1345 tmp &= ~(0x06); in ufx_i2c_init()
1346 tmp |= 0x02; in ufx_i2c_init()
1349 tmp &= ~(0x10); in ufx_i2c_init()
1352 tmp |= 0x21; in ufx_i2c_init()
1354 status = ufx_reg_write(dev, 0x1000, tmp); in ufx_i2c_init()
1355 check_warn_return(status, "error writing 0x1000"); in ufx_i2c_init()
1357 /* Set normal tx using target address 0 */ in ufx_i2c_init()
1358 status = ufx_reg_clear_and_set_bits(dev, 0x1004, 0xC00, 0x000); in ufx_i2c_init()
1359 check_warn_return(status, "error setting TX mode bits in 0x1004"); in ufx_i2c_init()
1362 status = ufx_reg_write(dev, 0x106C, 0x01); in ufx_i2c_init()
1365 return 0; in ufx_i2c_init()
1371 int status = ufx_reg_write(dev, 0x106C, 0x00); in ufx_i2c_configure()
1374 status = ufx_reg_write(dev, 0x3010, 0x00000000); in ufx_i2c_configure()
1375 check_warn_return(status, "failed to write 0x3010"); in ufx_i2c_configure()
1378 status = ufx_reg_clear_and_set_bits(dev, 0x1004, 0x3FF, (0xA0 >> 1)); in ufx_i2c_configure()
1379 check_warn_return(status, "failed to set TAR bits in 0x1004"); in ufx_i2c_configure()
1381 status = ufx_reg_write(dev, 0x106C, 0x01); in ufx_i2c_configure()
1384 return 0; in ufx_i2c_configure()
1394 for (i = 0; i < 15; i++) { in ufx_i2c_wait_busy()
1395 status = ufx_reg_read(dev, 0x1100, &tmp); in ufx_i2c_wait_busy()
1396 check_warn_return(status, "0x1100 read failed"); in ufx_i2c_wait_busy()
1399 if ((tmp & 0x80000000) == 0) { in ufx_i2c_wait_busy()
1400 if (tmp & 0x20000000) { in ufx_i2c_wait_busy()
1401 pr_warn("I2C read failed, 0x1100=0x%08x", tmp); in ufx_i2c_wait_busy()
1405 return 0; in ufx_i2c_wait_busy()
1414 status = ufx_reg_write(dev, 0x1100, 0x40000000); in ufx_i2c_wait_busy()
1415 check_warn_return(status, "0x1100 write failed"); in ufx_i2c_wait_busy()
1429 if (status < 0) { in ufx_read_edid()
1434 memset(edid, 0xff, EDID_LENGTH); in ufx_read_edid()
1437 for (i = 0; i < 2; i++) { in ufx_read_edid()
1438 u32 temp = 0x28070000 | (63 << 20) | (((u32)(i * 64)) << 8); in ufx_read_edid()
1439 status = ufx_reg_write(dev, 0x1100, temp); in ufx_read_edid()
1440 check_warn_return(status, "Failed to write 0x1100"); in ufx_read_edid()
1442 temp |= 0x80000000; in ufx_read_edid()
1443 status = ufx_reg_write(dev, 0x1100, temp); in ufx_read_edid()
1444 check_warn_return(status, "Failed to write 0x1100"); in ufx_read_edid()
1449 for (j = 0; j < 16; j++) { in ufx_read_edid()
1450 u32 data_reg_addr = 0x1110 + (j * 4); in ufx_read_edid()
1457 for (i = 0; i < 16; i++) { in ufx_read_edid()
1458 if (edid[i] != 0xFF) { in ufx_read_edid()
1464 pr_warn("edid data contains all 0xff"); in ufx_read_edid()
1479 * Returns 0 if successful */
1485 int i, result = 0, tries = 3; in ufx_setup_modes()
1497 memset(&info->monspecs, 0, sizeof(info->monspecs)); in ufx_setup_modes()
1508 if (info->monspecs.modedb_len > 0) { in ufx_setup_modes()
1516 if (info->monspecs.modedb_len == 0) { in ufx_setup_modes()
1521 if (info->monspecs.modedb_len > 0) in ufx_setup_modes()
1527 if (info->monspecs.modedb_len == 0) { in ufx_setup_modes()
1530 if (info->monspecs.modedb_len > 0) { in ufx_setup_modes()
1540 if (info->monspecs.modedb_len > 0) { in ufx_setup_modes()
1542 for (i = 0; i < info->monspecs.modedb_len; i++) { in ufx_setup_modes()
1557 struct fb_videomode fb_vmode = {0}; in ufx_setup_modes()
1564 for (i = 0; i < VESA_MODEDB_SIZE; i++) { in ufx_setup_modes()
1582 if ((default_vmode != NULL) && (dev->fb_count == 0)) { in ufx_setup_modes()
1651 info = framebuffer_alloc(0, &usbdev->dev); in ufx_usb_probe()
1660 retval = fb_alloc_cmap(&info->cmap, 256, 0); in ufx_usb_probe()
1661 if (retval < 0) { in ufx_usb_probe()
1671 retval = ufx_reg_read(dev, 0x3000, &id_rev); in ufx_usb_probe()
1672 check_warn_goto_error(retval, "error %d reading 0x3000 register from device", retval); in ufx_usb_probe()
1673 dev_dbg(dev->gdev, "ID_REV register value 0x%08x", id_rev); in ufx_usb_probe()
1675 retval = ufx_reg_read(dev, 0x3004, &fpga_rev); in ufx_usb_probe()
1676 check_warn_goto_error(retval, "error %d reading 0x3004 register from device", retval); in ufx_usb_probe()
1677 dev_dbg(dev->gdev, "FPGA_REV register value 0x%08x", fpga_rev); in ufx_usb_probe()
1696 retval = ufx_setup_modes(dev, info, NULL, 0); in ufx_usb_probe()
1699 retval = ufx_reg_set_bits(dev, 0x4000, 0x00000001); in ufx_usb_probe()
1721 return 0; in ufx_usb_probe()
1752 atomic_set(&dev->usb_active, 0); in ufx_usb_disconnect()
1757 if (dev->fb_count == 0) in ufx_usb_disconnect()
1758 schedule_delayed_work(&dev->free_framebuffer_work, 0); in ufx_usb_disconnect()
1802 schedule_delayed_work(&unode->release_urb_work, 0); in ufx_urb_completion()
1845 int i = 0; in ufx_alloc_urb_list()
1864 urb = usb_alloc_urb(0, GFP_KERNEL); in ufx_alloc_urb_list()
1900 int ret = 0; in ufx_get_urb()