Lines Matching +full:shut +full:- +full:down +full:- +full:gpios
1 // SPDX-License-Identifier: GPL-2.0
10 * some D2-state (APM-style) sleep/wakeup code for use on some PowerMacs,
11 * and the necessary bits to re-initialize from scratch a few chips found
33 * - enable D2 sleep in some IBM Thinkpads
34 * - special case for Samsung P35
103 for (id = radeon_workaround_list; id->ident != NULL; id++ ) in radeon_apply_workarounds()
104 if ((id->subsystem_vendor == rinfo->pdev->subsystem_vendor ) && in radeon_apply_workarounds()
105 (id->subsystem_device == rinfo->pdev->subsystem_device )) { in radeon_apply_workarounds()
109 ", enabling workaround\n", id->ident); in radeon_apply_workarounds()
111 rinfo->pm_mode |= id->pm_mode_modifier; in radeon_apply_workarounds()
113 if (id->new_reinit_func != NULL) in radeon_apply_workarounds()
114 rinfo->reinit_func = id->new_reinit_func; in radeon_apply_workarounds()
135 if ((rinfo->family == CHIP_FAMILY_RV100) && (!rinfo->is_mobility)) { in radeon_pm_disable_dynamic_mode()
136 if (rinfo->has_CRTC2) { in radeon_pm_disable_dynamic_mode()
153 if (!rinfo->has_CRTC2) { in radeon_pm_disable_dynamic_mode()
166 if (rinfo->family == CHIP_FAMILY_RV350) { in radeon_pm_disable_dynamic_mode()
232 if (rinfo->is_mobility) { in radeon_pm_disable_dynamic_mode()
249 else if (rinfo->family == CHIP_FAMILY_R300 || in radeon_pm_disable_dynamic_mode()
250 rinfo->family == CHIP_FAMILY_R350) { in radeon_pm_disable_dynamic_mode()
261 if (rinfo->family == CHIP_FAMILY_R300 || rinfo->family == CHIP_FAMILY_R350) { in radeon_pm_disable_dynamic_mode()
275 if (rinfo->is_IGP) { in radeon_pm_disable_dynamic_mode()
286 else if (rinfo->is_mobility) { in radeon_pm_disable_dynamic_mode()
304 if (rinfo->is_mobility) { in radeon_pm_disable_dynamic_mode()
336 if (!rinfo->has_CRTC2) { in radeon_pm_enable_dynamic_mode()
351 if (rinfo->family == CHIP_FAMILY_RV350) { in radeon_pm_enable_dynamic_mode()
421 if (rinfo->vram_width == 64) { in radeon_pm_enable_dynamic_mode()
436 if (rinfo->family == CHIP_FAMILY_R300 || rinfo->family == CHIP_FAMILY_R350) { in radeon_pm_enable_dynamic_mode()
473 if ((rinfo->family == CHIP_FAMILY_RV250 && in radeon_pm_enable_dynamic_mode()
475 ((rinfo->family == CHIP_FAMILY_RV100) && in radeon_pm_enable_dynamic_mode()
483 if ((rinfo->family == CHIP_FAMILY_RV200) || in radeon_pm_enable_dynamic_mode()
484 (rinfo->family == CHIP_FAMILY_RV250) || in radeon_pm_enable_dynamic_mode()
485 (rinfo->family == CHIP_FAMILY_RV280)) { in radeon_pm_enable_dynamic_mode()
490 if (((rinfo->family == CHIP_FAMILY_RV200) || in radeon_pm_enable_dynamic_mode()
491 (rinfo->family == CHIP_FAMILY_RV250)) && in radeon_pm_enable_dynamic_mode()
501 if (((rinfo->family == CHIP_FAMILY_RV200) || in radeon_pm_enable_dynamic_mode()
502 (rinfo->family == CHIP_FAMILY_RV250)) && in radeon_pm_enable_dynamic_mode()
528 if (rinfo->is_mobility) { in radeon_pm_enable_dynamic_mode()
564 rinfo->save_regs[0] = INPLL(PLL_PWRMGT_CNTL); in radeon_pm_save_regs()
565 rinfo->save_regs[1] = INPLL(CLK_PWRMGT_CNTL); in radeon_pm_save_regs()
566 rinfo->save_regs[2] = INPLL(MCLK_CNTL); in radeon_pm_save_regs()
567 rinfo->save_regs[3] = INPLL(SCLK_CNTL); in radeon_pm_save_regs()
568 rinfo->save_regs[4] = INPLL(CLK_PIN_CNTL); in radeon_pm_save_regs()
569 rinfo->save_regs[5] = INPLL(VCLK_ECP_CNTL); in radeon_pm_save_regs()
570 rinfo->save_regs[6] = INPLL(PIXCLKS_CNTL); in radeon_pm_save_regs()
571 rinfo->save_regs[7] = INPLL(MCLK_MISC); in radeon_pm_save_regs()
572 rinfo->save_regs[8] = INPLL(P2PLL_CNTL); in radeon_pm_save_regs()
574 rinfo->save_regs[9] = INREG(DISP_MISC_CNTL); in radeon_pm_save_regs()
575 rinfo->save_regs[10] = INREG(DISP_PWR_MAN); in radeon_pm_save_regs()
576 rinfo->save_regs[11] = INREG(LVDS_GEN_CNTL); in radeon_pm_save_regs()
577 rinfo->save_regs[13] = INREG(TV_DAC_CNTL); in radeon_pm_save_regs()
578 rinfo->save_regs[14] = INREG(BUS_CNTL1); in radeon_pm_save_regs()
579 rinfo->save_regs[15] = INREG(CRTC_OFFSET_CNTL); in radeon_pm_save_regs()
580 rinfo->save_regs[16] = INREG(AGP_CNTL); in radeon_pm_save_regs()
581 rinfo->save_regs[17] = (INREG(CRTC_GEN_CNTL) & 0xfdffffff) | 0x04000000; in radeon_pm_save_regs()
582 rinfo->save_regs[18] = (INREG(CRTC2_GEN_CNTL) & 0xfdffffff) | 0x04000000; in radeon_pm_save_regs()
583 rinfo->save_regs[19] = INREG(GPIOPAD_A); in radeon_pm_save_regs()
584 rinfo->save_regs[20] = INREG(GPIOPAD_EN); in radeon_pm_save_regs()
585 rinfo->save_regs[21] = INREG(GPIOPAD_MASK); in radeon_pm_save_regs()
586 rinfo->save_regs[22] = INREG(ZV_LCDPAD_A); in radeon_pm_save_regs()
587 rinfo->save_regs[23] = INREG(ZV_LCDPAD_EN); in radeon_pm_save_regs()
588 rinfo->save_regs[24] = INREG(ZV_LCDPAD_MASK); in radeon_pm_save_regs()
589 rinfo->save_regs[25] = INREG(GPIO_VGA_DDC); in radeon_pm_save_regs()
590 rinfo->save_regs[26] = INREG(GPIO_DVI_DDC); in radeon_pm_save_regs()
591 rinfo->save_regs[27] = INREG(GPIO_MONID); in radeon_pm_save_regs()
592 rinfo->save_regs[28] = INREG(GPIO_CRT2_DDC); in radeon_pm_save_regs()
594 rinfo->save_regs[29] = INREG(SURFACE_CNTL); in radeon_pm_save_regs()
595 rinfo->save_regs[30] = INREG(MC_FB_LOCATION); in radeon_pm_save_regs()
596 rinfo->save_regs[31] = INREG(DISPLAY_BASE_ADDR); in radeon_pm_save_regs()
597 rinfo->save_regs[32] = INREG(MC_AGP_LOCATION); in radeon_pm_save_regs()
598 rinfo->save_regs[33] = INREG(CRTC2_DISPLAY_BASE_ADDR); in radeon_pm_save_regs()
600 rinfo->save_regs[34] = INPLL(SCLK_MORE_CNTL); in radeon_pm_save_regs()
601 rinfo->save_regs[35] = INREG(MEM_SDRAM_MODE_REG); in radeon_pm_save_regs()
602 rinfo->save_regs[36] = INREG(BUS_CNTL); in radeon_pm_save_regs()
603 rinfo->save_regs[39] = INREG(RBBM_CNTL); in radeon_pm_save_regs()
604 rinfo->save_regs[40] = INREG(DAC_CNTL); in radeon_pm_save_regs()
605 rinfo->save_regs[41] = INREG(HOST_PATH_CNTL); in radeon_pm_save_regs()
606 rinfo->save_regs[37] = INREG(MPP_TB_CONFIG); in radeon_pm_save_regs()
607 rinfo->save_regs[38] = INREG(FCP_CNTL); in radeon_pm_save_regs()
609 if (rinfo->is_mobility) { in radeon_pm_save_regs()
610 rinfo->save_regs[12] = INREG(LVDS_PLL_CNTL); in radeon_pm_save_regs()
611 rinfo->save_regs[43] = INPLL(pllSSPLL_CNTL); in radeon_pm_save_regs()
612 rinfo->save_regs[44] = INPLL(pllSSPLL_REF_DIV); in radeon_pm_save_regs()
613 rinfo->save_regs[45] = INPLL(pllSSPLL_DIV_0); in radeon_pm_save_regs()
614 rinfo->save_regs[90] = INPLL(pllSS_INT_CNTL); in radeon_pm_save_regs()
615 rinfo->save_regs[91] = INPLL(pllSS_TST_CNTL); in radeon_pm_save_regs()
616 rinfo->save_regs[81] = INREG(LVDS_GEN_CNTL); in radeon_pm_save_regs()
619 if (rinfo->family >= CHIP_FAMILY_RV200) { in radeon_pm_save_regs()
620 rinfo->save_regs[42] = INREG(MEM_REFRESH_CNTL); in radeon_pm_save_regs()
621 rinfo->save_regs[46] = INREG(MC_CNTL); in radeon_pm_save_regs()
622 rinfo->save_regs[47] = INREG(MC_INIT_GFX_LAT_TIMER); in radeon_pm_save_regs()
623 rinfo->save_regs[48] = INREG(MC_INIT_MISC_LAT_TIMER); in radeon_pm_save_regs()
624 rinfo->save_regs[49] = INREG(MC_TIMING_CNTL); in radeon_pm_save_regs()
625 rinfo->save_regs[50] = INREG(MC_READ_CNTL_AB); in radeon_pm_save_regs()
626 rinfo->save_regs[51] = INREG(MC_IOPAD_CNTL); in radeon_pm_save_regs()
627 rinfo->save_regs[52] = INREG(MC_CHIP_IO_OE_CNTL_AB); in radeon_pm_save_regs()
628 rinfo->save_regs[53] = INREG(MC_DEBUG); in radeon_pm_save_regs()
630 rinfo->save_regs[54] = INREG(PAMAC0_DLY_CNTL); in radeon_pm_save_regs()
631 rinfo->save_regs[55] = INREG(PAMAC1_DLY_CNTL); in radeon_pm_save_regs()
632 rinfo->save_regs[56] = INREG(PAD_CTLR_MISC); in radeon_pm_save_regs()
633 rinfo->save_regs[57] = INREG(FW_CNTL); in radeon_pm_save_regs()
635 if (rinfo->family >= CHIP_FAMILY_R300) { in radeon_pm_save_regs()
636 rinfo->save_regs[58] = INMC(rinfo, ixR300_MC_MC_INIT_WR_LAT_TIMER); in radeon_pm_save_regs()
637 rinfo->save_regs[59] = INMC(rinfo, ixR300_MC_IMP_CNTL); in radeon_pm_save_regs()
638 rinfo->save_regs[60] = INMC(rinfo, ixR300_MC_CHP_IO_CNTL_C0); in radeon_pm_save_regs()
639 rinfo->save_regs[61] = INMC(rinfo, ixR300_MC_CHP_IO_CNTL_C1); in radeon_pm_save_regs()
640 rinfo->save_regs[62] = INMC(rinfo, ixR300_MC_CHP_IO_CNTL_D0); in radeon_pm_save_regs()
641 rinfo->save_regs[63] = INMC(rinfo, ixR300_MC_CHP_IO_CNTL_D1); in radeon_pm_save_regs()
642 rinfo->save_regs[64] = INMC(rinfo, ixR300_MC_BIST_CNTL_3); in radeon_pm_save_regs()
643 rinfo->save_regs[65] = INMC(rinfo, ixR300_MC_CHP_IO_CNTL_A0); in radeon_pm_save_regs()
644 rinfo->save_regs[66] = INMC(rinfo, ixR300_MC_CHP_IO_CNTL_A1); in radeon_pm_save_regs()
645 rinfo->save_regs[67] = INMC(rinfo, ixR300_MC_CHP_IO_CNTL_B0); in radeon_pm_save_regs()
646 rinfo->save_regs[68] = INMC(rinfo, ixR300_MC_CHP_IO_CNTL_B1); in radeon_pm_save_regs()
647 rinfo->save_regs[69] = INMC(rinfo, ixR300_MC_DEBUG_CNTL); in radeon_pm_save_regs()
648 rinfo->save_regs[70] = INMC(rinfo, ixR300_MC_DLL_CNTL); in radeon_pm_save_regs()
649 rinfo->save_regs[71] = INMC(rinfo, ixR300_MC_IMP_CNTL_0); in radeon_pm_save_regs()
650 rinfo->save_regs[72] = INMC(rinfo, ixR300_MC_ELPIDA_CNTL); in radeon_pm_save_regs()
651 rinfo->save_regs[96] = INMC(rinfo, ixR300_MC_READ_CNTL_CD); in radeon_pm_save_regs()
653 rinfo->save_regs[59] = INMC(rinfo, ixMC_IMP_CNTL); in radeon_pm_save_regs()
654 rinfo->save_regs[65] = INMC(rinfo, ixMC_CHP_IO_CNTL_A0); in radeon_pm_save_regs()
655 rinfo->save_regs[66] = INMC(rinfo, ixMC_CHP_IO_CNTL_A1); in radeon_pm_save_regs()
656 rinfo->save_regs[67] = INMC(rinfo, ixMC_CHP_IO_CNTL_B0); in radeon_pm_save_regs()
657 rinfo->save_regs[68] = INMC(rinfo, ixMC_CHP_IO_CNTL_B1); in radeon_pm_save_regs()
658 rinfo->save_regs[71] = INMC(rinfo, ixMC_IMP_CNTL_0); in radeon_pm_save_regs()
661 rinfo->save_regs[73] = INPLL(pllMPLL_CNTL); in radeon_pm_save_regs()
662 rinfo->save_regs[74] = INPLL(pllSPLL_CNTL); in radeon_pm_save_regs()
663 rinfo->save_regs[75] = INPLL(pllMPLL_AUX_CNTL); in radeon_pm_save_regs()
664 rinfo->save_regs[76] = INPLL(pllSPLL_AUX_CNTL); in radeon_pm_save_regs()
665 rinfo->save_regs[77] = INPLL(pllM_SPLL_REF_FB_DIV); in radeon_pm_save_regs()
666 rinfo->save_regs[78] = INPLL(pllAGP_PLL_CNTL); in radeon_pm_save_regs()
667 rinfo->save_regs[79] = INREG(PAMAC2_DLY_CNTL); in radeon_pm_save_regs()
669 rinfo->save_regs[80] = INREG(OV0_BASE_ADDR); in radeon_pm_save_regs()
670 rinfo->save_regs[82] = INREG(FP_GEN_CNTL); in radeon_pm_save_regs()
671 rinfo->save_regs[83] = INREG(FP2_GEN_CNTL); in radeon_pm_save_regs()
672 rinfo->save_regs[84] = INREG(TMDS_CNTL); in radeon_pm_save_regs()
673 rinfo->save_regs[85] = INREG(TMDS_TRANSMITTER_CNTL); in radeon_pm_save_regs()
674 rinfo->save_regs[86] = INREG(DISP_OUTPUT_CNTL); in radeon_pm_save_regs()
675 rinfo->save_regs[87] = INREG(DISP_HW_DEBUG); in radeon_pm_save_regs()
676 rinfo->save_regs[88] = INREG(TV_MASTER_CNTL); in radeon_pm_save_regs()
677 rinfo->save_regs[89] = INPLL(pllP2PLL_REF_DIV); in radeon_pm_save_regs()
678 rinfo->save_regs[92] = INPLL(pllPPLL_DIV_0); in radeon_pm_save_regs()
679 rinfo->save_regs[93] = INPLL(pllPPLL_CNTL); in radeon_pm_save_regs()
680 rinfo->save_regs[94] = INREG(GRPH_BUFFER_CNTL); in radeon_pm_save_regs()
681 rinfo->save_regs[95] = INREG(GRPH2_BUFFER_CNTL); in radeon_pm_save_regs()
682 rinfo->save_regs[96] = INREG(HDP_DEBUG); in radeon_pm_save_regs()
683 rinfo->save_regs[97] = INPLL(pllMDLL_CKO); in radeon_pm_save_regs()
684 rinfo->save_regs[98] = INPLL(pllMDLL_RDCKA); in radeon_pm_save_regs()
685 rinfo->save_regs[99] = INPLL(pllMDLL_RDCKB); in radeon_pm_save_regs()
690 OUTPLL(P2PLL_CNTL, rinfo->save_regs[8] & 0xFFFFFFFE); /* First */ in radeon_pm_restore_regs()
692 OUTPLL(PLL_PWRMGT_CNTL, rinfo->save_regs[0]); in radeon_pm_restore_regs()
693 OUTPLL(CLK_PWRMGT_CNTL, rinfo->save_regs[1]); in radeon_pm_restore_regs()
694 OUTPLL(MCLK_CNTL, rinfo->save_regs[2]); in radeon_pm_restore_regs()
695 OUTPLL(SCLK_CNTL, rinfo->save_regs[3]); in radeon_pm_restore_regs()
696 OUTPLL(CLK_PIN_CNTL, rinfo->save_regs[4]); in radeon_pm_restore_regs()
697 OUTPLL(VCLK_ECP_CNTL, rinfo->save_regs[5]); in radeon_pm_restore_regs()
698 OUTPLL(PIXCLKS_CNTL, rinfo->save_regs[6]); in radeon_pm_restore_regs()
699 OUTPLL(MCLK_MISC, rinfo->save_regs[7]); in radeon_pm_restore_regs()
700 if (rinfo->family == CHIP_FAMILY_RV350) in radeon_pm_restore_regs()
701 OUTPLL(SCLK_MORE_CNTL, rinfo->save_regs[34]); in radeon_pm_restore_regs()
703 OUTREG(SURFACE_CNTL, rinfo->save_regs[29]); in radeon_pm_restore_regs()
704 OUTREG(MC_FB_LOCATION, rinfo->save_regs[30]); in radeon_pm_restore_regs()
705 OUTREG(DISPLAY_BASE_ADDR, rinfo->save_regs[31]); in radeon_pm_restore_regs()
706 OUTREG(MC_AGP_LOCATION, rinfo->save_regs[32]); in radeon_pm_restore_regs()
707 OUTREG(CRTC2_DISPLAY_BASE_ADDR, rinfo->save_regs[33]); in radeon_pm_restore_regs()
708 OUTREG(CNFG_MEMSIZE, rinfo->video_ram); in radeon_pm_restore_regs()
710 OUTREG(DISP_MISC_CNTL, rinfo->save_regs[9]); in radeon_pm_restore_regs()
711 OUTREG(DISP_PWR_MAN, rinfo->save_regs[10]); in radeon_pm_restore_regs()
712 OUTREG(LVDS_GEN_CNTL, rinfo->save_regs[11]); in radeon_pm_restore_regs()
713 OUTREG(LVDS_PLL_CNTL,rinfo->save_regs[12]); in radeon_pm_restore_regs()
714 OUTREG(TV_DAC_CNTL, rinfo->save_regs[13]); in radeon_pm_restore_regs()
715 OUTREG(BUS_CNTL1, rinfo->save_regs[14]); in radeon_pm_restore_regs()
716 OUTREG(CRTC_OFFSET_CNTL, rinfo->save_regs[15]); in radeon_pm_restore_regs()
717 OUTREG(AGP_CNTL, rinfo->save_regs[16]); in radeon_pm_restore_regs()
718 OUTREG(CRTC_GEN_CNTL, rinfo->save_regs[17]); in radeon_pm_restore_regs()
719 OUTREG(CRTC2_GEN_CNTL, rinfo->save_regs[18]); in radeon_pm_restore_regs()
720 OUTPLL(P2PLL_CNTL, rinfo->save_regs[8]); in radeon_pm_restore_regs()
722 OUTREG(GPIOPAD_A, rinfo->save_regs[19]); in radeon_pm_restore_regs()
723 OUTREG(GPIOPAD_EN, rinfo->save_regs[20]); in radeon_pm_restore_regs()
724 OUTREG(GPIOPAD_MASK, rinfo->save_regs[21]); in radeon_pm_restore_regs()
725 OUTREG(ZV_LCDPAD_A, rinfo->save_regs[22]); in radeon_pm_restore_regs()
726 OUTREG(ZV_LCDPAD_EN, rinfo->save_regs[23]); in radeon_pm_restore_regs()
727 OUTREG(ZV_LCDPAD_MASK, rinfo->save_regs[24]); in radeon_pm_restore_regs()
728 OUTREG(GPIO_VGA_DDC, rinfo->save_regs[25]); in radeon_pm_restore_regs()
729 OUTREG(GPIO_DVI_DDC, rinfo->save_regs[26]); in radeon_pm_restore_regs()
730 OUTREG(GPIO_MONID, rinfo->save_regs[27]); in radeon_pm_restore_regs()
731 OUTREG(GPIO_CRT2_DDC, rinfo->save_regs[28]); in radeon_pm_restore_regs()
751 if (rinfo->family <= CHIP_FAMILY_RV280) { in radeon_pm_program_v2clk()
783 if (rinfo->family <= CHIP_FAMILY_RV280) { in radeon_pm_low_current()
863 if (rinfo->family <= CHIP_FAMILY_RV280) in radeon_pm_setup_for_suspend()
963 if (rinfo->family <= CHIP_FAMILY_RV280) { in radeon_pm_setup_for_suspend()
1204 OUTMC(rinfo, ixR300_MC_DLL_CNTL, rinfo->save_regs[70]); in radeon_pm_enable_dll_m10()
1269 if (rinfo->family == CHIP_FAMILY_RV350) { in radeon_pm_full_reset_sdram()
1270 u32 sdram_mode_reg = rinfo->save_regs[35]; in radeon_pm_full_reset_sdram()
1296 if (rinfo->of_node != NULL) { in radeon_pm_full_reset_sdram()
1299 mrtable = of_get_property(rinfo->of_node, "ATY,MRT", &size); in radeon_pm_full_reset_sdram()
1330 else if (!rinfo->is_mobility && rinfo->family == CHIP_FAMILY_RV200) { in radeon_pm_full_reset_sdram()
1353 else if (rinfo->is_mobility && rinfo->family == CHIP_FAMILY_RV100) { in radeon_pm_full_reset_sdram()
1376 /* Complete & re-enable refresh */ in radeon_pm_full_reset_sdram()
1383 else if (rinfo->is_mobility) { in radeon_pm_full_reset_sdram()
1403 if (rinfo->family <= CHIP_FAMILY_RV250) { in radeon_pm_full_reset_sdram()
1411 else if (rinfo->family == CHIP_FAMILY_RV280) { in radeon_pm_full_reset_sdram()
1417 /* Complete & re-enable refresh */ in radeon_pm_full_reset_sdram()
1491 tmp = (tmp & 0xff00fffful) | (rinfo->save_regs[77] & 0x00ff0000ul); in radeon_pm_start_mclk_sclk()
1511 tmp |= rinfo->save_regs[3] & SCLK_CNTL__SCLK_SRC_SEL_MASK; in radeon_pm_start_mclk_sclk()
1526 tmp = (tmp & 0xffff00fful) | (rinfo->save_regs[77] & 0x0000ff00ul); in radeon_pm_start_mclk_sclk()
1536 /* Un-reset MPLL */ in radeon_pm_start_mclk_sclk()
1545 tmp |= rinfo->save_regs[2] & 0xffff; in radeon_pm_start_mclk_sclk()
1570 OUTPLL(pllSS_INT_CNTL, rinfo->save_regs[90] & ~3); in radeon_pm_m10_disable_spread_spectrum()
1594 OUTPLL(pllSSPLL_CNTL, rinfo->save_regs[43] | 3); in radeon_pm_m10_enable_lvds_spread_spectrum()
1597 OUTPLL(pllSSPLL_REF_DIV, rinfo->save_regs[44]); in radeon_pm_m10_enable_lvds_spread_spectrum()
1598 OUTPLL(pllSSPLL_DIV_0, rinfo->save_regs[45]); in radeon_pm_m10_enable_lvds_spread_spectrum()
1606 OUTPLL(pllSS_INT_CNTL, rinfo->save_regs[90]); in radeon_pm_m10_enable_lvds_spread_spectrum()
1622 OUTPLL(pllSCLK_MORE_CNTL, rinfo->save_regs[34]); in radeon_pm_m10_enable_lvds_spread_spectrum()
1623 OUTPLL(pllSS_TST_CNTL, rinfo->save_regs[91]); in radeon_pm_m10_enable_lvds_spread_spectrum()
1625 /* The trace reads that one here, waiting for something to settle down ? */ in radeon_pm_m10_enable_lvds_spread_spectrum()
1650 tmp = (tmp & ~PPLL_REF_DIV_MASK) | rinfo->pll.ref_div; in radeon_pm_restore_pixel_pll()
1666 OUTPLL(pllPPLL_DIV_0, rinfo->save_regs[92]); in radeon_pm_restore_pixel_pll()
1692 OUTREG(MC_CNTL, rinfo->save_regs[46]); in radeon_pm_m10_reconfigure_mc()
1693 OUTREG(MC_INIT_GFX_LAT_TIMER, rinfo->save_regs[47]); in radeon_pm_m10_reconfigure_mc()
1694 OUTREG(MC_INIT_MISC_LAT_TIMER, rinfo->save_regs[48]); in radeon_pm_m10_reconfigure_mc()
1696 rinfo->save_regs[35] & ~MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE); in radeon_pm_m10_reconfigure_mc()
1697 OUTREG(MC_TIMING_CNTL, rinfo->save_regs[49]); in radeon_pm_m10_reconfigure_mc()
1698 OUTREG(MEM_REFRESH_CNTL, rinfo->save_regs[42]); in radeon_pm_m10_reconfigure_mc()
1699 OUTREG(MC_READ_CNTL_AB, rinfo->save_regs[50]); in radeon_pm_m10_reconfigure_mc()
1700 OUTREG(MC_CHIP_IO_OE_CNTL_AB, rinfo->save_regs[52]); in radeon_pm_m10_reconfigure_mc()
1701 OUTREG(MC_IOPAD_CNTL, rinfo->save_regs[51]); in radeon_pm_m10_reconfigure_mc()
1702 OUTREG(MC_DEBUG, rinfo->save_regs[53]); in radeon_pm_m10_reconfigure_mc()
1704 OUTMC(rinfo, ixR300_MC_MC_INIT_WR_LAT_TIMER, rinfo->save_regs[58]); in radeon_pm_m10_reconfigure_mc()
1705 OUTMC(rinfo, ixR300_MC_IMP_CNTL, rinfo->save_regs[59]); in radeon_pm_m10_reconfigure_mc()
1706 OUTMC(rinfo, ixR300_MC_CHP_IO_CNTL_C0, rinfo->save_regs[60]); in radeon_pm_m10_reconfigure_mc()
1707 OUTMC(rinfo, ixR300_MC_CHP_IO_CNTL_C1, rinfo->save_regs[61]); in radeon_pm_m10_reconfigure_mc()
1708 OUTMC(rinfo, ixR300_MC_CHP_IO_CNTL_D0, rinfo->save_regs[62]); in radeon_pm_m10_reconfigure_mc()
1709 OUTMC(rinfo, ixR300_MC_CHP_IO_CNTL_D1, rinfo->save_regs[63]); in radeon_pm_m10_reconfigure_mc()
1710 OUTMC(rinfo, ixR300_MC_BIST_CNTL_3, rinfo->save_regs[64]); in radeon_pm_m10_reconfigure_mc()
1711 OUTMC(rinfo, ixR300_MC_CHP_IO_CNTL_A0, rinfo->save_regs[65]); in radeon_pm_m10_reconfigure_mc()
1712 OUTMC(rinfo, ixR300_MC_CHP_IO_CNTL_A1, rinfo->save_regs[66]); in radeon_pm_m10_reconfigure_mc()
1713 OUTMC(rinfo, ixR300_MC_CHP_IO_CNTL_B0, rinfo->save_regs[67]); in radeon_pm_m10_reconfigure_mc()
1714 OUTMC(rinfo, ixR300_MC_CHP_IO_CNTL_B1, rinfo->save_regs[68]); in radeon_pm_m10_reconfigure_mc()
1715 OUTMC(rinfo, ixR300_MC_DEBUG_CNTL, rinfo->save_regs[69]); in radeon_pm_m10_reconfigure_mc()
1716 OUTMC(rinfo, ixR300_MC_DLL_CNTL, rinfo->save_regs[70]); in radeon_pm_m10_reconfigure_mc()
1717 OUTMC(rinfo, ixR300_MC_IMP_CNTL_0, rinfo->save_regs[71]); in radeon_pm_m10_reconfigure_mc()
1718 OUTMC(rinfo, ixR300_MC_ELPIDA_CNTL, rinfo->save_regs[72]); in radeon_pm_m10_reconfigure_mc()
1719 OUTMC(rinfo, ixR300_MC_READ_CNTL_CD, rinfo->save_regs[96]); in radeon_pm_m10_reconfigure_mc()
1728 OUTREG(MC_AGP_LOCATION, rinfo->save_regs[32]); in radeon_reinitialize_M10()
1729 OUTREG(DISPLAY_BASE_ADDR, rinfo->save_regs[31]); in radeon_reinitialize_M10()
1730 OUTREG(CRTC2_DISPLAY_BASE_ADDR, rinfo->save_regs[33]); in radeon_reinitialize_M10()
1731 OUTREG(MC_FB_LOCATION, rinfo->save_regs[30]); in radeon_reinitialize_M10()
1732 OUTREG(OV0_BASE_ADDR, rinfo->save_regs[80]); in radeon_reinitialize_M10()
1733 OUTREG(CNFG_MEMSIZE, rinfo->video_ram); in radeon_reinitialize_M10()
1734 OUTREG(BUS_CNTL, rinfo->save_regs[36]); in radeon_reinitialize_M10()
1735 OUTREG(BUS_CNTL1, rinfo->save_regs[14]); in radeon_reinitialize_M10()
1736 OUTREG(MPP_TB_CONFIG, rinfo->save_regs[37]); in radeon_reinitialize_M10()
1737 OUTREG(FCP_CNTL, rinfo->save_regs[38]); in radeon_reinitialize_M10()
1738 OUTREG(RBBM_CNTL, rinfo->save_regs[39]); in radeon_reinitialize_M10()
1739 OUTREG(DAC_CNTL, rinfo->save_regs[40]); in radeon_reinitialize_M10()
1771 OUTREG(AGP_CNTL, rinfo->save_regs[16]); in radeon_reinitialize_M10()
1772 OUTREG(HOST_PATH_CNTL, rinfo->save_regs[41]); in radeon_reinitialize_M10()
1773 OUTREG(DISP_MISC_CNTL, rinfo->save_regs[9]); in radeon_reinitialize_M10()
1776 tmp = rinfo->save_regs[1] in radeon_reinitialize_M10()
1781 OUTREG(PAD_CTLR_MISC, rinfo->save_regs[56]); in radeon_reinitialize_M10()
1782 OUTREG(FW_CNTL, rinfo->save_regs[57]); in radeon_reinitialize_M10()
1783 OUTREG(HDP_DEBUG, rinfo->save_regs[96]); in radeon_reinitialize_M10()
1784 OUTREG(PAMAC0_DLY_CNTL, rinfo->save_regs[54]); in radeon_reinitialize_M10()
1785 OUTREG(PAMAC1_DLY_CNTL, rinfo->save_regs[55]); in radeon_reinitialize_M10()
1786 OUTREG(PAMAC2_DLY_CNTL, rinfo->save_regs[79]); in radeon_reinitialize_M10()
1803 OUTPLL(pllCLK_PIN_CNTL, rinfo->save_regs[4]); in radeon_reinitialize_M10()
1806 tmp = rinfo->save_regs[2] & 0xff000000; in radeon_reinitialize_M10()
1855 OUTPLL(pllM_SPLL_REF_FB_DIV, rinfo->save_regs[77]); in radeon_reinitialize_M10()
1856 OUTPLL(pllMPLL_AUX_CNTL, rinfo->save_regs[75]); in radeon_reinitialize_M10()
1857 OUTPLL(pllSPLL_AUX_CNTL, rinfo->save_regs[76]); in radeon_reinitialize_M10()
1860 OUTPLL(pllPPLL_CNTL, rinfo->save_regs[93] | 0x3); in radeon_reinitialize_M10()
1861 OUTPLL(pllP2PLL_CNTL, rinfo->save_regs[8] | 0x3); in radeon_reinitialize_M10()
1862 OUTPLL(pllMPLL_CNTL, rinfo->save_regs[73] | 0x03); in radeon_reinitialize_M10()
1863 OUTPLL(pllSPLL_CNTL, rinfo->save_regs[74] | 0x03); in radeon_reinitialize_M10()
1866 OUTMC(rinfo, ixR300_MC_DLL_CNTL, rinfo->save_regs[70]); in radeon_reinitialize_M10()
1869 OUTPLL(pllMDLL_RDCKA, rinfo->save_regs[98] | 0xff); in radeon_reinitialize_M10()
1875 OUTPLL(pllPLL_PWRMGT_CNTL, rinfo->save_regs[0]); in radeon_reinitialize_M10()
1894 /* Full reset sdrams, this also re-inits the MDLL */ in radeon_reinitialize_M10()
1910 OUTREG(FP_GEN_CNTL, rinfo->save_regs[82]); in radeon_reinitialize_M10()
1911 OUTREG(FP2_GEN_CNTL, rinfo->save_regs[83]); in radeon_reinitialize_M10()
1913 /* Set LVDS registers but keep interface & pll down */ in radeon_reinitialize_M10()
1914 OUTREG(LVDS_GEN_CNTL, rinfo->save_regs[11] & in radeon_reinitialize_M10()
1916 OUTREG(LVDS_PLL_CNTL, (rinfo->save_regs[12] & ~0xf0000) | 0x20000); in radeon_reinitialize_M10()
1918 OUTREG(DISP_OUTPUT_CNTL, rinfo->save_regs[86]); in radeon_reinitialize_M10()
1921 OUTREG(GPIOPAD_A, rinfo->save_regs[19]); in radeon_reinitialize_M10()
1922 OUTREG(GPIOPAD_EN, rinfo->save_regs[20]); in radeon_reinitialize_M10()
1923 OUTREG(GPIOPAD_MASK, rinfo->save_regs[21]); in radeon_reinitialize_M10()
1927 writeb(0, rinfo->fb_base + i); in radeon_reinitialize_M10()
1934 OUTREG(GRPH_BUFFER_CNTL, rinfo->save_regs[94]); in radeon_reinitialize_M10()
1935 OUTREG(GRPH2_BUFFER_CNTL, rinfo->save_regs[95]); in radeon_reinitialize_M10()
1953 OUTREG(MC_CNTL, rinfo->save_regs[46]); in radeon_pm_m9p_reconfigure_mc()
1954 OUTREG(MC_INIT_GFX_LAT_TIMER, rinfo->save_regs[47]); in radeon_pm_m9p_reconfigure_mc()
1955 OUTREG(MC_INIT_MISC_LAT_TIMER, rinfo->save_regs[48]); in radeon_pm_m9p_reconfigure_mc()
1957 rinfo->save_regs[35] & ~MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE); in radeon_pm_m9p_reconfigure_mc()
1958 OUTREG(MC_TIMING_CNTL, rinfo->save_regs[49]); in radeon_pm_m9p_reconfigure_mc()
1959 OUTREG(MC_READ_CNTL_AB, rinfo->save_regs[50]); in radeon_pm_m9p_reconfigure_mc()
1960 OUTREG(MEM_REFRESH_CNTL, rinfo->save_regs[42]); in radeon_pm_m9p_reconfigure_mc()
1961 OUTREG(MC_IOPAD_CNTL, rinfo->save_regs[51]); in radeon_pm_m9p_reconfigure_mc()
1962 OUTREG(MC_DEBUG, rinfo->save_regs[53]); in radeon_pm_m9p_reconfigure_mc()
1963 OUTREG(MC_CHIP_IO_OE_CNTL_AB, rinfo->save_regs[52]); in radeon_pm_m9p_reconfigure_mc()
1965 OUTMC(rinfo, ixMC_IMP_CNTL, rinfo->save_regs[59] /*0x00f460d6*/); in radeon_pm_m9p_reconfigure_mc()
1966 OUTMC(rinfo, ixMC_CHP_IO_CNTL_A0, rinfo->save_regs[65] /*0xfecfa666*/); in radeon_pm_m9p_reconfigure_mc()
1967 OUTMC(rinfo, ixMC_CHP_IO_CNTL_A1, rinfo->save_regs[66] /*0x141555ff*/); in radeon_pm_m9p_reconfigure_mc()
1968 OUTMC(rinfo, ixMC_CHP_IO_CNTL_B0, rinfo->save_regs[67] /*0xfecfa666*/); in radeon_pm_m9p_reconfigure_mc()
1969 OUTMC(rinfo, ixMC_CHP_IO_CNTL_B1, rinfo->save_regs[68] /*0x141555ff*/); in radeon_pm_m9p_reconfigure_mc()
1970 OUTMC(rinfo, ixMC_IMP_CNTL_0, rinfo->save_regs[71] /*0x00009249*/); in radeon_pm_m9p_reconfigure_mc()
1972 OUTREG(CNFG_MEMSIZE, rinfo->video_ram); in radeon_pm_m9p_reconfigure_mc()
1982 OUTREG(SURFACE_CNTL, rinfo->save_regs[29]); in radeon_reinitialize_M9P()
1983 OUTREG(MC_AGP_LOCATION, rinfo->save_regs[32]); in radeon_reinitialize_M9P()
1984 OUTREG(DISPLAY_BASE_ADDR, rinfo->save_regs[31]); in radeon_reinitialize_M9P()
1985 OUTREG(CRTC2_DISPLAY_BASE_ADDR, rinfo->save_regs[33]); in radeon_reinitialize_M9P()
1986 OUTREG(MC_FB_LOCATION, rinfo->save_regs[30]); in radeon_reinitialize_M9P()
1987 OUTREG(OV0_BASE_ADDR, rinfo->save_regs[80]); in radeon_reinitialize_M9P()
1988 OUTREG(BUS_CNTL, rinfo->save_regs[36]); in radeon_reinitialize_M9P()
1989 OUTREG(BUS_CNTL1, rinfo->save_regs[14]); in radeon_reinitialize_M9P()
1990 OUTREG(MPP_TB_CONFIG, rinfo->save_regs[37]); in radeon_reinitialize_M9P()
1991 OUTREG(FCP_CNTL, rinfo->save_regs[38]); in radeon_reinitialize_M9P()
1992 OUTREG(RBBM_CNTL, rinfo->save_regs[39]); in radeon_reinitialize_M9P()
1994 OUTREG(DAC_CNTL, rinfo->save_regs[40]); in radeon_reinitialize_M9P()
2021 OUTPLL(pllAGP_PLL_CNTL, rinfo->save_regs[78]); in radeon_reinitialize_M9P()
2023 OUTREG(PAMAC0_DLY_CNTL, rinfo->save_regs[54]); in radeon_reinitialize_M9P()
2024 OUTREG(PAMAC1_DLY_CNTL, rinfo->save_regs[55]); in radeon_reinitialize_M9P()
2025 OUTREG(PAMAC2_DLY_CNTL, rinfo->save_regs[79]); in radeon_reinitialize_M9P()
2027 OUTREG(AGP_CNTL, rinfo->save_regs[16]); in radeon_reinitialize_M9P()
2028 OUTREG(HOST_PATH_CNTL, rinfo->save_regs[41]); /* MacOS sets that to 0 !!! */ in radeon_reinitialize_M9P()
2029 OUTREG(DISP_MISC_CNTL, rinfo->save_regs[9]); in radeon_reinitialize_M9P()
2031 tmp = rinfo->save_regs[1] in radeon_reinitialize_M9P()
2036 OUTREG(FW_CNTL, rinfo->save_regs[57]); in radeon_reinitialize_M9P()
2043 OUTPLL(pllCLK_PIN_CNTL, rinfo->save_regs[4]); in radeon_reinitialize_M9P()
2046 tmp = rinfo->save_regs[2] & 0xff000000; in radeon_reinitialize_M9P()
2085 OUTPLL(pllM_SPLL_REF_FB_DIV, rinfo->save_regs[77]); in radeon_reinitialize_M9P()
2086 OUTPLL(pllMPLL_AUX_CNTL, rinfo->save_regs[75]); in radeon_reinitialize_M9P()
2087 OUTPLL(pllSPLL_AUX_CNTL, rinfo->save_regs[76]); in radeon_reinitialize_M9P()
2090 OUTPLL(pllPPLL_CNTL, rinfo->save_regs[93] | 0x3); in radeon_reinitialize_M9P()
2091 OUTPLL(pllP2PLL_CNTL, rinfo->save_regs[8] | 0x3); in radeon_reinitialize_M9P()
2094 OUTPLL(pllMPLL_CNTL, rinfo->save_regs[73] | 0x03); in radeon_reinitialize_M9P()
2095 OUTPLL(pllSPLL_CNTL, rinfo->save_regs[74] | 0x03); in radeon_reinitialize_M9P()
2104 tmp = rinfo->save_regs[0]; in radeon_reinitialize_M9P()
2126 /* Full reset sdrams, this also re-inits the MDLL */ in radeon_reinitialize_M9P()
2141 /* Restore TV stuff, make sure TV DAC is down */ in radeon_reinitialize_M9P()
2142 OUTREG(TV_MASTER_CNTL, rinfo->save_regs[88]); in radeon_reinitialize_M9P()
2143 OUTREG(TV_DAC_CNTL, rinfo->save_regs[13] | 0x07000000); in radeon_reinitialize_M9P()
2145 /* Restore GPIOS. MacOS does some magic here with one of the GPIO bits, in radeon_reinitialize_M9P()
2150 OUTREG(GPIOPAD_A, rinfo->save_regs[19]); in radeon_reinitialize_M9P()
2151 OUTREG(GPIOPAD_EN, rinfo->save_regs[20]); in radeon_reinitialize_M9P()
2152 OUTREG(GPIOPAD_MASK, rinfo->save_regs[21]); in radeon_reinitialize_M9P()
2158 tmp |= rinfo->save_regs[34] & 0xffff0000; in radeon_reinitialize_M9P()
2163 tmp |= rinfo->save_regs[34] & 0xffff0000; in radeon_reinitialize_M9P()
2167 OUTREG(LVDS_GEN_CNTL, rinfo->save_regs[11] & in radeon_reinitialize_M9P()
2170 OUTREG(LVDS_PLL_CNTL, (rinfo->save_regs[12] & ~0xf0000) | 0x20000); in radeon_reinitialize_M9P()
2175 writeb(0, rinfo->fb_base + i); in radeon_reinitialize_M9P()
2178 OUTPLL(pllSSPLL_REF_DIV, rinfo->save_regs[44] /*0x3f */); in radeon_reinitialize_M9P()
2179 OUTPLL(pllSSPLL_DIV_0, rinfo->save_regs[45] /*0x000081bb */); in radeon_reinitialize_M9P()
2191 OUTPLL(pllSS_INT_CNTL, rinfo->save_regs[90] & ~3);/*0x0020300c*/ in radeon_reinitialize_M9P()
2195 OUTPLL(pllPPLL_REF_DIV, rinfo->pll.ref_div); in radeon_reinitialize_M9P()
2196 OUTPLL(pllPPLL_DIV_0, rinfo->save_regs[92]); in radeon_reinitialize_M9P()
2203 OUTREG(GRPH_BUFFER_CNTL, rinfo->save_regs[94]); in radeon_reinitialize_M9P()
2204 OUTREG(GRPH2_BUFFER_CNTL, rinfo->save_regs[95]); in radeon_reinitialize_M9P()
2221 OUTREG(MC_AGP_LOCATION, rinfo->save_regs[32]);
2222 OUTREG(DISPLAY_BASE_ADDR, rinfo->save_regs[31]);
2223 OUTREG(CRTC2_DISPLAY_BASE_ADDR, rinfo->save_regs[33]);
2224 OUTREG(MC_FB_LOCATION, rinfo->save_regs[30]);
2225 OUTREG(BUS_CNTL, rinfo->save_regs[36]);
2226 OUTREG(RBBM_CNTL, rinfo->save_regs[39]);
2242 OUTREG(SURFACE_CNTL, rinfo->save_regs[29]);
2243 OUTREG(AGP_CNTL, rinfo->save_regs[16]);
2244 OUTREG(HOST_PATH_CNTL, rinfo->save_regs[41]);
2245 OUTREG(DISP_MISC_CNTL, rinfo->save_regs[9]);
2373 OUTREG(CNFG_MEMSIZE, rinfo->video_ram);
2387 OUTPLL(CLK_PIN_CNTL, rinfo->save_regs[4]);
2388 OUTPLL(CLK_PWRMGT_CNTL, rinfo->save_regs[1]);
2389 OUTPLL(PLL_PWRMGT_CNTL, rinfo->save_regs[0]);
2451 tmp = (tmp & ~PPLL_REF_DIV_MASK) | rinfo->pll.ref_div;
2524 pci_read_config_word(rinfo->pdev, in radeonfb_whack_power_state()
2525 rinfo->pdev->pm_cap + PCI_PM_CTRL, in radeonfb_whack_power_state()
2530 pci_write_config_word(rinfo->pdev, in radeonfb_whack_power_state()
2531 rinfo->pdev->pm_cap + PCI_PM_CTRL, in radeonfb_whack_power_state()
2535 rinfo->pdev->current_state = state; in radeonfb_whack_power_state()
2542 if (!rinfo->pdev->pm_cap) in radeon_set_suspend()
2546 * D3 would require a compete re-initialization of the chip, in radeon_set_suspend()
2551 pci_name(rinfo->pdev)); in radeon_set_suspend()
2563 if (rinfo->is_mobility) { in radeon_set_suspend()
2576 if (rinfo->family <= CHIP_FAMILY_RV280) { in radeon_set_suspend()
2587 pci_disable_device(rinfo->pdev); in radeon_set_suspend()
2588 pci_save_state(rinfo->pdev); in radeon_set_suspend()
2590 * repeatedly until it sticks. We do that -prior- to in radeon_set_suspend()
2594 pci_platform_power_transition(rinfo->pdev, PCI_D2); in radeon_set_suspend()
2597 pci_name(rinfo->pdev)); in radeon_set_suspend()
2599 if (rinfo->family <= CHIP_FAMILY_RV250) { in radeon_set_suspend()
2618 struct radeonfb_info *rinfo = info->par; in radeonfb_pci_suspend_late()
2620 if (mesg.event == pdev->dev.power.power_state.event) in radeonfb_pci_suspend_late()
2626 /* For suspend-to-disk, we cheat here. We don't suspend anything and in radeonfb_pci_suspend_late()
2641 if (!(info->flags & FBINFO_HWACCEL_DISABLED)) { in radeonfb_pci_suspend_late()
2652 rinfo->asleep = 1; in radeonfb_pci_suspend_late()
2653 rinfo->lock_blank = 1; in radeonfb_pci_suspend_late()
2654 del_timer_sync(&rinfo->lvds_timer); in radeonfb_pci_suspend_late()
2667 if (rinfo->pm_mode & radeon_pm_off) { in radeonfb_pci_suspend_late()
2669 * the chip goes off (basically the panel doesn't shut down properly in radeonfb_pci_suspend_late()
2678 if (rinfo->is_mobility && !(rinfo->pm_mode & radeon_pm_d2)) { in radeonfb_pci_suspend_late()
2692 if (rinfo->pm_mode & radeon_pm_d2) in radeonfb_pci_suspend_late()
2698 pdev->dev.power.power_state = mesg; in radeonfb_pci_suspend_late()
2720 return rinfo->save_regs[4] != INPLL(CLK_PIN_CNTL) || in radeon_check_power_loss()
2721 rinfo->save_regs[2] != INPLL(MCLK_CNTL) || in radeon_check_power_loss()
2722 rinfo->save_regs[3] != INPLL(SCLK_CNTL); in radeon_check_power_loss()
2729 struct radeonfb_info *rinfo = info->par; in radeonfb_pci_resume()
2732 if (pdev->dev.power.power_state.event == PM_EVENT_ON) in radeonfb_pci_resume()
2735 if (rinfo->no_schedule) { in radeonfb_pci_resume()
2742 pci_name(pdev), pdev->dev.power.power_state.event); in radeonfb_pci_resume()
2748 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) { in radeonfb_pci_resume()
2750 if ((rinfo->pm_mode & radeon_pm_off) && radeon_check_power_loss(rinfo)) { in radeonfb_pci_resume()
2751 if (rinfo->reinit_func != NULL) in radeonfb_pci_resume()
2752 rinfo->reinit_func(rinfo); in radeonfb_pci_resume()
2756 rc = -EIO; in radeonfb_pci_resume()
2764 else if (rinfo->pm_mode & radeon_pm_d2) in radeonfb_pci_resume()
2767 rinfo->asleep = 0; in radeonfb_pci_resume()
2772 radeon_write_mode (rinfo, &rinfo->state, 1); in radeonfb_pci_resume()
2773 if (!(info->flags & FBINFO_HWACCEL_DISABLED)) in radeonfb_pci_resume()
2776 fb_pan_display(info, &info->var); in radeonfb_pci_resume()
2777 fb_set_cmap(&info->cmap, info); in radeonfb_pci_resume()
2783 rinfo->lock_blank = 0; in radeonfb_pci_resume()
2796 if (rinfo->dynclk == 1) in radeonfb_pci_resume()
2798 else if (rinfo->dynclk == 0) in radeonfb_pci_resume()
2801 pdev->dev.power.power_state = PMSG_ON; in radeonfb_pci_resume()
2823 rinfo->no_schedule = 1; in radeonfb_early_resume()
2824 pci_restore_state(rinfo->pdev); in radeonfb_early_resume()
2825 radeonfb_pci_resume(rinfo->pdev); in radeonfb_early_resume()
2826 rinfo->no_schedule = 0; in radeonfb_early_resume()
2835 if (rinfo->family == CHIP_FAMILY_RS480) in radeonfb_pm_init()
2836 rinfo->dynclk = -1; in radeonfb_pm_init()
2838 rinfo->dynclk = dynclk; in radeonfb_pm_init()
2840 if (rinfo->dynclk == 1) { in radeonfb_pm_init()
2843 } else if (rinfo->dynclk == 0) { in radeonfb_pm_init()
2853 * BIOS does tho. Right now, all this PM stuff is pmac-only for that in radeonfb_pm_init()
2854 * reason. --BenH in radeonfb_pm_init()
2856 if (machine_is(powermac) && rinfo->of_node) { in radeonfb_pm_init()
2857 if (rinfo->is_mobility && rinfo->pdev->pm_cap && in radeonfb_pm_init()
2858 rinfo->family <= CHIP_FAMILY_RV250) in radeonfb_pm_init()
2859 rinfo->pm_mode |= radeon_pm_d2; in radeonfb_pm_init()
2865 if (of_node_name_eq(rinfo->of_node, "ATY,JasperParent") || in radeonfb_pm_init()
2866 of_node_name_eq(rinfo->of_node, "ATY,SnowyParent")) { in radeonfb_pm_init()
2867 rinfo->reinit_func = radeon_reinitialize_M10; in radeonfb_pm_init()
2868 rinfo->pm_mode |= radeon_pm_off; in radeonfb_pm_init()
2871 if (!strcmp(rinfo->of_node->name, "ATY,BlueStoneParent")) { in radeonfb_pm_init()
2872 rinfo->reinit_func = radeon_reinitialize_QW; in radeonfb_pm_init()
2873 rinfo->pm_mode |= radeon_pm_off; in radeonfb_pm_init()
2876 if (of_node_name_eq(rinfo->of_node, "ATY,ViaParent")) { in radeonfb_pm_init()
2877 rinfo->reinit_func = radeon_reinitialize_M9P; in radeonfb_pm_init()
2878 rinfo->pm_mode |= radeon_pm_off; in radeonfb_pm_init()
2886 if (rinfo->pm_mode != radeon_pm_none) { in radeonfb_pm_init()
2887 pmac_call_feature(PMAC_FTR_DEVICE_CAN_WAKE, rinfo->of_node, 0, 1); in radeonfb_pm_init()
2899 /* Power down TV DAC, that saves a significant amount of power, in radeonfb_pm_init()
2918 rinfo->pm_mode |= radeon_pm_d2; in radeonfb_pm_init()
2925 if (rinfo->pm_mode != radeon_pm_none) in radeonfb_pm_exit()