Lines Matching +full:0 +full:x31c
21 #define HC_CAPLENGTH 0x000
22 #define HC_LENGTH(p) (((p) >> 00) & 0x00ff) /* bits 7:0 */
23 #define HC_VERSION(p) (((p) >> 16) & 0xffff) /* bits 31:16 */
25 #define HC_HCSPARAMS 0x004
28 #define HCS_N_PORTS(p) (((p) >> 0) & 0xf) /* bits 3:0, ports on HC */
30 #define HC_HCCPARAMS 0x008
32 #define HCC_ISOC_THRES(p) (((p) >> 4) & 0x7) /* bits 6:4, uframes cached */
35 #define HC_USBCMD 0x020
38 #define CMD_RUN (1 << 0) /* start/stop HC */
40 #define HC_USBSTS 0x024
43 #define HC_FRINDEX 0x02c
45 #define HC_CONFIGFLAG 0x060
46 #define FLAG_CF (1 << 0) /* true: we'll support "high speed" */
48 #define HC_PORTSC1 0x064
57 #define PORT_CONNECT (1 << 0) /* device connected */
60 #define HC_ISO_PTD_DONEMAP_REG 0x130
61 #define HC_ISO_PTD_SKIPMAP_REG 0x134
62 #define HC_ISO_PTD_LASTPTD_REG 0x138
63 #define HC_INT_PTD_DONEMAP_REG 0x140
64 #define HC_INT_PTD_SKIPMAP_REG 0x144
65 #define HC_INT_PTD_LASTPTD_REG 0x148
66 #define HC_ATL_PTD_DONEMAP_REG 0x150
67 #define HC_ATL_PTD_SKIPMAP_REG 0x154
68 #define HC_ATL_PTD_LASTPTD_REG 0x158
71 #define HC_HW_MODE_CTRL 0x300
82 #define HW_GLOBAL_INTR_EN (1 << 0)
84 #define HC_CHIP_ID_REG 0x304
85 #define HC_SCRATCH_REG 0x308
87 #define HC_RESET_REG 0x30c
89 #define SW_RESET_RESET_ALL (1 << 0)
91 #define HC_BUFFER_STATUS_REG 0x334
94 #define ATL_BUF_FILL (1 << 0)
96 #define HC_MEMORY_REG 0x33c
99 #define HC_PORT1_CTRL 0x374
103 #define HW_OTG_CTRL_SET 0x374
104 #define HW_OTG_CTRL_CLR 0x376
115 #define HW_DP_PULLUP (1 << 0)
118 #define HC_INTERRUPT_REG 0x310
120 #define HC_INTERRUPT_ENABLE 0x314
128 #define HC_ISO_IRQ_MASK_OR_REG 0x318
129 #define HC_INT_IRQ_MASK_OR_REG 0x31c
130 #define HC_ATL_IRQ_MASK_OR_REG 0x320
131 #define HC_ISO_IRQ_MASK_AND_REG 0x324
132 #define HC_INT_IRQ_MASK_AND_REG 0x328
133 #define HC_ATL_IRQ_MASK_AND_REG 0x32c
140 #define DC_ADDRESS 0x0200
143 #define DC_MODE 0x020c
153 #define DC_INTCONF 0x0210
154 #define DC_CDBGMOD_ACK_NAK (0 << 6)
157 #define DC_DDBGMODIN_ACK_NAK (0 << 4)
160 #define DC_DDBGMODOUT_ACK_NYET_NAK (0 << 2)
164 #define DC_INTPOL (1 << 0)
166 #define DC_DEBUG 0x0212
167 #define DC_INTENABLE 0x0214
179 #define DC_IEBRST (1 << 0)
182 #define DC_EPINDEX 0x022c
185 #define DC_EPDIR (1 << 0)
187 #define DC_CTRLFUNC 0x0228
192 #define DC_STALL (1 << 0)
194 #define DC_DATAPORT 0x0220
195 #define DC_BUFLEN 0x021c
196 #define DC_DATACOUNT_MASK 0xffff
197 #define DC_BUFSTAT 0x021e
198 #define DC_EPMAXPKTSZ 0x0204
200 #define DC_EPTYPE 0x0208
204 #define DC_ENDPTYP_ISOC (1 << 0)
205 #define DC_ENDPTYP_BULK (2 << 0)
206 #define DC_ENDPTYP_INTERRUPT (3 << 0)
209 #define DC_DMACMD 0x0230
210 #define DC_DMATXCOUNT 0x0234
211 #define DC_DMACONF 0x0238
212 #define DC_DMAHW 0x023c
213 #define DC_DMAINTREASON 0x0250
214 #define DC_DMAINTEN 0x0254
215 #define DC_DMAEP 0x0258
216 #define DC_DMABURSTCOUNT 0x0264
219 #define DC_INTERRUPT 0x0218
220 #define DC_CHIPID 0x0270
221 #define DC_FRAMENUM 0x0274
222 #define DC_SCRATCH 0x0278
223 #define DC_UNLOCKDEV 0x027c
224 #define DC_INTPULSEWIDTH 0x0280
225 #define DC_TESTMODE 0x0284