1 /* SPDX-License-Identifier: GPL-2.0+ */
3  * Copyright (c) 2001-2002 by David Brownell
9 /* definitions used for the EHCI driver */
16  * To facilitate the strongest possible byte-order checking from "sparse"
46  * high-speed devices and full/low-speed devices lying behind a TT.
53 	u16			cs_mask;	/* C-mask and S-mask bytes */
66 /* ehci_hcd->lock guards shared data against other CPUs:
92  * ehci-timer.c) in parallel with this list.
188 			the change-suspend feature turned on */
194 	/* per-HC memory pools (could be per-bus, but ...) */
232 	unsigned		has_ppcd:1; /* support per-port change bits */
257 	/* platform-specific data -- must come last */
264 	return (struct ehci_hcd *) (hcd->hcd_priv);  in hcd_to_ehci()
266 static inline struct usb_hcd *ehci_to_hcd(struct ehci_hcd *ehci)  in ehci_to_hcd()  argument
268 	return container_of((void *) ehci, struct usb_hcd, hcd_priv);  in ehci_to_hcd()
271 /*-------------------------------------------------------------------------*/
273 #include <linux/usb/ehci_def.h>
275 /*-------------------------------------------------------------------------*/
277 #define	QTD_NEXT(ehci, dma)	cpu_to_hc32(ehci, (u32)dma)  argument
280  * EHCI Specification 0.95 Section 3.5
282  * See Fig 3-6 "Queue Element Transfer Descriptor Block Diagram".
288 	/* first part defined by EHCI spec */
289 	__hc32			hw_next;	/* see EHCI 3.5.1 */
290 	__hc32			hw_alt_next;    /* see EHCI 3.5.2 */
291 	__hc32			hw_token;       /* see EHCI 3.5.3 */
306 #define ACTIVE_BIT(ehci)	cpu_to_hc32(ehci, QTD_STS_ACTIVE)  argument
307 #define HALT_BIT(ehci)		cpu_to_hc32(ehci, QTD_STS_HALT)  argument
308 #define STATUS_BIT(ehci)	cpu_to_hc32(ehci, QTD_STS_STS)  argument
310 	__hc32			hw_buf[5];        /* see EHCI 3.5.4 */
313 	/* the rest is HCD-private */
320 /* mask NakCnt+T in qh->hw_alt_next */
321 #define QTD_MASK(ehci)	cpu_to_hc32(ehci, ~0x1f)  argument
325 /*-------------------------------------------------------------------------*/
327 /* type tag from {qh,itd,sitd,fstn}->hw_next */
328 #define Q_NEXT_TYPE(ehci, dma)	((dma) & cpu_to_hc32(ehci, 3 << 1))  argument
334  * can be used on one system with SoC EHCI controller using big-endian
335  * descriptors as well as a normal little-endian PCI EHCI controller.
344 #define QH_NEXT(ehci, dma) \  argument
345 		(cpu_to_hc32(ehci, (((u32) dma) & ~0x01f) | Q_TYPE_QH))
348 #define EHCI_LIST_END(ehci)	cpu_to_hc32(ehci, 1) /* "null pointer" to hw */  argument
367 /*-------------------------------------------------------------------------*/
370  * EHCI Specification 0.95 Section 3.6
372  * See Fig 3-7 "Queue Head Structure Layout".
377 /* first part defined by EHCI spec */
379 	__hc32			hw_next;	/* see EHCI 3.6.1 */
380 	__hc32			hw_info1;       /* see EHCI 3.6.2 */
388 	__hc32			hw_info2;        /* see EHCI 3.6.2 */
394 	__hc32			hw_current;	/* qtd list - see EHCI 3.6.4 */
406 	/* the rest is HCD-private */
438 	unsigned		clearing_tt:1;	/* Clear-TT-Buf in progress */
443 /*-------------------------------------------------------------------------*/
448 	u64			bufp;		/* itd->hw_bufp{,_hi}[pg] |= */
449 	__hc32			transaction;	/* itd->hw_transaction[i] |= */
456  * each packet is one logical usb transaction to the device (not TT),
457  * beginning at stream->next_uframe
467  * ehci_iso_stream - groups all (s)itds for this endpoint.
468  * acts like a qh would, if EHCI had them for ISO.
500 /*-------------------------------------------------------------------------*/
503  * EHCI Specification 0.95 Section 3.3
504  * Fig 3-4 "Isochronous Transaction Descriptor (iTD)"
509 	/* first part defined by EHCI spec */
510 	__hc32			hw_next;           /* see EHCI 3.3.1 */
511 	__hc32			hw_transaction[8]; /* see EHCI 3.3.2 */
515 #define EHCI_ISOC_XACTERR       (1<<28)        /* XactErr - transaction error */
519 #define ITD_ACTIVE(ehci)	cpu_to_hc32(ehci, EHCI_ISOC_ACTIVE)  argument
521 	__hc32			hw_bufp[7];	/* see EHCI 3.3.3 */
524 	/* the rest is HCD-private */
535 	unsigned		index[8];	/* in urb->iso_frame_desc */
538 /*-------------------------------------------------------------------------*/
541  * EHCI Specification 0.95 Section 3.4
542  * siTD, aka split-transaction isochronous Transfer Descriptor
544  * see Figure 3-5 "Split-transaction Isochronous Transaction Descriptor (siTD)
547 	/* first part defined by EHCI spec */
549 /* uses bit field macros above - see EHCI 0.95 Table 3-8 */
550 	__hc32			hw_fullspeed_ep;	/* EHCI table 3-9 */
551 	__hc32			hw_uframe;		/* EHCI table 3-10 */
552 	__hc32			hw_results;		/* EHCI table 3-11 */
564 #define SITD_ACTIVE(ehci)	cpu_to_hc32(ehci, SITD_STS_ACTIVE)  argument
566 	__hc32			hw_buf[2];		/* EHCI table 3-12 */
567 	__hc32			hw_backpointer;		/* EHCI table 3-13 */
570 	/* the rest is HCD-private */
581 /*-------------------------------------------------------------------------*/
584  * EHCI Specification 0.96 Section 3.7
596 	/* the rest is HCD-private */
601 /*-------------------------------------------------------------------------*/
604  * USB-2.0 Specification Sections 11.14 and 11.18
608  * port).  The bandwidth and budgeting information for the full/low-speed bus
609  * below each TT is self-contained and independent of the other TTs or the
610  * high-speed bus.
614  * the best-case estimate of the number of full-speed bytes allocated to an
618  * keep an up-to-date record, we recompute the budget when it is needed.
630 /*-------------------------------------------------------------------------*/
634 #define ehci_prepare_ports_for_controller_suspend(ehci, do_wakeup)	\  argument
635 		ehci_adjust_port_wakeup_flags(ehci, true, do_wakeup)
637 #define ehci_prepare_ports_for_controller_resume(ehci)			\  argument
638 		ehci_adjust_port_wakeup_flags(ehci, false, false)
640 /*-------------------------------------------------------------------------*/
645  * Some EHCI controllers have a Transaction Translator built into the
646  * root hub. This is a non-standard feature.  Each controller will need
651 #define	ehci_is_TDI(e)			(ehci_to_hcd(e)->has_tt)
655 ehci_port_speed(struct ehci_hcd *ehci, unsigned int portsc)  in ehci_port_speed()  argument
657 	if (ehci_is_TDI(ehci)) {  in ehci_port_speed()
658 		switch ((portsc >> (ehci->has_hostpc ? 25 : 26)) & 3) {  in ehci_port_speed()
675 #define	ehci_port_speed(ehci, portsc)	USB_PORT_STAT_HIGH_SPEED  argument
678 /*-------------------------------------------------------------------------*/
682  * port number in the queue head was 0..N-1 instead of 1..N.
684 #define	ehci_has_fsl_portno_bug(e)		((e)->has_fsl_port_bug)
689 #define PORTSC_FSL_PFSC	24	/* Port Force Full-Speed Connect */
692 /* Some Freescale processors have an erratum (USB A-005275) in which
695 #define ehci_has_fsl_hs_errata(e)	((e)->has_fsl_hs_errata)
701  * Some Freescale/NXP processors have an erratum (USB A-005697)
705 #define ehci_has_fsl_susp_errata(e)	((e)->has_fsl_susp_errata)
708  * While most USB host controllers implement their registers in
709  * little-endian format, a minority (celleb companion chip) implement
718  * as fields of a 32-bit register.
722 #define ehci_big_endian_mmio(e)		((e)->big_endian_mmio)
723 #define ehci_big_endian_capbase(e)	((e)->big_endian_capbase)
730  * Big-endian read/write functions are arch-specific.
738 static inline unsigned int ehci_readl(const struct ehci_hcd *ehci,  in ehci_readl()  argument
742 	return ehci_big_endian_mmio(ehci) ?  in ehci_readl()
762 static inline void ehci_writel(const struct ehci_hcd *ehci,  in ehci_writel()  argument
766 	ehci_big_endian_mmio(ehci) ?  in ehci_writel()
770 	if (ehci->imx28_write_fix)  in ehci_writel()
778  * On certain ppc-44x SoC there is a HW issue, that could only worked around with
783 static inline void set_ohci_hcfs(struct ehci_hcd *ehci, int operational)  in set_ohci_hcfs()  argument
787 	hc_control = (readl_be(ehci->ohci_hcctrl_reg) & ~OHCI_CTRL_HCFS);  in set_ohci_hcfs()
793 	writel_be(hc_control, ehci->ohci_hcctrl_reg);  in set_ohci_hcfs()
794 	(void) readl_be(ehci->ohci_hcctrl_reg);  in set_ohci_hcfs()
797 static inline void set_ohci_hcfs(struct ehci_hcd *ehci, int operational)  in set_ohci_hcfs()  argument
801 /*-------------------------------------------------------------------------*/
804  * The AMCC 440EPx not only implements its EHCI registers in big-endian
807  * EHCI controllers accessed through PCI work normally (little-endian
808  * everywhere), so we won't bother supporting a BE-only mode for now.
811 #define ehci_big_endian_desc(e)		((e)->big_endian_desc)
813 /* cpu to ehci */
814 static inline __hc32 cpu_to_hc32(const struct ehci_hcd *ehci, const u32 x)  in cpu_to_hc32()  argument
816 	return ehci_big_endian_desc(ehci)  in cpu_to_hc32()
821 /* ehci to cpu */
822 static inline u32 hc32_to_cpu(const struct ehci_hcd *ehci, const __hc32 x)  in hc32_to_cpu()  argument
824 	return ehci_big_endian_desc(ehci)  in hc32_to_cpu()
829 static inline u32 hc32_to_cpup(const struct ehci_hcd *ehci, const __hc32 *x)  in hc32_to_cpup()  argument
831 	return ehci_big_endian_desc(ehci)  in hc32_to_cpup()
838 /* cpu to ehci */
839 static inline __hc32 cpu_to_hc32(const struct ehci_hcd *ehci, const u32 x)  in cpu_to_hc32()  argument
844 /* ehci to cpu */
845 static inline u32 hc32_to_cpu(const struct ehci_hcd *ehci, const __hc32 x)  in hc32_to_cpu()  argument
850 static inline u32 hc32_to_cpup(const struct ehci_hcd *ehci, const __hc32 *x)  in hc32_to_cpup()  argument
857 /*-------------------------------------------------------------------------*/
859 #define ehci_dbg(ehci, fmt, args...) \  argument
860 	dev_dbg(ehci_to_hcd(ehci)->self.controller, fmt, ## args)
861 #define ehci_err(ehci, fmt, args...) \  argument
862 	dev_err(ehci_to_hcd(ehci)->self.controller, fmt, ## args)
863 #define ehci_info(ehci, fmt, args...) \  argument
864 	dev_info(ehci_to_hcd(ehci)->self.controller, fmt, ## args)
865 #define ehci_warn(ehci, fmt, args...) \  argument
866 	dev_warn(ehci_to_hcd(ehci)->self.controller, fmt, ## args)
868 /*-------------------------------------------------------------------------*/
870 /* Declarations of things exported for use by ehci platform drivers */
882 extern int	ehci_handshake(struct ehci_hcd *ehci, void __iomem *ptr,
884 extern int	ehci_reset(struct ehci_hcd *ehci);
888 extern void	ehci_adjust_port_wakeup_flags(struct ehci_hcd *ehci,