Lines Matching full:ehci
3 * EHCI-compliant USB host controller driver for NVIDIA Tegra SoCs
29 #include "ehci.h"
35 #define DRIVER_DESC "Tegra EHCI driver"
36 #define DRV_NAME "tegra-ehci"
104 struct ehci_hcd *ehci, in tegra_ehci_internal_port_reset() argument
114 spin_lock_irqsave(&ehci->lock, flags); in tegra_ehci_internal_port_reset()
115 saved_usbintr = ehci_readl(ehci, &ehci->regs->intr_enable); in tegra_ehci_internal_port_reset()
117 ehci_writel(ehci, 0, &ehci->regs->intr_enable); in tegra_ehci_internal_port_reset()
118 spin_unlock_irqrestore(&ehci->lock, flags); in tegra_ehci_internal_port_reset()
125 temp = ehci_readl(ehci, portsc_reg); in tegra_ehci_internal_port_reset()
127 ehci_writel(ehci, temp, portsc_reg); in tegra_ehci_internal_port_reset()
130 ehci_writel(ehci, temp, portsc_reg); in tegra_ehci_internal_port_reset()
141 temp = ehci_readl(ehci, portsc_reg); in tegra_ehci_internal_port_reset()
154 ehci_writel(ehci, PORT_CSC, portsc_reg); in tegra_ehci_internal_port_reset()
160 temp = ehci_readl(ehci, &ehci->regs->status); in tegra_ehci_internal_port_reset()
161 ehci_writel(ehci, temp, &ehci->regs->status); in tegra_ehci_internal_port_reset()
164 ehci_writel(ehci, saved_usbintr, &ehci->regs->intr_enable); in tegra_ehci_internal_port_reset()
177 struct ehci_hcd *ehci = hcd_to_ehci(hcd); in tegra_ehci_hub_control() local
178 struct tegra_ehci_hcd *tegra = (struct tegra_ehci_hcd *)ehci->priv; in tegra_ehci_hub_control()
184 status_reg = &ehci->regs->port_status[(wIndex & 0xff) - 1]; in tegra_ehci_hub_control()
186 spin_lock_irqsave(&ehci->lock, flags); in tegra_ehci_hub_control()
189 temp = ehci_readl(ehci, status_reg); in tegra_ehci_hub_control()
198 temp = ehci_readl(ehci, status_reg); in tegra_ehci_hub_control()
206 ehci_writel(ehci, temp | PORT_SUSPEND, status_reg); in tegra_ehci_hub_control()
212 if (ehci_handshake(ehci, status_reg, PORT_SUSPEND, in tegra_ehci_hub_control()
216 set_bit((wIndex & 0xff) - 1, &ehci->suspended_ports); in tegra_ehci_hub_control()
223 spin_unlock_irqrestore(&ehci->lock, flags); in tegra_ehci_hub_control()
224 return tegra_ehci_internal_port_reset(ehci, status_reg); in tegra_ehci_hub_control()
230 * is different from EHCI where the host controller driver is required in tegra_ehci_hub_control()
236 temp = ehci_readl(ehci, status_reg); in tegra_ehci_hub_control()
248 ehci->reset_done[wIndex-1] = jiffies + msecs_to_jiffies(25); in tegra_ehci_hub_control()
252 ehci_writel(ehci, temp | PORT_RESUME, status_reg); in tegra_ehci_hub_control()
253 set_bit(wIndex-1, &ehci->resuming_ports); in tegra_ehci_hub_control()
255 spin_unlock_irqrestore(&ehci->lock, flags); in tegra_ehci_hub_control()
257 spin_lock_irqsave(&ehci->lock, flags); in tegra_ehci_hub_control()
260 if (ehci_handshake(ehci, status_reg, PORT_RESUME, 0, 2000)) in tegra_ehci_hub_control()
262 if (ehci_handshake(ehci, status_reg, PORT_SUSPEND, 0, 2000)) in tegra_ehci_hub_control()
265 ehci->reset_done[wIndex-1] = 0; in tegra_ehci_hub_control()
266 clear_bit(wIndex-1, &ehci->resuming_ports); in tegra_ehci_hub_control()
272 spin_unlock_irqrestore(&ehci->lock, flags); in tegra_ehci_hub_control()
278 spin_unlock_irqrestore(&ehci->lock, flags); in tegra_ehci_hub_control()
376 { .compatible = "nvidia,tegra30-ehci", .data = &tegra30_soc_config },
377 { .compatible = "nvidia,tegra20-ehci", .data = &tegra20_soc_config },
387 struct ehci_hcd *ehci; in tegra_ehci_probe() local
415 ehci = hcd_to_ehci(hcd); in tegra_ehci_probe()
416 tegra = (struct tegra_ehci_hcd *)ehci->priv; in tegra_ehci_probe()
422 dev_err(&pdev->dev, "Can't get ehci clock\n"); in tegra_ehci_probe()
429 dev_err(&pdev->dev, "Can't get ehci reset\n"); in tegra_ehci_probe()
464 ehci->caps = hcd->regs + 0x100; in tegra_ehci_probe()
465 ehci->has_hostpc = soc_config->has_hostpc; in tegra_ehci_probe()
544 struct ehci_hcd *ehci = hcd_to_ehci(hcd); in tegra_ehci_reset() local
558 txfifothresh = ehci->has_hostpc ? 0x10 : 10; in tegra_ehci_reset()
559 ehci_writel(ehci, txfifothresh << 16, &ehci->regs->txfill_tuning); in tegra_ehci_reset()