Lines Matching full:only
83 #define S3C2410_UDC_INT_EP4 (1 << 4) /* R/W (clear only) */
84 #define S3C2410_UDC_INT_EP3 (1 << 3) /* R/W (clear only) */
85 #define S3C2410_UDC_INT_EP2 (1 << 2) /* R/W (clear only) */
86 #define S3C2410_UDC_INT_EP1 (1 << 1) /* R/W (clear only) */
87 #define S3C2410_UDC_INT_EP0 (1 << 0) /* R/W (clear only) */
89 #define S3C2410_UDC_USBINT_RESET (1 << 2) /* R/W (clear only) */
90 #define S3C2410_UDC_USBINT_RESUME (1 << 1) /* R/W (clear only) */
91 #define S3C2410_UDC_USBINT_SUSPEND (1 << 0) /* R/W (clear only) */
109 #define S3C2410_UDC_ICSR1_SENTSTL (1 << 5) /* R/W (clear only) */
111 #define S3C2410_UDC_ICSR1_FFLUSH (1 << 3) /* W (set only) */
112 #define S3C2410_UDC_ICSR1_UNDRUN (1 << 2) /* R/W (clear only) */
113 #define S3C2410_UDC_ICSR1_PKTRDY (1 << 0) /* R/W (set only) */
121 #define S3C2410_UDC_OCSR1_SENTSTL (1 << 6) /* R/W (clear only) */
125 #define S3C2410_UDC_OCSR1_OVRRUN (1 << 2) /* R/W (clear only) */
126 #define S3C2410_UDC_OCSR1_PKTRDY (1 << 0) /* R/W (clear only) */