usb/dwc2/hw.h

1 /* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
3  * hw.h - DesignWare HS OTG Controller hardware definitions
5  * Copyright 2004-2013 Synopsys, Inc.
16  * 3. The names of the above-listed copyright holders may not be used
49 #define GOTGCTL_ASESVLD			BIT(18)
68 #define GOTGINT_A_DEV_TOUT_CHG		BIT(18)
100 #define GUSBCFG_ULPI_INT_PROT_DIS	BIT(25)
107 #define GUSBCFG_ULPI_AUTO_RES		BIT(18)
149 #define GINTSTS_HCHINT			BIT(25)
157 #define GINTSTS_IEPINT			BIT(18)
179 #define GRXSTS_FN_MASK			(0x7f << 25)
180 #define GRXSTS_FN_SHIFT			25
224 #define GI2CCTL_I2CSUSPCTL		BIT(25)
255 #define GHWCFG2_PERIO_EP_SUPPORTED		BIT(18)
311 #define GHWCFG4_DED_FIFO_EN			BIT(25)
312 #define GHWCFG4_DED_FIFO_SHIFT		25
340 #define GLPMCFG_LPM_RETRYCNT_STS_MASK	(0x7 << 25)
341 #define GLPMCFG_LPM_RETRYCNT_STS_SHIFT	25
371 #define GPWRDN_STS_CHGINT_MSK		BIT(18)
401 #define ADPCTL_ADP_SNS_INT_MSK		BIT(25)
408 #define ADPCTL_ENASNS			BIT(18)
435 #define DPTXFSIZN(_a)			HSOTG_REG(0x104 + (((_a) - 1) * 4))
449 #define DCFG_EPMISCNT_MASK		(0x1f << 18)
450 #define DCFG_EPMISCNT_SHIFT		18
452 #define DCFG_EPMISCNT(_x)		((_x) << 18)
543  * bits[29..28] - reserved (no SetD0PID, SetD1PID)
544  * bits[25..22] - should always be zero, this isn't a periodic endpoint
545  * bits[10..0]  - MPS setting different for EP0
568 #define DXEPCTL_EPTYPE_MASK		(0x3 << 18)
569 #define DXEPCTL_EPTYPE_CONTROL		(0x0 << 18)
570 #define DXEPCTL_EPTYPE_ISO		(0x1 << 18)
571 #define DXEPCTL_EPTYPE_BULK		(0x2 << 18)
572 #define DXEPCTL_EPTYPE_INTERRUPT	(0x3 << 18)
727 #define TXSTS_QTOP_TOKEN_MASK		(0x3 << 25)
728 #define TXSTS_QTOP_TOKEN_SHIFT		25
768 #define HCCHAR_EPTYPE_MASK		(0x3 << 18)
769 #define HCCHAR_EPTYPE_SHIFT		18
834  * struct dwc2_dma_desc - DMA descriptor structure,
855 #define HOST_DMA_IOC			BIT(25)
881 #define DEV_DMA_IOC			BIT(25)