tty/serial/atmel_serial.h

1 /* SPDX-License-Identifier: GPL-2.0+ */
16 #define	ATMEL_US_RSTRX		BIT(2)	/* Reset Receiver */
17 #define	ATMEL_US_RSTTX		BIT(3)	/* Reset Transmitter */
18 #define	ATMEL_US_RXEN		BIT(4)	/* Receiver Enable */
19 #define	ATMEL_US_RXDIS		BIT(5)	/* Receiver Disable */
20 #define	ATMEL_US_TXEN		BIT(6)	/* Transmitter Enable */
21 #define	ATMEL_US_TXDIS		BIT(7)	/* Transmitter Disable */
22 #define	ATMEL_US_RSTSTA		BIT(8)	/* Reset Status Bits */
23 #define	ATMEL_US_STTBRK		BIT(9)	/* Start Break */
24 #define	ATMEL_US_STPBRK		BIT(10)	/* Stop Break */
25 #define	ATMEL_US_STTTO		BIT(11)	/* Start Time-out */
26 #define	ATMEL_US_SENDA		BIT(12)	/* Send Address */
27 #define	ATMEL_US_RSTIT		BIT(13)	/* Reset Iterations */
28 #define	ATMEL_US_RSTNACK	BIT(14)	/* Reset Non Acknowledge */
29 #define	ATMEL_US_RETTO		BIT(15)	/* Rearm Time-out */
30 #define	ATMEL_US_DTREN		BIT(16)	/* Data Terminal Ready Enable */
31 #define	ATMEL_US_DTRDIS		BIT(17)	/* Data Terminal Ready Disable */
32 #define	ATMEL_US_RTSEN		BIT(18)	/* Request To Send Enable */
33 #define	ATMEL_US_RTSDIS		BIT(19)	/* Request To Send Disable */
34 #define	ATMEL_US_TXFCLR		BIT(24)	/* Transmit FIFO Clear */
35 #define	ATMEL_US_RXFCLR		BIT(25)	/* Receive FIFO Clear */
36 #define	ATMEL_US_TXFLCLR	BIT(26)	/* Transmit FIFO Lock Clear */
37 #define	ATMEL_US_FIFOEN		BIT(30)	/* FIFO enable */
38 #define	ATMEL_US_FIFODIS	BIT(31)	/* FIFO disable */
58 #define	ATMEL_US_SYNC		BIT(8)		/* Synchronous Mode Select */
75 #define	ATMEL_US_MSBF		BIT(16)	/* Bit Order */
76 #define	ATMEL_US_MODE9		BIT(17)	/* 9-bit Character Length */
77 #define	ATMEL_US_CLKO		BIT(18)	/* Clock Output Select */
78 #define	ATMEL_US_OVER		BIT(19)	/* Oversampling Mode */
79 #define	ATMEL_US_INACK		BIT(20)	/* Inhibit Non Acknowledge */
80 #define	ATMEL_US_DSNACK		BIT(21)	/* Disable Successive NACK */
83 #define	ATMEL_US_FILTER		BIT(28)	/* Infrared Receive Line Filter */
86 #define	ATMEL_US_RXRDY		BIT(0)	/* Receiver Ready */
87 #define	ATMEL_US_TXRDY		BIT(1)	/* Transmitter Ready */
88 #define	ATMEL_US_RXBRK		BIT(2)	/* Break Received / End of Break */
89 #define	ATMEL_US_ENDRX		BIT(3)	/* End of Receiver Transfer */
90 #define	ATMEL_US_ENDTX		BIT(4)	/* End of Transmitter Transfer */
91 #define	ATMEL_US_OVRE		BIT(5)	/* Overrun Error */
92 #define	ATMEL_US_FRAME		BIT(6)	/* Framing Error */
93 #define	ATMEL_US_PARE		BIT(7)	/* Parity Error */
94 #define	ATMEL_US_TIMEOUT	BIT(8)	/* Receiver Time-out */
95 #define	ATMEL_US_TXEMPTY	BIT(9)	/* Transmitter Empty */
96 #define	ATMEL_US_ITERATION	BIT(10)	/* Max number of Repetitions Reached */
97 #define	ATMEL_US_TXBUFE		BIT(11)	/* Transmission Buffer Empty */
98 #define	ATMEL_US_RXBUFF		BIT(12)	/* Reception Buffer Full */
99 #define	ATMEL_US_NACK		BIT(13)	/* Non Acknowledge */
100 #define	ATMEL_US_RIIC		BIT(16)	/* Ring Indicator Input Change */
101 #define	ATMEL_US_DSRIC		BIT(17)	/* Data Set Ready Input Change */
102 #define	ATMEL_US_DCDIC		BIT(18)	/* Data Carrier Detect Input Change */
103 #define	ATMEL_US_CTSIC		BIT(19)	/* Clear to Send Input Change */
104 #define	ATMEL_US_RI		BIT(20)	/* RI */
105 #define	ATMEL_US_DSR		BIT(21)	/* DSR */
106 #define	ATMEL_US_DCD		BIT(22)	/* DCD */
107 #define	ATMEL_US_CTS		BIT(23)	/* CTS */
114 #define	ATMEL_US_SYNH		BIT(15)	/* Transmit/Receive Sync */
121 #define ATMEL_US_RTOR		0x24	/* Receiver Time-out Register for USART */
122 #define ATMEL_UA_RTOR		0x28	/* Receiver Time-out Register for UART */
123 #define	ATMEL_US_TO		GENMASK(15, 0)	/* Time-out Value */
139 #define	ATMEL_US_FRTSC		BIT(7)	/* FIFO RTS pin Control */
152 #define	ATMEL_US_TXFEF		BIT(0)	/* Transmit FIFO Empty Flag */
153 #define	ATMEL_US_TXFFF		BIT(1)	/* Transmit FIFO Full Flag */
154 #define	ATMEL_US_TXFTHF		BIT(2)	/* Transmit FIFO Threshold Flag */
155 #define	ATMEL_US_RXFEF		BIT(3)	/* Receive FIFO Empty Flag */
156 #define	ATMEL_US_RXFFF		BIT(4)	/* Receive FIFO Full Flag */
157 #define	ATMEL_US_RXFTHF		BIT(5)	/* Receive FIFO Threshold Flag */
158 #define	ATMEL_US_TXFPTEF	BIT(6)	/* Transmit FIFO Pointer Error Flag */
159 #define	ATMEL_US_RXFPTEF	BIT(7)	/* Receive FIFO Pointer Error Flag */
160 #define	ATMEL_US_TXFLOCK	BIT(8)	/* Transmit FIFO Lock (FESR only) */
161 #define	ATMEL_US_RXFTHF2	BIT(9)	/* Receive FIFO Threshold Flag 2 */