Lines Matching +full:ri +full:- +full:override
1 // SPDX-License-Identifier: GPL-2.0+
73 struct dw8250_data *d = to_dw8250_data(p->private_data); in dw8250_modify_msr()
75 /* Override any modem control signals if needed */ in dw8250_modify_msr()
77 value |= d->msr_mask_on; in dw8250_modify_msr()
78 value &= ~d->msr_mask_off; in dw8250_modify_msr()
89 (void)p->serial_in(p, UART_RX); in dw8250_force_idle()
94 void __iomem *offset = p->membase + (UART_LCR << p->regshift); in dw8250_check_lcr()
98 while (tries--) { in dw8250_check_lcr()
99 unsigned int lcr = p->serial_in(p, UART_LCR); in dw8250_check_lcr()
107 if (p->type == PORT_OCTEON) in dw8250_check_lcr()
111 if (p->iotype == UPIO_MEM32) in dw8250_check_lcr()
113 else if (p->iotype == UPIO_MEM32BE) in dw8250_check_lcr()
119 * FIXME: this deadlocks if port->lock is already held in dw8250_check_lcr()
120 * dev_err(p->dev, "Couldn't set LCR to %d\n", value); in dw8250_check_lcr()
128 unsigned int delay_threshold = tries - 1000; in dw8250_tx_wait_empty()
131 while (tries--) { in dw8250_tx_wait_empty()
132 lsr = readb (p->membase + (UART_LSR << p->regshift)); in dw8250_tx_wait_empty()
138 * the buffer has still not emptied, allow more time for low- in dw8250_tx_wait_empty()
147 struct dw8250_data *d = to_dw8250_data(p->private_data); in dw8250_serial_out38x()
153 writeb(value, p->membase + (offset << p->regshift)); in dw8250_serial_out38x()
155 if (offset == UART_LCR && !d->uart_16550_compatible) in dw8250_serial_out38x()
162 struct dw8250_data *d = to_dw8250_data(p->private_data); in dw8250_serial_out()
164 writeb(value, p->membase + (offset << p->regshift)); in dw8250_serial_out()
166 if (offset == UART_LCR && !d->uart_16550_compatible) in dw8250_serial_out()
172 unsigned int value = readb(p->membase + (offset << p->regshift)); in dw8250_serial_in()
182 value = (u8)__raw_readq(p->membase + (offset << p->regshift)); in dw8250_serial_inq()
189 struct dw8250_data *d = to_dw8250_data(p->private_data); in dw8250_serial_outq()
192 __raw_writeq(value, p->membase + (offset << p->regshift)); in dw8250_serial_outq()
194 __raw_readq(p->membase + (UART_LCR << p->regshift)); in dw8250_serial_outq()
196 if (offset == UART_LCR && !d->uart_16550_compatible) in dw8250_serial_outq()
203 struct dw8250_data *d = to_dw8250_data(p->private_data); in dw8250_serial_out32()
205 writel(value, p->membase + (offset << p->regshift)); in dw8250_serial_out32()
207 if (offset == UART_LCR && !d->uart_16550_compatible) in dw8250_serial_out32()
213 unsigned int value = readl(p->membase + (offset << p->regshift)); in dw8250_serial_in32()
220 struct dw8250_data *d = to_dw8250_data(p->private_data); in dw8250_serial_out32be()
222 iowrite32be(value, p->membase + (offset << p->regshift)); in dw8250_serial_out32be()
224 if (offset == UART_LCR && !d->uart_16550_compatible) in dw8250_serial_out32be()
230 unsigned int value = ioread32be(p->membase + (offset << p->regshift)); in dw8250_serial_in32be()
239 struct dw8250_data *d = to_dw8250_data(p->private_data); in dw8250_handle_irq()
240 unsigned int iir = p->serial_in(p, UART_IIR); in dw8250_handle_irq()
245 * There are ways to get Designware-based UARTs into a state where in dw8250_handle_irq()
252 * so we limit the workaround only to non-DMA mode. in dw8250_handle_irq()
254 if (!up->dma && ((iir & 0x3f) == UART_IIR_RX_TIMEOUT)) { in dw8250_handle_irq()
255 spin_lock_irqsave(&p->lock, flags); in dw8250_handle_irq()
256 status = p->serial_in(p, UART_LSR); in dw8250_handle_irq()
259 (void) p->serial_in(p, UART_RX); in dw8250_handle_irq()
261 spin_unlock_irqrestore(&p->lock, flags); in dw8250_handle_irq()
269 (void)p->serial_in(p, d->usr_reg); in dw8250_handle_irq()
283 rate = clk_get_rate(d->clk); in dw8250_clk_work_cb()
287 up = serial8250_get_port(d->data.line); in dw8250_clk_work_cb()
289 serial8250_update_uartclk(&up->port, rate); in dw8250_clk_work_cb()
302 * the clk and tty-port mutexes lock. It happens if clock rate change in dw8250_clk_notifier_cb()
304 * tty-port mutex lock and clk_set_rate() function invocation and in dw8250_clk_notifier_cb()
305 * vise-versa. Anyway if we didn't have the reference clock alteration in dw8250_clk_notifier_cb()
310 queue_work(system_unbound_wq, &d->clk_work); in dw8250_clk_notifier_cb()
321 pm_runtime_get_sync(port->dev); in dw8250_do_pm()
326 pm_runtime_put_sync_suspend(port->dev); in dw8250_do_pm()
333 struct dw8250_data *d = to_dw8250_data(p->private_data); in dw8250_set_termios()
337 clk_disable_unprepare(d->clk); in dw8250_set_termios()
338 rate = clk_round_rate(d->clk, newrate); in dw8250_set_termios()
346 swap(p->uartclk, rate); in dw8250_set_termios()
347 ret = clk_set_rate(d->clk, newrate); in dw8250_set_termios()
349 swap(p->uartclk, rate); in dw8250_set_termios()
351 clk_prepare_enable(d->clk); in dw8250_set_termios()
353 p->status &= ~UPSTAT_AUTOCTS; in dw8250_set_termios()
354 if (termios->c_cflag & CRTSCTS) in dw8250_set_termios()
355 p->status |= UPSTAT_AUTOCTS; in dw8250_set_termios()
363 unsigned int mcr = p->serial_in(p, UART_MCR); in dw8250_set_ldisc()
365 if (up->capabilities & UART_CAP_IRDA) { in dw8250_set_ldisc()
366 if (termios->c_line == N_IRDA) in dw8250_set_ldisc()
371 p->serial_out(p, UART_MCR, mcr); in dw8250_set_ldisc()
391 return param == chan->device->dev; in dw8250_idma_filter()
396 if (p->dev->of_node) { in dw8250_quirks()
397 struct device_node *np = p->dev->of_node; in dw8250_quirks()
403 p->line = id; in dw8250_quirks()
405 if (of_device_is_compatible(np, "cavium,octeon-3860-uart")) { in dw8250_quirks()
406 p->serial_in = dw8250_serial_inq; in dw8250_quirks()
407 p->serial_out = dw8250_serial_outq; in dw8250_quirks()
408 p->flags = UPF_SKIP_TEST | UPF_SHARE_IRQ | UPF_FIXED_TYPE; in dw8250_quirks()
409 p->type = PORT_OCTEON; in dw8250_quirks()
410 data->usr_reg = 0x27; in dw8250_quirks()
411 data->skip_autocfg = true; in dw8250_quirks()
414 if (of_device_is_big_endian(p->dev->of_node)) { in dw8250_quirks()
415 p->iotype = UPIO_MEM32BE; in dw8250_quirks()
416 p->serial_in = dw8250_serial_in32be; in dw8250_quirks()
417 p->serial_out = dw8250_serial_out32be; in dw8250_quirks()
419 if (of_device_is_compatible(np, "marvell,armada-38x-uart")) in dw8250_quirks()
420 p->serial_out = dw8250_serial_out38x; in dw8250_quirks()
422 } else if (acpi_dev_present("APMC0D08", NULL, -1)) { in dw8250_quirks()
423 p->iotype = UPIO_MEM32; in dw8250_quirks()
424 p->regshift = 2; in dw8250_quirks()
425 p->serial_in = dw8250_serial_in32; in dw8250_quirks()
426 data->uart_16550_compatible = true; in dw8250_quirks()
429 /* Platforms with iDMA 64-bit */ in dw8250_quirks()
430 if (platform_get_resource_byname(to_platform_device(p->dev), in dw8250_quirks()
432 data->data.dma.rx_param = p->dev->parent; in dw8250_quirks()
433 data->data.dma.tx_param = p->dev->parent; in dw8250_quirks()
434 data->data.dma.fn = dw8250_idma_filter; in dw8250_quirks()
442 struct uart_port *p = &up->port; in dw8250_probe()
443 struct device *dev = &pdev->dev; in dw8250_probe()
451 return -EINVAL; in dw8250_probe()
458 spin_lock_init(&p->lock); in dw8250_probe()
459 p->mapbase = regs->start; in dw8250_probe()
460 p->irq = irq; in dw8250_probe()
461 p->handle_irq = dw8250_handle_irq; in dw8250_probe()
462 p->pm = dw8250_do_pm; in dw8250_probe()
463 p->type = PORT_8250; in dw8250_probe()
464 p->flags = UPF_SHARE_IRQ | UPF_FIXED_PORT; in dw8250_probe()
465 p->dev = dev; in dw8250_probe()
466 p->iotype = UPIO_MEM; in dw8250_probe()
467 p->serial_in = dw8250_serial_in; in dw8250_probe()
468 p->serial_out = dw8250_serial_out; in dw8250_probe()
469 p->set_ldisc = dw8250_set_ldisc; in dw8250_probe()
470 p->set_termios = dw8250_set_termios; in dw8250_probe()
472 p->membase = devm_ioremap(dev, regs->start, resource_size(regs)); in dw8250_probe()
473 if (!p->membase) in dw8250_probe()
474 return -ENOMEM; in dw8250_probe()
478 return -ENOMEM; in dw8250_probe()
480 data->data.dma.fn = dw8250_fallback_dma_filter; in dw8250_probe()
481 data->usr_reg = DW_UART_USR; in dw8250_probe()
482 p->private_data = &data->data; in dw8250_probe()
484 data->uart_16550_compatible = device_property_read_bool(dev, in dw8250_probe()
485 "snps,uart-16550-compatible"); in dw8250_probe()
487 err = device_property_read_u32(dev, "reg-shift", &val); in dw8250_probe()
489 p->regshift = val; in dw8250_probe()
491 err = device_property_read_u32(dev, "reg-io-width", &val); in dw8250_probe()
493 p->iotype = UPIO_MEM32; in dw8250_probe()
494 p->serial_in = dw8250_serial_in32; in dw8250_probe()
495 p->serial_out = dw8250_serial_out32; in dw8250_probe()
498 if (device_property_read_bool(dev, "dcd-override")) { in dw8250_probe()
500 data->msr_mask_on |= UART_MSR_DCD; in dw8250_probe()
501 data->msr_mask_off |= UART_MSR_DDCD; in dw8250_probe()
504 if (device_property_read_bool(dev, "dsr-override")) { in dw8250_probe()
506 data->msr_mask_on |= UART_MSR_DSR; in dw8250_probe()
507 data->msr_mask_off |= UART_MSR_DDSR; in dw8250_probe()
510 if (device_property_read_bool(dev, "cts-override")) { in dw8250_probe()
512 data->msr_mask_on |= UART_MSR_CTS; in dw8250_probe()
513 data->msr_mask_off |= UART_MSR_DCTS; in dw8250_probe()
516 if (device_property_read_bool(dev, "ri-override")) { in dw8250_probe()
518 data->msr_mask_off |= UART_MSR_RI; in dw8250_probe()
519 data->msr_mask_off |= UART_MSR_TERI; in dw8250_probe()
523 device_property_read_u32(dev, "clock-frequency", &p->uartclk); in dw8250_probe()
526 data->clk = devm_clk_get_optional(dev, "baudclk"); in dw8250_probe()
527 if (data->clk == NULL) in dw8250_probe()
528 data->clk = devm_clk_get_optional(dev, NULL); in dw8250_probe()
529 if (IS_ERR(data->clk)) in dw8250_probe()
530 return PTR_ERR(data->clk); in dw8250_probe()
532 INIT_WORK(&data->clk_work, dw8250_clk_work_cb); in dw8250_probe()
533 data->clk_notifier.notifier_call = dw8250_clk_notifier_cb; in dw8250_probe()
535 err = clk_prepare_enable(data->clk); in dw8250_probe()
539 if (data->clk) in dw8250_probe()
540 p->uartclk = clk_get_rate(data->clk); in dw8250_probe()
543 if (!p->uartclk) { in dw8250_probe()
545 err = -EINVAL; in dw8250_probe()
549 data->pclk = devm_clk_get_optional(dev, "apb_pclk"); in dw8250_probe()
550 if (IS_ERR(data->pclk)) { in dw8250_probe()
551 err = PTR_ERR(data->pclk); in dw8250_probe()
555 err = clk_prepare_enable(data->pclk); in dw8250_probe()
561 data->rst = devm_reset_control_get_optional_exclusive(dev, NULL); in dw8250_probe()
562 if (IS_ERR(data->rst)) { in dw8250_probe()
563 err = PTR_ERR(data->rst); in dw8250_probe()
566 reset_control_deassert(data->rst); in dw8250_probe()
571 if (data->uart_16550_compatible) in dw8250_probe()
572 p->handle_irq = NULL; in dw8250_probe()
574 if (!data->skip_autocfg) in dw8250_probe()
578 if (p->fifosize) { in dw8250_probe()
579 data->data.dma.rxconf.src_maxburst = p->fifosize / 4; in dw8250_probe()
580 data->data.dma.txconf.dst_maxburst = p->fifosize / 4; in dw8250_probe()
581 up->dma = &data->data.dma; in dw8250_probe()
584 data->data.line = serial8250_register_8250_port(up); in dw8250_probe()
585 if (data->data.line < 0) { in dw8250_probe()
586 err = data->data.line; in dw8250_probe()
595 if (data->clk) { in dw8250_probe()
596 err = clk_notifier_register(data->clk, &data->clk_notifier); in dw8250_probe()
598 dev_warn(p->dev, "Failed to set the clock notifier\n"); in dw8250_probe()
600 queue_work(system_unbound_wq, &data->clk_work); in dw8250_probe()
611 reset_control_assert(data->rst); in dw8250_probe()
614 clk_disable_unprepare(data->pclk); in dw8250_probe()
617 clk_disable_unprepare(data->clk); in dw8250_probe()
625 struct device *dev = &pdev->dev; in dw8250_remove()
629 if (data->clk) { in dw8250_remove()
630 clk_notifier_unregister(data->clk, &data->clk_notifier); in dw8250_remove()
632 flush_work(&data->clk_work); in dw8250_remove()
635 serial8250_unregister_port(data->data.line); in dw8250_remove()
637 reset_control_assert(data->rst); in dw8250_remove()
639 clk_disable_unprepare(data->pclk); in dw8250_remove()
641 clk_disable_unprepare(data->clk); in dw8250_remove()
654 serial8250_suspend_port(data->data.line); in dw8250_suspend()
663 serial8250_resume_port(data->data.line); in dw8250_resume()
674 clk_disable_unprepare(data->clk); in dw8250_runtime_suspend()
676 clk_disable_unprepare(data->pclk); in dw8250_runtime_suspend()
685 clk_prepare_enable(data->pclk); in dw8250_runtime_resume()
687 clk_prepare_enable(data->clk); in dw8250_runtime_resume()
699 { .compatible = "snps,dw-apb-uart" },
700 { .compatible = "cavium,octeon-3860-uart" },
701 { .compatible = "marvell,armada-38x-uart" },
702 { .compatible = "renesas,rzn1-uart" },
725 .name = "dw-apb-uart",
739 MODULE_ALIAS("platform:dw-apb-uart");