1 // SPDX-License-Identifier: GPL-2.0
3  * Copyright (c) 2014 - 2018, NVIDIA CORPORATION.  All rights reserved.
34 #include <dt-bindings/thermal/tegra124-soctherm.h>
197 #define REG_GET_MASK(r, m)	(((r) & (m)) >> (ffs(m) - 1))
200 				 (((v) & (m >> (ffs(m) - 1))) << (ffs(m) - 1)))
203 #define THROT_DEPTH_DIVIDEND(depth)	((256 * (100 - (depth)) / 100) - 1)
205 /* gk20a nv_therm interface N:3 Mapping. Levels defined in tegra124-soctherm.h
212 #define THROT_LEVEL_TO_DEPTH(level)	((0x1 << (level)) - 1)
229 					(ALARM_OFFSET * (throt - THROTTLE_OC1)))
232 					(ALARM_OFFSET * (throt - THROTTLE_OC1)))
235 					(ALARM_OFFSET * (throt - THROTTLE_OC1)))
238 					(ALARM_OFFSET * (throt - THROTTLE_OC1)))
241 					(ALARM_OFFSET * (throt - THROTTLE_OC1)))
244 					(4 * (throt - THROTTLE_OC1)))
260 static const int min_low_temp = -127000;
361  * ccroc_writel() - writes a value to a CCROC register
370 	writel(value, (ts->ccroc_regs + reg));  in ccroc_writel()
374  * ccroc_readl() - reads specified register from CCROC IP block
382 	return readl(ts->ccroc_regs + reg);  in ccroc_readl()
387 	const struct tegra_tsensor *sensor = &tegra->soc->tsensors[i];  in enable_tsensor()
388 	void __iomem *base = tegra->regs + sensor->base;  in enable_tsensor()
391 	val = sensor->config->tall << SENSOR_CONFIG0_TALL_SHIFT;  in enable_tsensor()
394 	val  = (sensor->config->tsample - 1) << SENSOR_CONFIG1_TSAMPLE_SHIFT;  in enable_tsensor()
395 	val |= sensor->config->tiddq_en << SENSOR_CONFIG1_TIDDQ_EN_SHIFT;  in enable_tsensor()
396 	val |= sensor->config->ten_count << SENSOR_CONFIG1_TEN_COUNT_SHIFT;  in enable_tsensor()
400 	writel(tegra->calib[i], base + SENSOR_CONFIG2);  in enable_tsensor()
419 		t *= -1;  in translate_temp()
429 	val = readl(zone->reg);  in tegra_thermctl_get_temp()
430 	val = REG_GET_MASK(val, zone->sg->sensor_temp_mask);  in tegra_thermctl_get_temp()
437  * enforce_temp_range() - check and enforce temperature range [min, max]
459  * thermtrip_program() - Configures the hardware to shut down the
472  * Return: 0 upon success, or %-EINVAL upon failure.
482 	if (!sg || !sg->thermtrip_threshold_mask)  in thermtrip_program()
483 		return -EINVAL;  in thermtrip_program()
485 	temp = enforce_temp_range(dev, trip_temp) / ts->soc->thresh_grain;  in thermtrip_program()
487 	r = readl(ts->regs + THERMCTL_THERMTRIP_CTL);  in thermtrip_program()
488 	r = REG_SET_MASK(r, sg->thermtrip_threshold_mask, temp);  in thermtrip_program()
489 	r = REG_SET_MASK(r, sg->thermtrip_enable_mask, 1);  in thermtrip_program()
490 	r = REG_SET_MASK(r, sg->thermtrip_any_en_mask, 0);  in thermtrip_program()
491 	writel(r, ts->regs + THERMCTL_THERMTRIP_CTL);  in thermtrip_program()
497  * throttrip_program() - Configures the hardware to throttle the
511  * Return: 0 upon success, or %-EINVAL upon failure.
523 	if (!sg || !stc || !stc->init)  in throttrip_program()
524 		return -EINVAL;  in throttrip_program()
526 	temp = enforce_temp_range(dev, trip_temp) / ts->soc->thresh_grain;  in throttrip_program()
529 	throt = stc->id;  in throttrip_program()
530 	reg_off = THERMCTL_LVL_REG(sg->thermctl_lvl0_offset, throt + 1);  in throttrip_program()
540 				 "invalid throt id %d - assuming HEAVY",  in throttrip_program()
544 	r = readl(ts->regs + reg_off);  in throttrip_program()
545 	r = REG_SET_MASK(r, sg->thermctl_lvl0_up_thresh_mask, temp);  in throttrip_program()
546 	r = REG_SET_MASK(r, sg->thermctl_lvl0_dn_thresh_mask, temp);  in throttrip_program()
550 	writel(r, ts->regs + reg_off);  in throttrip_program()
560 	for (i = 0; ts->throt_cfgs[i].name; i++)  in find_throttle_cfg_by_name()
561 		if (!strcmp(ts->throt_cfgs[i].name, name))  in find_throttle_cfg_by_name()
562 			return &ts->throt_cfgs[i];  in find_throttle_cfg_by_name()
570 	struct tsensor_group_thermtrips *tt = ts->soc->thermtrips;  in tsensor_group_thermtrip_get()
576 		for (i = 0; i < ts->soc->num_ttgs; i++) {  in tsensor_group_thermtrip_get()
588 	struct thermal_zone_device *tz = zone->tz;  in tegra_thermctl_set_trip_temp()
589 	struct tegra_soctherm *ts = zone->ts;  in tegra_thermctl_set_trip_temp()
590 	const struct tegra_tsensor_group *sg = zone->sg;  in tegra_thermctl_set_trip_temp()
591 	struct device *dev = zone->dev;  in tegra_thermctl_set_trip_temp()
596 		return -EINVAL;  in tegra_thermctl_set_trip_temp()
598 	ret = tz->ops->get_trip_type(tz, trip, &type);  in tegra_thermctl_set_trip_temp()
608 		if (min_low_temp == tsensor_group_thermtrip_get(ts, sg->id))  in tegra_thermctl_set_trip_temp()
620 			if (!ts->throt_cfgs[i].init)  in tegra_thermctl_set_trip_temp()
623 			cdev = ts->throt_cfgs[i].cdev;  in tegra_thermctl_set_trip_temp()
625 				stc = find_throttle_cfg_by_name(ts, cdev->type);  in tegra_thermctl_set_trip_temp()
640 	struct thermal_zone_device *tz = zone->tz;  in tegra_thermctl_get_trend()
644 		return -EINVAL;  in tegra_thermctl_get_trend()
646 	ret = tz->ops->get_trip_temp(zone->tz, trip, &trip_temp);  in tegra_thermctl_get_trend()
650 	temp = READ_ONCE(tz->temperature);  in tegra_thermctl_get_trend()
651 	last_temp = READ_ONCE(tz->last_temperature);  in tegra_thermctl_get_trend()
672 	mutex_lock(&zn->ts->thermctl_lock);  in thermal_irq_enable()
673 	r = readl(zn->ts->regs + THERMCTL_INTR_ENABLE);  in thermal_irq_enable()
674 	r = REG_SET_MASK(r, zn->sg->thermctl_isr_mask, TH_INTR_UP_DN_EN);  in thermal_irq_enable()
675 	writel(r, zn->ts->regs + THERMCTL_INTR_ENABLE);  in thermal_irq_enable()
676 	mutex_unlock(&zn->ts->thermctl_lock);  in thermal_irq_enable()
684 	mutex_lock(&zn->ts->thermctl_lock);  in thermal_irq_disable()
685 	r = readl(zn->ts->regs + THERMCTL_INTR_DISABLE);  in thermal_irq_disable()
686 	r = REG_SET_MASK(r, zn->sg->thermctl_isr_mask, 0);  in thermal_irq_disable()
687 	writel(r, zn->ts->regs + THERMCTL_INTR_DISABLE);  in thermal_irq_disable()
688 	mutex_unlock(&zn->ts->thermctl_lock);  in thermal_irq_disable()
698 	r = readl(zone->ts->regs + zone->sg->thermctl_lvl0_offset);  in tegra_thermctl_set_trips()
700 	writel(r, zone->ts->regs + zone->sg->thermctl_lvl0_offset);  in tegra_thermctl_set_trips()
702 	lo = enforce_temp_range(zone->dev, lo) / zone->ts->soc->thresh_grain;  in tegra_thermctl_set_trips()
703 	hi = enforce_temp_range(zone->dev, hi) / zone->ts->soc->thresh_grain;  in tegra_thermctl_set_trips()
704 	dev_dbg(zone->dev, "%s hi:%d, lo:%d\n", __func__, hi, lo);  in tegra_thermctl_set_trips()
706 	r = REG_SET_MASK(r, zone->sg->thermctl_lvl0_up_thresh_mask, hi);  in tegra_thermctl_set_trips()
707 	r = REG_SET_MASK(r, zone->sg->thermctl_lvl0_dn_thresh_mask, lo);  in tegra_thermctl_set_trips()
709 	writel(r, zone->ts->regs + zone->sg->thermctl_lvl0_offset);  in tegra_thermctl_set_trips()
730 		return -EINVAL;  in get_hot_temp()
733 		ret = tz->ops->get_trip_type(tz, i, &type);  in get_hot_temp()
735 			return -EINVAL;  in get_hot_temp()
737 			ret = tz->ops->get_trip_temp(tz, i, temp);  in get_hot_temp()
745 	return -EINVAL;  in get_hot_temp()
749  * tegra_soctherm_set_hwtrips() - set HW trip point from DT data
767  * "thermtrip: will shut down when sensor group XXX reaches YYYYYY mC"
770  * ""throttrip: will throttle when sensor group XXX reaches YYYYYY mC"
781 	temperature = tsensor_group_thermtrip_get(ts, sg->id);  in tegra_soctherm_set_hwtrips()
783 		if (tz->ops->get_crit_temp(tz, &temperature))  in tegra_soctherm_set_hwtrips()
788 		dev_err(dev, "thermtrip: %s: error during enable\n", sg->name);  in tegra_soctherm_set_hwtrips()
792 	dev_info(dev, "thermtrip: will shut down when %s reaches %d mC\n",  in tegra_soctherm_set_hwtrips()
793 		 sg->name, temperature);  in tegra_soctherm_set_hwtrips()
798 			 sg->name);  in tegra_soctherm_set_hwtrips()
805 		if (!ts->throt_cfgs[i].init)  in tegra_soctherm_set_hwtrips()
808 		cdev = ts->throt_cfgs[i].cdev;  in tegra_soctherm_set_hwtrips()
810 			stc = find_throttle_cfg_by_name(ts, cdev->type);  in tegra_soctherm_set_hwtrips()
817 				sg->name);  in tegra_soctherm_set_hwtrips()
822 			 "throttrip: will throttle when %s reaches %d mC\n",  in tegra_soctherm_set_hwtrips()
823 			 sg->name, temperature);  in tegra_soctherm_set_hwtrips()
829 			 sg->name);  in tegra_soctherm_set_hwtrips()
845 	 * cause a new interrupt but this is taken care of by the re-reading of  in soctherm_thermal_isr()
848 	r = readl(ts->regs + THERMCTL_INTR_STATUS);  in soctherm_thermal_isr()
849 	writel(r, ts->regs + THERMCTL_INTR_DISABLE);  in soctherm_thermal_isr()
855  * soctherm_thermal_isr_thread() - Handles a thermal interrupt request
866  * Disabled interrupts are re-enabled.
877 	st = readl(ts->regs + THERMCTL_INTR_STATUS);  in soctherm_thermal_isr_thread()
894 		writel(ex, ts->regs + THERMCTL_INTR_STATUS);  in soctherm_thermal_isr_thread()
898 			tz = ts->thermctl_tzs[TEGRA124_SOCTHERM_SENSOR_CPU];  in soctherm_thermal_isr_thread()
904 			tz = ts->thermctl_tzs[TEGRA124_SOCTHERM_SENSOR_GPU];  in soctherm_thermal_isr_thread()
910 			tz = ts->thermctl_tzs[TEGRA124_SOCTHERM_SENSOR_PLLX];  in soctherm_thermal_isr_thread()
916 			tz = ts->thermctl_tzs[TEGRA124_SOCTHERM_SENSOR_MEM];  in soctherm_thermal_isr_thread()
929 		writel(st, ts->regs + THERMCTL_INTR_STATUS);  in soctherm_thermal_isr_thread()
936  * soctherm_oc_intr_enable() - Enables the soctherm over-current interrupt
939  * @enable:		Flag indicating enable the soctherm over-current
942  * Enables a specific over-current pins @alarm to raise an interrupt if the flag
954 	r = readl(ts->regs + OC_INTR_ENABLE);  in soctherm_oc_intr_enable()
972 	writel(r, ts->regs + OC_INTR_ENABLE);  in soctherm_oc_intr_enable()
976  * soctherm_handle_alarm() - Handles soctherm alarms
979  * "Handles" over-current alarms (OC1, OC2, OC3, and OC4) by printing
982  * Return: -EINVAL for @alarm = THROTTLE_OC3, otherwise 0 (success).
986 	int rv = -EINVAL;  in soctherm_handle_alarm()
1021  * soctherm_edp_isr_thread() - log an over-current interrupt request
1025  * Over-current events are handled in hardware. This function is called to log
1027  * over-current interrupt registers for registers are set but
1038 	st = readl(ts->regs + OC_INTR_STATUS);  in soctherm_edp_isr_thread()
1049 		writel(st, ts->regs + OC_INTR_STATUS);  in soctherm_edp_isr_thread()
1083 		writel(st, ts->regs + OC_INTR_STATUS);  in soctherm_edp_isr_thread()
1090  * soctherm_edp_isr() - Disables any active interrupts
1097  * handle asserted interrupts and subsequently unmask/re-enable them.
1112 	r = readl(ts->regs + OC_INTR_STATUS);  in soctherm_edp_isr()
1113 	writel(r, ts->regs + OC_INTR_DISABLE);  in soctherm_edp_isr()
1119  * soctherm_oc_irq_lock() - locks the over-current interrupt request
1123  * a particular over-current interrupt request.
1129 	mutex_lock(&d->irq_lock);  in soctherm_oc_irq_lock()
1133  * soctherm_oc_irq_sync_unlock() - Unlocks the OC interrupt request
1137  * with a particular over-current interrupt request.
1143 	mutex_unlock(&d->irq_lock);  in soctherm_oc_irq_sync_unlock()
1147  * soctherm_oc_irq_enable() - Enables the SOC_THERM over-current interrupt queue
1151  * to respond to over-current interrupts.
1158 	d->irq_enable |= BIT(data->hwirq);  in soctherm_oc_irq_enable()
1162  * soctherm_oc_irq_disable() - Disables overcurrent interrupt requests
1174 	d->irq_enable &= ~BIT(data->hwirq);  in soctherm_oc_irq_disable()
1183  * soctherm_oc_irq_map() - SOC_THERM interrupt request domain mapper
1202 	struct soctherm_oc_irq_chip_data *data = h->host_data;  in soctherm_oc_irq_map()
1205 	irq_set_chip(virq, &data->irq_chip);  in soctherm_oc_irq_map()
1211  * soctherm_irq_domain_xlate_twocell() - xlate for soctherm interrupts
1231 		return -EINVAL;  in soctherm_irq_domain_xlate_twocell()
1237 	*out_hwirq = intspec[0] - 1;  in soctherm_irq_domain_xlate_twocell()
1248  * soctherm_oc_int_init() - Initial enabling of the over
1256  * -ENOMEM (out of memory), or irq_base if the function failed to
1284 		return -ENOMEM;  in soctherm_oc_int_init()
1294 	struct platform_device *pdev = s->private;  in regs_show()
1296 	const struct tegra_tsensor *tsensors = ts->soc->tsensors;  in regs_show()
1297 	const struct tegra_tsensor_group **ttgs = ts->soc->ttgs;  in regs_show()
1301 	seq_puts(s, "-----TSENSE (convert HW)-----\n");  in regs_show()
1303 	for (i = 0; i < ts->soc->num_tsensors; i++) {  in regs_show()
1304 		r = readl(ts->regs + tsensors[i].base + SENSOR_CONFIG1);  in regs_show()
1322 		r = readl(ts->regs + tsensors[i].base + SENSOR_STATUS1);  in regs_show()
1328 		r = readl(ts->regs + tsensors[i].base + SENSOR_STATUS0);  in regs_show()
1334 		r = readl(ts->regs + tsensors[i].base + SENSOR_CONFIG0);  in regs_show()
1346 		r = readl(ts->regs + tsensors[i].base + SENSOR_CONFIG2);  in regs_show()
1353 	r = readl(ts->regs + SENSOR_PDIV);  in regs_show()
1356 	r = readl(ts->regs + SENSOR_HOTSPOT_OFF);  in regs_show()
1360 	seq_puts(s, "-----SOC_THERM-----\n");  in regs_show()
1362 	r = readl(ts->regs + SENSOR_TEMP1);  in regs_show()
1367 	r = readl(ts->regs + SENSOR_TEMP2);  in regs_show()
1373 	for (i = 0; i < ts->soc->num_ttgs; i++) {  in regs_show()
1374 		seq_printf(s, "%s:\n", ttgs[i]->name);  in regs_show()
1378 			u16 off = ttgs[i]->thermctl_lvl0_offset;  in regs_show()
1380 			r = readl(ts->regs + THERMCTL_LVL_REG(off, level));  in regs_show()
1382 			mask = ttgs[i]->thermctl_lvl0_up_thresh_mask;  in regs_show()
1384 			v = sign_extend32(state, ts->soc->bptt - 1);  in regs_show()
1385 			v *= ts->soc->thresh_grain;  in regs_show()
1388 			mask = ttgs[i]->thermctl_lvl0_dn_thresh_mask;  in regs_show()
1390 			v = sign_extend32(state, ts->soc->bptt - 1);  in regs_show()
1391 			v *= ts->soc->thresh_grain;  in regs_show()
1431 	r = readl(ts->regs + THERMCTL_STATS_CTL);  in regs_show()
1433 		   r & STATS_CTL_EN_UP ? "En" : "--",  in regs_show()
1434 		   r & STATS_CTL_EN_DN ? "En" : "--");  in regs_show()
1440 		r = readl(ts->regs + THERMCTL_LVL_REG(off, level));  in regs_show()
1444 		r = readl(ts->regs + THERMCTL_LVL_REG(off, level));  in regs_show()
1448 	r = readl(ts->regs + THERMCTL_THERMTRIP_CTL);  in regs_show()
1449 	state = REG_GET_MASK(r, ttgs[0]->thermtrip_any_en_mask);  in regs_show()
1451 	for (i = 0; i < ts->soc->num_ttgs; i++) {  in regs_show()
1452 		state = REG_GET_MASK(r, ttgs[i]->thermtrip_enable_mask);  in regs_show()
1453 		seq_printf(s, "     %s En(%d) ", ttgs[i]->name, state);  in regs_show()
1454 		state = REG_GET_MASK(r, ttgs[i]->thermtrip_threshold_mask);  in regs_show()
1455 		state *= ts->soc->thresh_grain;  in regs_show()
1459 	r = readl(ts->regs + THROT_GLOBAL_CFG);  in regs_show()
1463 	seq_puts(s, "---------------------------------------------------\n");  in regs_show()
1464 	r = readl(ts->regs + THROT_STATUS);  in regs_show()
1472 	r = readl(ts->regs + CPU_PSKIP_STATUS);  in regs_show()
1473 	if (ts->soc->use_ccroc) {  in regs_show()
1497 	tegra->debugfs_dir = root;  in soctherm_debug_init()
1510 	if (!tegra->clock_soctherm || !tegra->clock_tsensor)  in soctherm_clk_enable()
1511 		return -EINVAL;  in soctherm_clk_enable()
1513 	reset_control_assert(tegra->reset);  in soctherm_clk_enable()
1516 		err = clk_prepare_enable(tegra->clock_soctherm);  in soctherm_clk_enable()
1518 			reset_control_deassert(tegra->reset);  in soctherm_clk_enable()
1522 		err = clk_prepare_enable(tegra->clock_tsensor);  in soctherm_clk_enable()
1524 			clk_disable_unprepare(tegra->clock_soctherm);  in soctherm_clk_enable()
1525 			reset_control_deassert(tegra->reset);  in soctherm_clk_enable()
1529 		clk_disable_unprepare(tegra->clock_tsensor);  in soctherm_clk_enable()
1530 		clk_disable_unprepare(tegra->clock_soctherm);  in soctherm_clk_enable()
1533 	reset_control_deassert(tegra->reset);  in soctherm_clk_enable()
1548 	struct tegra_soctherm *ts = cdev->devdata;  in throt_get_cdev_cur_state()
1551 	r = readl(ts->regs + THROT_STATUS);  in throt_get_cdev_cur_state()
1574 	struct device *dev = &pdev->dev;  in soctherm_thermtrips_parse()
1576 	struct tsensor_group_thermtrips *tt = ts->soc->thermtrips;  in soctherm_thermtrips_parse()
1577 	const int max_num_prop = ts->soc->num_ttgs * 2;  in soctherm_thermtrips_parse()
1582 		return -ENOMEM;  in soctherm_thermtrips_parse()
1584 	n = of_property_count_u32_elems(dev->of_node, "nvidia,thermtrips");  in soctherm_thermtrips_parse()
1593 	tlb = devm_kcalloc(&pdev->dev, max_num_prop, sizeof(u32), GFP_KERNEL);  in soctherm_thermtrips_parse()
1595 		return -ENOMEM;  in soctherm_thermtrips_parse()
1596 	ret = of_property_read_u32_array(dev->of_node, "nvidia,thermtrips",  in soctherm_thermtrips_parse()
1622 	if (of_property_read_bool(np_oc, "nvidia,polarity-active-low"))  in soctherm_oc_cfg_parse()
1623 		stc->oc_cfg.active_low = 1;  in soctherm_oc_cfg_parse()
1625 		stc->oc_cfg.active_low = 0;  in soctherm_oc_cfg_parse()
1627 	if (!of_property_read_u32(np_oc, "nvidia,count-threshold", &val)) {  in soctherm_oc_cfg_parse()
1628 		stc->oc_cfg.intr_en = 1;  in soctherm_oc_cfg_parse()
1629 		stc->oc_cfg.alarm_cnt_thresh = val;  in soctherm_oc_cfg_parse()
1632 	if (!of_property_read_u32(np_oc, "nvidia,throttle-period-us", &val))  in soctherm_oc_cfg_parse()
1633 		stc->oc_cfg.throt_period = val;  in soctherm_oc_cfg_parse()
1635 	if (!of_property_read_u32(np_oc, "nvidia,alarm-filter", &val))  in soctherm_oc_cfg_parse()
1636 		stc->oc_cfg.alarm_filter = val;  in soctherm_oc_cfg_parse()
1639 	stc->oc_cfg.mode = OC_THROTTLE_MODE_BRIEF;  in soctherm_oc_cfg_parse()
1652 		dev_err(dev, "throttle-cfg: %s: invalid priority\n", stc->name);  in soctherm_throt_cfg_parse()
1653 		return -EINVAL;  in soctherm_throt_cfg_parse()
1655 	stc->priority = val;  in soctherm_throt_cfg_parse()
1657 	ret = of_property_read_u32(np, ts->soc->use_ccroc ?  in soctherm_throt_cfg_parse()
1658 				   "nvidia,cpu-throt-level" :  in soctherm_throt_cfg_parse()
1659 				   "nvidia,cpu-throt-percent", &val);  in soctherm_throt_cfg_parse()
1661 		if (ts->soc->use_ccroc &&  in soctherm_throt_cfg_parse()
1663 			stc->cpu_throt_level = val;  in soctherm_throt_cfg_parse()
1664 		else if (!ts->soc->use_ccroc && val <= 100)  in soctherm_throt_cfg_parse()
1665 			stc->cpu_throt_depth = val;  in soctherm_throt_cfg_parse()
1672 	ret = of_property_read_u32(np, "nvidia,gpu-throt-level", &val);  in soctherm_throt_cfg_parse()
1674 		stc->gpu_throt_level = val;  in soctherm_throt_cfg_parse()
1681 	dev_err(dev, "throttle-cfg: %s: no throt prop or invalid prop\n",  in soctherm_throt_cfg_parse()
1682 		stc->name);  in soctherm_throt_cfg_parse()
1683 	return -EINVAL;  in soctherm_throt_cfg_parse()
1687  * soctherm_init_hw_throt_cdev() - Parse the HW throttle configurations
1693 	struct device *dev = &pdev->dev;  in soctherm_init_hw_throt_cdev()
1700 		ts->throt_cfgs[i].name = throt_names[i];  in soctherm_init_hw_throt_cdev()
1701 		ts->throt_cfgs[i].id = i;  in soctherm_init_hw_throt_cdev()
1702 		ts->throt_cfgs[i].init = false;  in soctherm_init_hw_throt_cdev()
1705 	np_stc = of_get_child_by_name(dev->of_node, "throttle-cfgs");  in soctherm_init_hw_throt_cdev()
1708 			 "throttle-cfg: no throttle-cfgs - not enabling\n");  in soctherm_init_hw_throt_cdev()
1717 		name = np_stcc->name;  in soctherm_init_hw_throt_cdev()
1721 				"throttle-cfg: could not find %s\n", name);  in soctherm_init_hw_throt_cdev()
1725 		if (stc->init) {  in soctherm_init_hw_throt_cdev()
1726 			dev_err(dev, "throttle-cfg: %s: redefined!\n", name);  in soctherm_init_hw_throt_cdev()
1735 		if (stc->id >= THROTTLE_OC1) {  in soctherm_init_hw_throt_cdev()
1737 			stc->init = true;  in soctherm_init_hw_throt_cdev()
1745 					"throttle-cfg: %s: failed to register cooling device\n",  in soctherm_init_hw_throt_cdev()
1749 			stc->cdev = tcd;  in soctherm_init_hw_throt_cdev()
1750 			stc->init = true;  in soctherm_init_hw_throt_cdev()
1759  * throttlectl_cpu_level_cfg() - programs CCROC NV_THERM level config
1763  * It's necessary to set up the CPU-local CCROC NV_THERM instance with
1766  * This function pre-programs the CCROC NV_THERM levels in terms of
1767  * pre-configured "Low", "Medium" or "Heavy" throttle levels which are
1807  * throttlectl_cpu_level_select() - program CPU pulse skipper config
1813  * data.  This function is used on SoCs which have CPU-local pulse
1824 	switch (ts->throt_cfgs[throt].cpu_throt_level) {  in throttlectl_cpu_level_select()
1839 	r = readl(ts->regs + THROT_PSKIP_CTRL(throt, THROTTLE_DEV_CPU));  in throttlectl_cpu_level_select()
1843 	writel(r, ts->regs + THROT_PSKIP_CTRL(throt, THROTTLE_DEV_CPU));  in throttlectl_cpu_level_select()
1847 	writel(r, ts->regs + THROT_PSKIP_RAMP(throt, THROTTLE_DEV_CPU));  in throttlectl_cpu_level_select()
1851  * throttlectl_cpu_mn() - program CPU pulse skipper configuration
1869 	depth = ts->throt_cfgs[throt].cpu_throt_depth;  in throttlectl_cpu_mn()
1872 	r = readl(ts->regs + THROT_PSKIP_CTRL(throt, THROTTLE_DEV_CPU));  in throttlectl_cpu_mn()
1876 	writel(r, ts->regs + THROT_PSKIP_CTRL(throt, THROTTLE_DEV_CPU));  in throttlectl_cpu_mn()
1878 	r = readl(ts->regs + THROT_PSKIP_RAMP(throt, THROTTLE_DEV_CPU));  in throttlectl_cpu_mn()
1881 	writel(r, ts->regs + THROT_PSKIP_RAMP(throt, THROTTLE_DEV_CPU));  in throttlectl_cpu_mn()
1885  * throttlectl_gpu_level_select() - selects throttling level for GPU
1890  * pre-configured "Low", "Medium" or "Heavy" throttle levels.
1899 	level = ts->throt_cfgs[throt].gpu_throt_level;  in throttlectl_gpu_level_select()
1901 	r = readl(ts->regs + THROT_PSKIP_CTRL(throt, THROTTLE_DEV_GPU));  in throttlectl_gpu_level_select()
1904 	writel(r, ts->regs + THROT_PSKIP_CTRL(throt, THROTTLE_DEV_GPU));  in throttlectl_gpu_level_select()
1911 	struct soctherm_oc_cfg *oc = &ts->throt_cfgs[throt].oc_cfg;  in soctherm_oc_cfg_program()
1913 	if (oc->mode == OC_THROTTLE_MODE_DISABLED)  in soctherm_oc_cfg_program()
1914 		return -EINVAL;  in soctherm_oc_cfg_program()
1917 	r = REG_SET_MASK(r, OC1_CFG_THROTTLE_MODE_MASK, oc->mode);  in soctherm_oc_cfg_program()
1918 	r = REG_SET_MASK(r, OC1_CFG_ALARM_POLARITY_MASK, oc->active_low);  in soctherm_oc_cfg_program()
1920 	writel(r, ts->regs + ALARM_CFG(throt));  in soctherm_oc_cfg_program()
1921 	writel(oc->throt_period, ts->regs + ALARM_THROTTLE_PERIOD(throt));  in soctherm_oc_cfg_program()
1922 	writel(oc->alarm_cnt_thresh, ts->regs + ALARM_CNT_THRESHOLD(throt));  in soctherm_oc_cfg_program()
1923 	writel(oc->alarm_filter, ts->regs + ALARM_FILTER(throt));  in soctherm_oc_cfg_program()
1924 	soctherm_oc_intr_enable(ts, throt, oc->intr_en);  in soctherm_oc_cfg_program()
1930  * soctherm_throttle_program() - programs pulse skippers' configuration
1941 	struct soctherm_throt_cfg stc = ts->throt_cfgs[throt];  in soctherm_throttle_program()
1950 	if (ts->soc->use_ccroc)  in soctherm_throttle_program()
1958 	writel(r, ts->regs + THROT_PRIORITY_CTRL(throt));  in soctherm_throttle_program()
1961 	writel(r, ts->regs + THROT_DELAY_CTRL(throt));  in soctherm_throttle_program()
1963 	r = readl(ts->regs + THROT_PRIORITY_LOCK);  in soctherm_throttle_program()
1969 	writel(r, ts->regs + THROT_PRIORITY_LOCK);  in soctherm_throttle_program()
1979 	if (ts->soc->use_ccroc) {  in tegra_soctherm_throttle()
1990 	if (ts->soc->use_ccroc) {  in tegra_soctherm_throttle()
1997 		writel(v, ts->regs + THROT_GLOBAL_CFG);  in tegra_soctherm_throttle()
1999 		v = readl(ts->clk_regs + CAR_SUPER_CCLKG_DIVIDER);  in tegra_soctherm_throttle()
2001 		writel(v, ts->clk_regs + CAR_SUPER_CCLKG_DIVIDER);  in tegra_soctherm_throttle()
2007 	writel(v, ts->regs + THERMCTL_STATS_CTL);  in tegra_soctherm_throttle()
2013 	struct device_node *np = pdev->dev.of_node;  in soctherm_interrupts_init()
2018 		dev_err(&pdev->dev, "soctherm_oc_int_init failed\n");  in soctherm_interrupts_init()
2022 	tegra->thermal_irq = platform_get_irq(pdev, 0);  in soctherm_interrupts_init()
2023 	if (tegra->thermal_irq < 0) {  in soctherm_interrupts_init()
2024 		dev_dbg(&pdev->dev, "get 'thermal_irq' failed.\n");  in soctherm_interrupts_init()
2028 	tegra->edp_irq = platform_get_irq(pdev, 1);  in soctherm_interrupts_init()
2029 	if (tegra->edp_irq < 0) {  in soctherm_interrupts_init()
2030 		dev_dbg(&pdev->dev, "get 'edp_irq' failed.\n");  in soctherm_interrupts_init()
2034 	ret = devm_request_threaded_irq(&pdev->dev,  in soctherm_interrupts_init()
2035 					tegra->thermal_irq,  in soctherm_interrupts_init()
2039 					dev_name(&pdev->dev),  in soctherm_interrupts_init()
2042 		dev_err(&pdev->dev, "request_irq 'thermal_irq' failed.\n");  in soctherm_interrupts_init()
2046 	ret = devm_request_threaded_irq(&pdev->dev,  in soctherm_interrupts_init()
2047 					tegra->edp_irq,  in soctherm_interrupts_init()
2054 		dev_err(&pdev->dev, "request_irq 'edp_irq' failed.\n");  in soctherm_interrupts_init()
2064 	const struct tegra_tsensor_group **ttgs = tegra->soc->ttgs;  in soctherm_init()
2069 	for (i = 0; i < tegra->soc->num_tsensors; ++i)  in soctherm_init()
2073 	pdiv = readl(tegra->regs + SENSOR_PDIV);  in soctherm_init()
2074 	hotspot = readl(tegra->regs + SENSOR_HOTSPOT_OFF);  in soctherm_init()
2075 	for (i = 0; i < tegra->soc->num_ttgs; ++i) {  in soctherm_init()
2076 		pdiv = REG_SET_MASK(pdiv, ttgs[i]->pdiv_mask,  in soctherm_init()
2077 				    ttgs[i]->pdiv);  in soctherm_init()
2079 		if (ttgs[i]->id == TEGRA124_SOCTHERM_SENSOR_PLLX)  in soctherm_init()
2082 					ttgs[i]->pllx_hotspot_mask,  in soctherm_init()
2083 					ttgs[i]->pllx_hotspot_diff);  in soctherm_init()
2085 	writel(pdiv, tegra->regs + SENSOR_PDIV);  in soctherm_init()
2086 	writel(hotspot, tegra->regs + SENSOR_HOTSPOT_OFF);  in soctherm_init()
2089 	tegra_soctherm_throttle(&pdev->dev);  in soctherm_init()
2095 		.compatible = "nvidia,tegra124-soctherm",
2101 		.compatible = "nvidia,tegra132-soctherm",
2107 		.compatible = "nvidia,tegra210-soctherm",
2126 	match = of_match_node(tegra_soctherm_of_match, pdev->dev.of_node);  in tegra_soctherm_probe()
2128 		return -ENODEV;  in tegra_soctherm_probe()
2130 	soc = (struct tegra_soctherm_soc *)match->data;  in tegra_soctherm_probe()
2131 	if (soc->num_ttgs > TEGRA124_SOCTHERM_SENSOR_NUM)  in tegra_soctherm_probe()
2132 		return -EINVAL;  in tegra_soctherm_probe()
2134 	tegra = devm_kzalloc(&pdev->dev, sizeof(*tegra), GFP_KERNEL);  in tegra_soctherm_probe()
2136 		return -ENOMEM;  in tegra_soctherm_probe()
2138 	mutex_init(&tegra->thermctl_lock);  in tegra_soctherm_probe()
2139 	dev_set_drvdata(&pdev->dev, tegra);  in tegra_soctherm_probe()
2141 	tegra->soc = soc;  in tegra_soctherm_probe()
2144 					   "soctherm-reg");  in tegra_soctherm_probe()
2145 	tegra->regs = devm_ioremap_resource(&pdev->dev, res);  in tegra_soctherm_probe()
2146 	if (IS_ERR(tegra->regs)) {  in tegra_soctherm_probe()
2147 		dev_err(&pdev->dev, "can't get soctherm registers");  in tegra_soctherm_probe()
2148 		return PTR_ERR(tegra->regs);  in tegra_soctherm_probe()
2151 	if (!tegra->soc->use_ccroc) {  in tegra_soctherm_probe()
2153 						   "car-reg");  in tegra_soctherm_probe()
2154 		tegra->clk_regs = devm_ioremap_resource(&pdev->dev, res);  in tegra_soctherm_probe()
2155 		if (IS_ERR(tegra->clk_regs)) {  in tegra_soctherm_probe()
2156 			dev_err(&pdev->dev, "can't get car clk registers");  in tegra_soctherm_probe()
2157 			return PTR_ERR(tegra->clk_regs);  in tegra_soctherm_probe()
2161 						   "ccroc-reg");  in tegra_soctherm_probe()
2162 		tegra->ccroc_regs = devm_ioremap_resource(&pdev->dev, res);  in tegra_soctherm_probe()
2163 		if (IS_ERR(tegra->ccroc_regs)) {  in tegra_soctherm_probe()
2164 			dev_err(&pdev->dev, "can't get ccroc registers");  in tegra_soctherm_probe()
2165 			return PTR_ERR(tegra->ccroc_regs);  in tegra_soctherm_probe()
2169 	tegra->reset = devm_reset_control_get(&pdev->dev, "soctherm");  in tegra_soctherm_probe()
2170 	if (IS_ERR(tegra->reset)) {  in tegra_soctherm_probe()
2171 		dev_err(&pdev->dev, "can't get soctherm reset\n");  in tegra_soctherm_probe()
2172 		return PTR_ERR(tegra->reset);  in tegra_soctherm_probe()
2175 	tegra->clock_tsensor = devm_clk_get(&pdev->dev, "tsensor");  in tegra_soctherm_probe()
2176 	if (IS_ERR(tegra->clock_tsensor)) {  in tegra_soctherm_probe()
2177 		dev_err(&pdev->dev, "can't get tsensor clock\n");  in tegra_soctherm_probe()
2178 		return PTR_ERR(tegra->clock_tsensor);  in tegra_soctherm_probe()
2181 	tegra->clock_soctherm = devm_clk_get(&pdev->dev, "soctherm");  in tegra_soctherm_probe()
2182 	if (IS_ERR(tegra->clock_soctherm)) {  in tegra_soctherm_probe()
2183 		dev_err(&pdev->dev, "can't get soctherm clock\n");  in tegra_soctherm_probe()
2184 		return PTR_ERR(tegra->clock_soctherm);  in tegra_soctherm_probe()
2187 	tegra->calib = devm_kcalloc(&pdev->dev,  in tegra_soctherm_probe()
2188 				    soc->num_tsensors, sizeof(u32),  in tegra_soctherm_probe()
2190 	if (!tegra->calib)  in tegra_soctherm_probe()
2191 		return -ENOMEM;  in tegra_soctherm_probe()
2194 	err = tegra_calc_shared_calib(soc->tfuse, &shared_calib);  in tegra_soctherm_probe()
2199 	for (i = 0; i < soc->num_tsensors; ++i) {  in tegra_soctherm_probe()
2200 		err = tegra_calc_tsensor_calib(&soc->tsensors[i],  in tegra_soctherm_probe()
2202 					       &tegra->calib[i]);  in tegra_soctherm_probe()
2207 	tegra->thermctl_tzs = devm_kcalloc(&pdev->dev,  in tegra_soctherm_probe()
2208 					   soc->num_ttgs, sizeof(z),  in tegra_soctherm_probe()
2210 	if (!tegra->thermctl_tzs)  in tegra_soctherm_probe()
2211 		return -ENOMEM;  in tegra_soctherm_probe()
2223 	for (i = 0; i < soc->num_ttgs; ++i) {  in tegra_soctherm_probe()
2225 			devm_kzalloc(&pdev->dev, sizeof(*zone), GFP_KERNEL);  in tegra_soctherm_probe()
2227 			err = -ENOMEM;  in tegra_soctherm_probe()
2231 		zone->reg = tegra->regs + soc->ttgs[i]->sensor_temp_offset;  in tegra_soctherm_probe()
2232 		zone->dev = &pdev->dev;  in tegra_soctherm_probe()
2233 		zone->sg = soc->ttgs[i];  in tegra_soctherm_probe()
2234 		zone->ts = tegra;  in tegra_soctherm_probe()
2236 		z = devm_thermal_zone_of_sensor_register(&pdev->dev,  in tegra_soctherm_probe()
2237 							 soc->ttgs[i]->id, zone,  in tegra_soctherm_probe()
2241 			dev_err(&pdev->dev, "failed to register sensor: %d\n",  in tegra_soctherm_probe()
2246 		zone->tz = z;  in tegra_soctherm_probe()
2247 		tegra->thermctl_tzs[soc->ttgs[i]->id] = z;  in tegra_soctherm_probe()
2250 		err = tegra_soctherm_set_hwtrips(&pdev->dev, soc->ttgs[i], z);  in tegra_soctherm_probe()
2271 	debugfs_remove_recursive(tegra->debugfs_dir);  in tegra_soctherm_remove()
2291 	struct tegra_soctherm_soc *soc = tegra->soc;  in soctherm_resume()
2296 		dev_err(&pdev->dev,  in soctherm_resume()
2303 	for (i = 0; i < soc->num_ttgs; ++i) {  in soctherm_resume()
2306 		tz = tegra->thermctl_tzs[soc->ttgs[i]->id];  in soctherm_resume()
2307 		err = tegra_soctherm_set_hwtrips(dev, soc->ttgs[i], tz);  in soctherm_resume()
2309 			dev_err(&pdev->dev,  in soctherm_resume()