28 	TSHUT_MODE_CRU = 0,
35  * 0: low active, 1: high active
38 	TSHUT_LOW_ACTIVE = 0,
47 	SENSOR_CPU = 0,
57 	ADC_DECREMENT = 0,
88  * @tshut_mode: the hardware-controlled shutdown mode (0:CRU 1:GPIO)
89  * @tshut_polarity: the hardware-controlled active polarity (0:LOW 1:HIGH)
151  * @tshut_mode: the hardware-controlled shutdown mode (0:CRU 1:GPIO)
152  * @tshut_polarity: the hardware-controlled active polarity (0:LOW 1:HIGH)
179 #define TSADCV2_USER_CON			0x00
180 #define TSADCV2_AUTO_CON			0x04
181 #define TSADCV2_INT_EN				0x08
182 #define TSADCV2_INT_PD				0x0c
183 #define TSADCV2_DATA(chn)			(0x20 + (chn) * 0x04)
184 #define TSADCV2_COMP_INT(chn)		        (0x30 + (chn) * 0x04)
185 #define TSADCV2_COMP_SHUT(chn)		        (0x40 + (chn) * 0x04)
186 #define TSADCV2_HIGHT_INT_DEBOUNCE		0x60
187 #define TSADCV2_HIGHT_TSHUT_DEBOUNCE		0x64
188 #define TSADCV2_AUTO_PERIOD			0x68
189 #define TSADCV2_AUTO_PERIOD_HT			0x6c
191 #define TSADCV2_AUTO_EN				BIT(0)
204 #define TSADCV2_DATA_MASK			0xfff
205 #define TSADCV3_DATA_MASK			0x3ff
214 #define TSADCV2_USER_INTER_PD_SOC		0x340 /* 13 clocks */
216 #define GRF_SARADC_TESTBIT			0x0e644
217 #define GRF_TSADC_TESTBIT_L			0x0e648
218 #define GRF_TSADC_TESTBIT_H			0x0e64c
220 #define PX30_GRF_SOC_CON2			0x0408
222 #define GRF_SARADC_TESTBIT_ON			(0x10001 << 2)
223 #define GRF_TSADC_TESTBIT_H_ON			(0x10001 << 2)
224 #define GRF_TSADC_VCM_EN_L			(0x10001 << 7)
225 #define GRF_TSADC_VCM_EN_H			(0x10001 << 7)
227 #define GRF_CON_TSADC_CH_INV			(0x10001 << 1)
245 	{0, -40000},
254 	{436, 0},
284 	{0, -40000},
293 	{629, 0},
332 	{3728, 0},
358 	{0, 125000},
362 	{0, -40000},
370 	{368, 0},
400 	{0, -40000},
409 	{122, 0},
439 	{0, -40000},
448 	{470, 0},
485 	low = 0;  in rk_tsadcv2_temp_to_code()
591 	return 0;  in rk_tsadcv2_code_to_temp()
598  * @tshut_polarity: the hardware-controlled active polarity (0:LOW 1:HIGH)
616 		writel_relaxed(0U | TSADCV2_AUTO_TSHUT_POLARITY_HIGH,  in rk_tsadcv2_initialize()
619 		writel_relaxed(0U & ~TSADCV2_AUTO_TSHUT_POLARITY_HIGH,  in rk_tsadcv2_initialize()
635  * @tshut_polarity: the hardware-controlled active polarity (0:LOW 1:HIGH)
690 		writel_relaxed(0U | TSADCV2_AUTO_TSHUT_POLARITY_HIGH,  in rk_tsadcv3_initialize()
693 		writel_relaxed(0U & ~TSADCV2_AUTO_TSHUT_POLARITY_HIGH,  in rk_tsadcv3_initialize()
781 		return 0;  in rk_tsadcv2_alarm_temp()
796 	return 0;  in rk_tsadcv2_alarm_temp()
815 	return 0;  in rk_tsadcv2_tshut_temp()
836 	.chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
860 	.chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
884 	.chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
933 	.chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
956 	.chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
981 	.chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
1006 	.chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
1086 	for (i = 0; i < thermal->chip->chn_num; i++)  in rockchip_thermal_alarm_irq_thread()
1186 	return 0;  in rockchip_configure_from_dt()
1217 	return 0;  in rockchip_thermal_register_sensor()
1245 	irq = platform_get_irq(pdev, 0);  in rockchip_thermal_probe()
1246 	if (irq < 0)  in rockchip_thermal_probe()
1260 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);  in rockchip_thermal_probe()
1312 	for (i = 0; i < thermal->chip->chn_num; i++) {  in rockchip_thermal_probe()
1336 	for (i = 0; i < thermal->chip->chn_num; i++) {  in rockchip_thermal_probe()
1348 	return 0;  in rockchip_thermal_probe()
1363 	for (i = 0; i < thermal->chip->chn_num; i++) {  in rockchip_thermal_remove()
1375 	return 0;  in rockchip_thermal_remove()
1383 	for (i = 0; i < thermal->chip->chn_num; i++)  in rockchip_thermal_suspend()
1393 	return 0;  in rockchip_thermal_suspend()
1417 	for (i = 0; i < thermal->chip->chn_num; i++) {  in rockchip_thermal_resume()
1433 	for (i = 0; i < thermal->chip->chn_num; i++)  in rockchip_thermal_resume()
1438 	return 0;  in rockchip_thermal_resume()