Lines Matching +full:thermal +full:- +full:sensors
1 // SPDX-License-Identifier: GPL-2.0-only
15 #include <linux/nvmem-consumer.h>
22 #include <linux/thermal.h>
34 /* Thermal Controller Registers */
91 /* MT8173 thermal sensors */
98 /* AUXADC channel 11 is used for the temperature sensors */
101 /* The total number of temperature sensors in the MT8173 */
119 * MT8183 has 6 sensors and needs 6 VTS calibration data.
120 * MT8173 has 5 sensors and needs 5 VTS calibration data.
121 * MT2701 has 3 sensors and needs 3 VTS calibration data.
122 * MT2712 has 4 sensors and needs 4 VTS calibration data.
166 /* MT2701 thermal sensors */
171 /* AUXADC channel 11 is used for the temperature sensors */
174 /* The total number of temperature sensors in the MT2701 */
186 /* MT2712 thermal sensors */
192 /* AUXADC channel 11 is used for the temperature sensors */
195 /* The total number of temperature sensors in the MT2712 */
220 /* MT8183 thermal sensors */
228 /* AUXADC channel is used for the temperature sensors */
231 /* The total number of temperature sensors in the MT8183 */
250 const int *sensors; member
295 /* MT8183 thermal sensor data */
316 /* MT8173 thermal sensor data */
339 /* MT2701 thermal sensor data */
359 /* MT2712 thermal sensor data */
379 /* MT7622 thermal sensor data */
388 * The MT8173 thermal controller has four banks. Each bank can read up to
389 * four temperature sensors simultaneously. The MT8173 has a total of 5
390 * temperature sensors. We use each bank to measure a certain area of the
394 * The thermal core only gets the maximum temperature of all banks, so
412 .sensors = mt8173_bank_data[0],
415 .sensors = mt8173_bank_data[1],
418 .sensors = mt8173_bank_data[2],
421 .sensors = mt8173_bank_data[3],
431 * The MT2701 thermal controller has one bank, which can read up to
432 * three temperature sensors simultaneously. The MT2701 has a total of 3
433 * temperature sensors.
435 * The thermal core only gets the maximum temperature of this one bank,
452 .sensors = mt2701_bank_data,
462 * The MT2712 thermal controller has one bank, which can read up to
463 * four temperature sensors simultaneously. The MT2712 has a total of 4
464 * temperature sensors.
466 * The thermal core only gets the maximum temperature of this one bank,
483 .sensors = mt2712_bank_data,
508 .sensors = mt7622_bank_data,
518 * The MT8183 thermal controller has one bank for the current SW framework.
519 * The MT8183 has a total of 6 temperature sensors.
520 * There are two thermal controller to control the six sensor.
521 * The first one bind 2 sensor, and the other bind 4 sensors.
522 * The thermal core only gets the maximum temperature of all sensor, so
540 .sensors = mt8183_bank_data,
551 * raw_to_mcelsius - convert a raw ADC value to mcelsius
552 * @mt: The thermal controller
566 tmp /= mt->conf->cali_val + mt->o_slope; in raw_to_mcelsius_v1()
567 tmp /= 10000 + mt->adc_ge; in raw_to_mcelsius_v1()
568 tmp *= raw - mt->vts[sensno] - 3350; in raw_to_mcelsius_v1()
571 return mt->degc_cali * 500 - tmp; in raw_to_mcelsius_v1()
587 g_gain = 10000 + (((mt->adc_ge - 512) * 10000) >> 12); in raw_to_mcelsius_v2()
588 g_oe = mt->adc_oe - 512; in raw_to_mcelsius_v2()
589 format_1 = mt->vts[VTS2] + 3105 - g_oe; in raw_to_mcelsius_v2()
590 format_2 = (mt->degc_cali * 10) >> 1; in raw_to_mcelsius_v2()
593 tmp = (((((raw - g_oe) * 10000) >> 12) * 10000) / g_gain) - g_x_roomt; in raw_to_mcelsius_v2()
596 if (mt->o_slope_sign == 0) in raw_to_mcelsius_v2()
597 tmp = tmp / (165 - mt->o_slope); in raw_to_mcelsius_v2()
599 tmp = tmp / (165 + mt->o_slope); in raw_to_mcelsius_v2()
601 return (format_2 - tmp) * 100; in raw_to_mcelsius_v2()
605 * mtk_thermal_get_bank - get bank
613 struct mtk_thermal *mt = bank->mt; in mtk_thermal_get_bank()
616 if (mt->conf->need_switch_bank) { in mtk_thermal_get_bank()
617 mutex_lock(&mt->lock); in mtk_thermal_get_bank()
619 val = readl(mt->thermal_base + PTPCORESEL); in mtk_thermal_get_bank()
621 val |= bank->id; in mtk_thermal_get_bank()
622 writel(val, mt->thermal_base + PTPCORESEL); in mtk_thermal_get_bank()
627 * mtk_thermal_put_bank - release bank
634 struct mtk_thermal *mt = bank->mt; in mtk_thermal_put_bank()
636 if (mt->conf->need_switch_bank) in mtk_thermal_put_bank()
637 mutex_unlock(&mt->lock); in mtk_thermal_put_bank()
641 * mtk_thermal_bank_temperature - get the temperature of a bank
645 * the sensors associated to the bank.
649 struct mtk_thermal *mt = bank->mt; in mtk_thermal_bank_temperature()
650 const struct mtk_thermal_data *conf = mt->conf; in mtk_thermal_bank_temperature()
654 for (i = 0; i < conf->bank_data[bank->id].num_sensors; i++) { in mtk_thermal_bank_temperature()
655 raw = readl(mt->thermal_base + conf->msr[i]); in mtk_thermal_bank_temperature()
657 if (mt->conf->version == MTK_THERMAL_V1) { in mtk_thermal_bank_temperature()
659 mt, conf->bank_data[bank->id].sensors[i], raw); in mtk_thermal_bank_temperature()
662 mt, conf->bank_data[bank->id].sensors[i], raw); in mtk_thermal_bank_temperature()
686 for (i = 0; i < mt->conf->num_banks; i++) { in mtk_read_temp()
687 struct mtk_thermal_bank *bank = &mt->banks[i]; in mtk_read_temp()
709 struct mtk_thermal_bank *bank = &mt->banks[num]; in mtk_thermal_init_bank()
710 const struct mtk_thermal_data *conf = mt->conf; in mtk_thermal_init_bank()
713 int offset = mt->conf->controller_offset[ctrl_id]; in mtk_thermal_init_bank()
714 void __iomem *controller_base = mt->thermal_base + offset; in mtk_thermal_init_bank()
716 bank->id = num; in mtk_thermal_init_bank()
717 bank->mt = mt; in mtk_thermal_init_bank()
747 * The MT8173 thermal controller does not have its own ADC. Instead it in mtk_thermal_init_bank()
748 * uses AHB bus accesses to control the AUXADC. To do this the thermal in mtk_thermal_init_bank()
751 * Also the thermal controller controls a mux in the APMIXEDSYS register in mtk_thermal_init_bank()
759 writel(BIT(conf->auxadc_channel), controller_base + TEMP_ADCMUX); in mtk_thermal_init_bank()
765 if (mt->conf->version == MTK_THERMAL_V1) { in mtk_thermal_init_bank()
772 writel(BIT(conf->auxadc_channel), controller_base + TEMP_ADCEN); in mtk_thermal_init_bank()
779 writel(auxadc_phys_base + AUXADC_DATA(conf->auxadc_channel), in mtk_thermal_init_bank()
783 writel(auxadc_phys_base + AUXADC_DATA(conf->auxadc_channel), in mtk_thermal_init_bank()
800 for (i = 0; i < conf->bank_data[num].num_sensors; i++) in mtk_thermal_init_bank()
801 writel(conf->sensor_mux_values[conf->bank_data[num].sensors[i]], in mtk_thermal_init_bank()
802 mt->thermal_base + conf->adcpnp[i]); in mtk_thermal_init_bank()
804 writel((1 << conf->bank_data[num].num_sensors) - 1, in mtk_thermal_init_bank()
831 return -EINVAL; in mtk_thermal_extract_efuse_v1()
833 mt->adc_ge = CALIB_BUF1_ADC_GE_V1(buf[1]); in mtk_thermal_extract_efuse_v1()
835 for (i = 0; i < mt->conf->num_sensors; i++) { in mtk_thermal_extract_efuse_v1()
836 switch (mt->conf->vts_index[i]) { in mtk_thermal_extract_efuse_v1()
838 mt->vts[VTS1] = CALIB_BUF0_VTS_TS1_V1(buf[0]); in mtk_thermal_extract_efuse_v1()
841 mt->vts[VTS2] = CALIB_BUF0_VTS_TS2_V1(buf[0]); in mtk_thermal_extract_efuse_v1()
844 mt->vts[VTS3] = CALIB_BUF1_VTS_TS3_V1(buf[1]); in mtk_thermal_extract_efuse_v1()
847 mt->vts[VTS4] = CALIB_BUF2_VTS_TS4_V1(buf[2]); in mtk_thermal_extract_efuse_v1()
850 mt->vts[VTS5] = CALIB_BUF2_VTS_TS5_V1(buf[2]); in mtk_thermal_extract_efuse_v1()
853 mt->vts[VTSABB] = in mtk_thermal_extract_efuse_v1()
861 mt->degc_cali = CALIB_BUF0_DEGC_CALI_V1(buf[0]); in mtk_thermal_extract_efuse_v1()
864 mt->o_slope = -CALIB_BUF0_O_SLOPE_V1(buf[0]); in mtk_thermal_extract_efuse_v1()
866 mt->o_slope = CALIB_BUF0_O_SLOPE_V1(buf[0]); in mtk_thermal_extract_efuse_v1()
874 return -EINVAL; in mtk_thermal_extract_efuse_v2()
876 mt->adc_oe = CALIB_BUF0_ADC_OE_V2(buf[0]); in mtk_thermal_extract_efuse_v2()
877 mt->adc_ge = CALIB_BUF0_ADC_GE_V2(buf[0]); in mtk_thermal_extract_efuse_v2()
878 mt->degc_cali = CALIB_BUF0_DEGC_CALI_V2(buf[0]); in mtk_thermal_extract_efuse_v2()
879 mt->o_slope = CALIB_BUF0_O_SLOPE_V2(buf[0]); in mtk_thermal_extract_efuse_v2()
880 mt->vts[VTS1] = CALIB_BUF1_VTS_TS1_V2(buf[1]); in mtk_thermal_extract_efuse_v2()
881 mt->vts[VTS2] = CALIB_BUF1_VTS_TS2_V2(buf[1]); in mtk_thermal_extract_efuse_v2()
882 mt->vts[VTSABB] = CALIB_BUF1_VTS_TSABB_V2(buf[1]); in mtk_thermal_extract_efuse_v2()
883 mt->o_slope_sign = CALIB_BUF1_O_SLOPE_SIGN_V2(buf[1]); in mtk_thermal_extract_efuse_v2()
897 mt->adc_ge = 512; in mtk_thermal_get_calibration_data()
898 for (i = 0; i < mt->conf->num_sensors; i++) in mtk_thermal_get_calibration_data()
899 mt->vts[i] = 260; in mtk_thermal_get_calibration_data()
900 mt->degc_cali = 40; in mtk_thermal_get_calibration_data()
901 mt->o_slope = 0; in mtk_thermal_get_calibration_data()
903 cell = nvmem_cell_get(dev, "calibration-data"); in mtk_thermal_get_calibration_data()
905 if (PTR_ERR(cell) == -EPROBE_DEFER) in mtk_thermal_get_calibration_data()
919 ret = -EINVAL; in mtk_thermal_get_calibration_data()
923 if (mt->conf->version == MTK_THERMAL_V1) in mtk_thermal_get_calibration_data()
941 .compatible = "mediatek,mt8173-thermal",
945 .compatible = "mediatek,mt2701-thermal",
949 .compatible = "mediatek,mt2712-thermal",
953 .compatible = "mediatek,mt7622-thermal",
957 .compatible = "mediatek,mt8183-thermal",
981 writel(0x1, mt->thermal_base + TEMP_MONCTL0); in mtk_thermal_release_periodic_ts()
982 tmp = readl(mt->thermal_base + TEMP_MSRCTL1); in mtk_thermal_release_periodic_ts()
983 writel((tmp & (~0x10e)), mt->thermal_base + TEMP_MSRCTL1); in mtk_thermal_release_periodic_ts()
989 struct device_node *auxadc, *apmixedsys, *np = pdev->dev.of_node; in mtk_thermal_probe()
996 mt = devm_kzalloc(&pdev->dev, sizeof(*mt), GFP_KERNEL); in mtk_thermal_probe()
998 return -ENOMEM; in mtk_thermal_probe()
1000 mt->conf = of_device_get_match_data(&pdev->dev); in mtk_thermal_probe()
1002 mt->clk_peri_therm = devm_clk_get(&pdev->dev, "therm"); in mtk_thermal_probe()
1003 if (IS_ERR(mt->clk_peri_therm)) in mtk_thermal_probe()
1004 return PTR_ERR(mt->clk_peri_therm); in mtk_thermal_probe()
1006 mt->clk_auxadc = devm_clk_get(&pdev->dev, "auxadc"); in mtk_thermal_probe()
1007 if (IS_ERR(mt->clk_auxadc)) in mtk_thermal_probe()
1008 return PTR_ERR(mt->clk_auxadc); in mtk_thermal_probe()
1011 mt->thermal_base = devm_ioremap_resource(&pdev->dev, res); in mtk_thermal_probe()
1012 if (IS_ERR(mt->thermal_base)) in mtk_thermal_probe()
1013 return PTR_ERR(mt->thermal_base); in mtk_thermal_probe()
1015 ret = mtk_thermal_get_calibration_data(&pdev->dev, mt); in mtk_thermal_probe()
1019 mutex_init(&mt->lock); in mtk_thermal_probe()
1021 mt->dev = &pdev->dev; in mtk_thermal_probe()
1025 dev_err(&pdev->dev, "missing auxadc node\n"); in mtk_thermal_probe()
1026 return -ENODEV; in mtk_thermal_probe()
1035 dev_err(&pdev->dev, "Can't get auxadc phys address\n"); in mtk_thermal_probe()
1036 return -EINVAL; in mtk_thermal_probe()
1041 dev_err(&pdev->dev, "missing apmixedsys node\n"); in mtk_thermal_probe()
1042 return -ENODEV; in mtk_thermal_probe()
1051 dev_err(&pdev->dev, "Can't get auxadc phys address\n"); in mtk_thermal_probe()
1052 return -EINVAL; in mtk_thermal_probe()
1055 ret = device_reset(&pdev->dev); in mtk_thermal_probe()
1059 ret = clk_prepare_enable(mt->clk_auxadc); in mtk_thermal_probe()
1061 dev_err(&pdev->dev, "Can't enable auxadc clk: %d\n", ret); in mtk_thermal_probe()
1065 ret = clk_prepare_enable(mt->clk_peri_therm); in mtk_thermal_probe()
1067 dev_err(&pdev->dev, "Can't enable peri clk: %d\n", ret); in mtk_thermal_probe()
1071 if (mt->conf->version == MTK_THERMAL_V2) { in mtk_thermal_probe()
1076 for (ctrl_id = 0; ctrl_id < mt->conf->num_controller ; ctrl_id++) in mtk_thermal_probe()
1077 for (i = 0; i < mt->conf->num_banks; i++) in mtk_thermal_probe()
1083 tzdev = devm_thermal_zone_of_sensor_register(&pdev->dev, 0, mt, in mtk_thermal_probe()
1093 clk_disable_unprepare(mt->clk_peri_therm); in mtk_thermal_probe()
1095 clk_disable_unprepare(mt->clk_auxadc); in mtk_thermal_probe()
1104 clk_disable_unprepare(mt->clk_peri_therm); in mtk_thermal_remove()
1105 clk_disable_unprepare(mt->clk_auxadc); in mtk_thermal_remove()
1114 .name = "mtk-thermal",
1126 MODULE_DESCRIPTION("Mediatek thermal driver");