360 static inline void stm32_spi_clr_bits(struct stm32_spi *spi,  in stm32_spi_clr_bits()  function
383 	stm32_spi_clr_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_SPE);  in stm32h7_spi_get_fifo_size()
678 	stm32_spi_clr_bits(spi, STM32F4_SPI_CR2, STM32F4_SPI_CR2_TXEIE |  in stm32f4_spi_disable()
694 	stm32_spi_clr_bits(spi, STM32F4_SPI_CR1, STM32F4_SPI_CR1_SPE);  in stm32f4_spi_disable()
696 	stm32_spi_clr_bits(spi, STM32F4_SPI_CR2, STM32F4_SPI_CR2_TXDMAEN |  in stm32f4_spi_disable()
758 	stm32_spi_clr_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_SPE);  in stm32h7_spi_disable()
760 	stm32_spi_clr_bits(spi, STM32H7_SPI_CFG1, STM32H7_SPI_CFG1_TXDMAEN |  in stm32h7_spi_disable()
873 		stm32_spi_clr_bits(spi, STM32F4_SPI_CR2,  in stm32f4_spi_irq_event()
1373 	stm32_spi_clr_bits(spi, spi->cfg->regs->dma_rx_en.reg,  in stm32_spi_transfer_one_dma()
1393 		stm32_spi_clr_bits(spi, STM32F4_SPI_CR1, STM32F4_SPI_CR1_DFF);  in stm32f4_spi_set_bpw()
1486 		stm32_spi_clr_bits(spi, STM32F4_SPI_CR1,  in stm32f4_spi_set_mode()
1492 		stm32_spi_clr_bits(spi, STM32F4_SPI_CR1,  in stm32f4_spi_set_mode()
1513 		stm32_spi_clr_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_HDDIR);  in stm32h7_spi_set_mode()
1726 	stm32_spi_clr_bits(spi, STM32F4_SPI_I2SCFGR,  in stm32f4_spi_config()
1757 	stm32_spi_clr_bits(spi, STM32H7_SPI_I2SCFGR,  in stm32h7_spi_config()