Lines Matching +full:dma +full:- +full:maxburst
1 // SPDX-License-Identifier: GPL-2.0
5 // Copyright (C) 2017, STMicroelectronics - All Rights Reserved
173 * use PIO for small transfers, avoiding DMA setup/teardown overhead for drivers
179 * struct stm32_spi_reg - stm32 SPI register & bitfield desc
191 * struct stm32_spi_regspec - stm32 registers definition, compatible dependent data
193 * @dma_rx_en: SPI DMA RX enable register end SPI DMA RX enable bit
194 * @dma_tx_en: SPI DMA TX enable register end SPI DMA TX enable bit
217 * struct stm32_spi_cfg - stm32 compatible configuration data
229 * @can_dma: routine to determine if the transfer is eligible for DMA use
231 * using DMA
232 * @dma_rx_cb: routine to call after DMA RX channel operation is complete
233 * @dma_tx_cb: routine to call after DMA TX channel operation is complete
264 * struct stm32_spi - private data of the SPI controller
275 * @cur_midi: master inter-data idleness in ns
281 * @cur_usedma: boolean to know if dma is used in current transfer
286 * @dma_tx: dma channel for TX transfer
287 * @dma_rx: dma channel for RX transfer
356 writel_relaxed(readl_relaxed(spi->base + offset) | bits, in stm32_spi_set_bits()
357 spi->base + offset); in stm32_spi_set_bits()
363 writel_relaxed(readl_relaxed(spi->base + offset) & ~bits, in stm32_spi_clr_bits()
364 spi->base + offset); in stm32_spi_clr_bits()
368 * stm32h7_spi_get_fifo_size - Return fifo size
376 spin_lock_irqsave(&spi->lock, flags); in stm32h7_spi_get_fifo_size()
380 while (readl_relaxed(spi->base + STM32H7_SPI_SR) & STM32H7_SPI_SR_TXP) in stm32h7_spi_get_fifo_size()
381 writeb_relaxed(++count, spi->base + STM32H7_SPI_TXDR); in stm32h7_spi_get_fifo_size()
385 spin_unlock_irqrestore(&spi->lock, flags); in stm32h7_spi_get_fifo_size()
387 dev_dbg(spi->dev, "%d x 8-bit fifo size\n", count); in stm32h7_spi_get_fifo_size()
393 * stm32f4_spi_get_bpw_mask - Return bits per word mask
398 dev_dbg(spi->dev, "8-bit or 16-bit data frame supported\n"); in stm32f4_spi_get_bpw_mask()
403 * stm32h7_spi_get_bpw_mask - Return bits per word mask
411 spin_lock_irqsave(&spi->lock, flags); in stm32h7_spi_get_bpw_mask()
415 * maximum data size of periperal instances is limited to 16-bit in stm32h7_spi_get_bpw_mask()
419 cfg1 = readl_relaxed(spi->base + STM32H7_SPI_CFG1); in stm32h7_spi_get_bpw_mask()
424 spin_unlock_irqrestore(&spi->lock, flags); in stm32h7_spi_get_bpw_mask()
426 dev_dbg(spi->dev, "%d-bit maximum data frame\n", max_bpw); in stm32h7_spi_get_bpw_mask()
432 * stm32_spi_prepare_mbr - Determine baud rate divisor value
438 * Return baud rate divisor value in case of success or -EINVAL
445 /* Ensure spi->clk_rate is even */ in stm32_spi_prepare_mbr()
446 div = DIV_ROUND_UP(spi->clk_rate & ~0x1, speed_hz); in stm32_spi_prepare_mbr()
449 * SPI framework set xfer->speed_hz to master->max_speed_hz if in stm32_spi_prepare_mbr()
450 * xfer->speed_hz is greater than master->max_speed_hz, and it returns in stm32_spi_prepare_mbr()
451 * an error when xfer->speed_hz is lower than master->min_speed_hz, so in stm32_spi_prepare_mbr()
456 return -EINVAL; in stm32_spi_prepare_mbr()
459 if (div & (div - 1)) in stm32_spi_prepare_mbr()
462 mbrdiv = fls(div) - 1; in stm32_spi_prepare_mbr()
464 spi->cur_speed = spi->clk_rate / (1 << mbrdiv); in stm32_spi_prepare_mbr()
466 return mbrdiv - 1; in stm32_spi_prepare_mbr()
470 * stm32h7_spi_prepare_fthlv - Determine FIFO threshold level
479 half_fifo = (spi->fifo_size / 2); in stm32h7_spi_prepare_fthlv()
487 if (spi->cur_bpw <= 8) in stm32h7_spi_prepare_fthlv()
489 else if (spi->cur_bpw <= 16) in stm32h7_spi_prepare_fthlv()
495 if (spi->cur_bpw > 8) in stm32h7_spi_prepare_fthlv()
496 fthlv -= (fthlv % 2); /* multiple of 2 */ in stm32h7_spi_prepare_fthlv()
498 fthlv -= (fthlv % 4); /* multiple of 4 */ in stm32h7_spi_prepare_fthlv()
507 * stm32f4_spi_write_tx - Write bytes to Transmit Data Register
515 if ((spi->tx_len > 0) && (readl_relaxed(spi->base + STM32F4_SPI_SR) & in stm32f4_spi_write_tx()
517 u32 offs = spi->cur_xferlen - spi->tx_len; in stm32f4_spi_write_tx()
519 if (spi->cur_bpw == 16) { in stm32f4_spi_write_tx()
520 const u16 *tx_buf16 = (const u16 *)(spi->tx_buf + offs); in stm32f4_spi_write_tx()
522 writew_relaxed(*tx_buf16, spi->base + STM32F4_SPI_DR); in stm32f4_spi_write_tx()
523 spi->tx_len -= sizeof(u16); in stm32f4_spi_write_tx()
525 const u8 *tx_buf8 = (const u8 *)(spi->tx_buf + offs); in stm32f4_spi_write_tx()
527 writeb_relaxed(*tx_buf8, spi->base + STM32F4_SPI_DR); in stm32f4_spi_write_tx()
528 spi->tx_len -= sizeof(u8); in stm32f4_spi_write_tx()
532 dev_dbg(spi->dev, "%s: %d bytes left\n", __func__, spi->tx_len); in stm32f4_spi_write_tx()
536 * stm32h7_spi_write_txfifo - Write bytes in Transmit Data Register
544 while ((spi->tx_len > 0) && in stm32h7_spi_write_txfifo()
545 (readl_relaxed(spi->base + STM32H7_SPI_SR) & in stm32h7_spi_write_txfifo()
547 u32 offs = spi->cur_xferlen - spi->tx_len; in stm32h7_spi_write_txfifo()
549 if (spi->tx_len >= sizeof(u32)) { in stm32h7_spi_write_txfifo()
550 const u32 *tx_buf32 = (const u32 *)(spi->tx_buf + offs); in stm32h7_spi_write_txfifo()
552 writel_relaxed(*tx_buf32, spi->base + STM32H7_SPI_TXDR); in stm32h7_spi_write_txfifo()
553 spi->tx_len -= sizeof(u32); in stm32h7_spi_write_txfifo()
554 } else if (spi->tx_len >= sizeof(u16)) { in stm32h7_spi_write_txfifo()
555 const u16 *tx_buf16 = (const u16 *)(spi->tx_buf + offs); in stm32h7_spi_write_txfifo()
557 writew_relaxed(*tx_buf16, spi->base + STM32H7_SPI_TXDR); in stm32h7_spi_write_txfifo()
558 spi->tx_len -= sizeof(u16); in stm32h7_spi_write_txfifo()
560 const u8 *tx_buf8 = (const u8 *)(spi->tx_buf + offs); in stm32h7_spi_write_txfifo()
562 writeb_relaxed(*tx_buf8, spi->base + STM32H7_SPI_TXDR); in stm32h7_spi_write_txfifo()
563 spi->tx_len -= sizeof(u8); in stm32h7_spi_write_txfifo()
567 dev_dbg(spi->dev, "%s: %d bytes left\n", __func__, spi->tx_len); in stm32h7_spi_write_txfifo()
571 * stm32f4_spi_read_rx - Read bytes from Receive Data Register
579 if ((spi->rx_len > 0) && (readl_relaxed(spi->base + STM32F4_SPI_SR) & in stm32f4_spi_read_rx()
581 u32 offs = spi->cur_xferlen - spi->rx_len; in stm32f4_spi_read_rx()
583 if (spi->cur_bpw == 16) { in stm32f4_spi_read_rx()
584 u16 *rx_buf16 = (u16 *)(spi->rx_buf + offs); in stm32f4_spi_read_rx()
586 *rx_buf16 = readw_relaxed(spi->base + STM32F4_SPI_DR); in stm32f4_spi_read_rx()
587 spi->rx_len -= sizeof(u16); in stm32f4_spi_read_rx()
589 u8 *rx_buf8 = (u8 *)(spi->rx_buf + offs); in stm32f4_spi_read_rx()
591 *rx_buf8 = readb_relaxed(spi->base + STM32F4_SPI_DR); in stm32f4_spi_read_rx()
592 spi->rx_len -= sizeof(u8); in stm32f4_spi_read_rx()
596 dev_dbg(spi->dev, "%s: %d bytes left\n", __func__, spi->rx_len); in stm32f4_spi_read_rx()
600 * stm32h7_spi_read_rxfifo - Read bytes in Receive Data Register
609 u32 sr = readl_relaxed(spi->base + STM32H7_SPI_SR); in stm32h7_spi_read_rxfifo()
613 while ((spi->rx_len > 0) && in stm32h7_spi_read_rxfifo()
616 u32 offs = spi->cur_xferlen - spi->rx_len; in stm32h7_spi_read_rxfifo()
618 if ((spi->rx_len >= sizeof(u32)) || in stm32h7_spi_read_rxfifo()
620 u32 *rx_buf32 = (u32 *)(spi->rx_buf + offs); in stm32h7_spi_read_rxfifo()
622 *rx_buf32 = readl_relaxed(spi->base + STM32H7_SPI_RXDR); in stm32h7_spi_read_rxfifo()
623 spi->rx_len -= sizeof(u32); in stm32h7_spi_read_rxfifo()
624 } else if ((spi->rx_len >= sizeof(u16)) || in stm32h7_spi_read_rxfifo()
625 (flush && (rxplvl >= 2 || spi->cur_bpw > 8))) { in stm32h7_spi_read_rxfifo()
626 u16 *rx_buf16 = (u16 *)(spi->rx_buf + offs); in stm32h7_spi_read_rxfifo()
628 *rx_buf16 = readw_relaxed(spi->base + STM32H7_SPI_RXDR); in stm32h7_spi_read_rxfifo()
629 spi->rx_len -= sizeof(u16); in stm32h7_spi_read_rxfifo()
631 u8 *rx_buf8 = (u8 *)(spi->rx_buf + offs); in stm32h7_spi_read_rxfifo()
633 *rx_buf8 = readb_relaxed(spi->base + STM32H7_SPI_RXDR); in stm32h7_spi_read_rxfifo()
634 spi->rx_len -= sizeof(u8); in stm32h7_spi_read_rxfifo()
637 sr = readl_relaxed(spi->base + STM32H7_SPI_SR); in stm32h7_spi_read_rxfifo()
642 dev_dbg(spi->dev, "%s%s: %d bytes left\n", __func__, in stm32h7_spi_read_rxfifo()
643 flush ? "(flush)" : "", spi->rx_len); in stm32h7_spi_read_rxfifo()
647 * stm32_spi_enable - Enable SPI controller
652 dev_dbg(spi->dev, "enable controller\n"); in stm32_spi_enable()
654 stm32_spi_set_bits(spi, spi->cfg->regs->en.reg, in stm32_spi_enable()
655 spi->cfg->regs->en.mask); in stm32_spi_enable()
659 * stm32f4_spi_disable - Disable SPI controller
667 dev_dbg(spi->dev, "disable controller\n"); in stm32f4_spi_disable()
669 spin_lock_irqsave(&spi->lock, flags); in stm32f4_spi_disable()
671 if (!(readl_relaxed(spi->base + STM32F4_SPI_CR1) & in stm32f4_spi_disable()
673 spin_unlock_irqrestore(&spi->lock, flags); in stm32f4_spi_disable()
683 if (readl_relaxed_poll_timeout_atomic(spi->base + STM32F4_SPI_SR, in stm32f4_spi_disable()
686 dev_warn(spi->dev, "disabling condition timeout\n"); in stm32f4_spi_disable()
689 if (spi->cur_usedma && spi->dma_tx) in stm32f4_spi_disable()
690 dmaengine_terminate_all(spi->dma_tx); in stm32f4_spi_disable()
691 if (spi->cur_usedma && spi->dma_rx) in stm32f4_spi_disable()
692 dmaengine_terminate_all(spi->dma_rx); in stm32f4_spi_disable()
700 readl_relaxed(spi->base + STM32F4_SPI_DR); in stm32f4_spi_disable()
701 readl_relaxed(spi->base + STM32F4_SPI_SR); in stm32f4_spi_disable()
703 spin_unlock_irqrestore(&spi->lock, flags); in stm32f4_spi_disable()
707 * stm32h7_spi_disable - Disable SPI controller
710 * RX-Fifo is flushed when SPI controller is disabled. To prevent any data
712 * RX-Fifo.
723 dev_dbg(spi->dev, "disable controller\n"); in stm32h7_spi_disable()
725 spin_lock_irqsave(&spi->lock, flags); in stm32h7_spi_disable()
727 cr1 = readl_relaxed(spi->base + STM32H7_SPI_CR1); in stm32h7_spi_disable()
730 spin_unlock_irqrestore(&spi->lock, flags); in stm32h7_spi_disable()
735 if (readl_relaxed_poll_timeout_atomic(spi->base + STM32H7_SPI_SR, in stm32h7_spi_disable()
740 spi->base + STM32H7_SPI_CR1); in stm32h7_spi_disable()
742 spi->base + STM32H7_SPI_SR, in stm32h7_spi_disable()
745 dev_warn(spi->dev, in stm32h7_spi_disable()
750 if (!spi->cur_usedma && spi->rx_buf && (spi->rx_len > 0)) in stm32h7_spi_disable()
753 if (spi->cur_usedma && spi->dma_tx) in stm32h7_spi_disable()
754 dmaengine_terminate_all(spi->dma_tx); in stm32h7_spi_disable()
755 if (spi->cur_usedma && spi->dma_rx) in stm32h7_spi_disable()
756 dmaengine_terminate_all(spi->dma_rx); in stm32h7_spi_disable()
764 writel_relaxed(0, spi->base + STM32H7_SPI_IER); in stm32h7_spi_disable()
765 writel_relaxed(STM32H7_SPI_IFCR_ALL, spi->base + STM32H7_SPI_IFCR); in stm32h7_spi_disable()
767 spin_unlock_irqrestore(&spi->lock, flags); in stm32h7_spi_disable()
771 * stm32_spi_can_dma - Determine if the transfer is eligible for DMA use
777 * use DMA. Otherwise use DMA for transfer longer than defined DMA min bytes.
786 if (spi->cfg->has_fifo) in stm32_spi_can_dma()
787 dma_size = spi->fifo_size; in stm32_spi_can_dma()
791 dev_dbg(spi->dev, "%s: %s\n", __func__, in stm32_spi_can_dma()
792 (transfer->len > dma_size) ? "true" : "false"); in stm32_spi_can_dma()
794 return (transfer->len > dma_size); in stm32_spi_can_dma()
798 * stm32f4_spi_irq_event - Interrupt handler for SPI controller events
809 spin_lock(&spi->lock); in stm32f4_spi_irq_event()
811 sr = readl_relaxed(spi->base + STM32F4_SPI_SR); in stm32f4_spi_irq_event()
818 if (!spi->cur_usedma && (spi->cur_comm == SPI_SIMPLEX_TX || in stm32f4_spi_irq_event()
819 spi->cur_comm == SPI_3WIRE_TX)) { in stm32f4_spi_irq_event()
825 if (!spi->cur_usedma && (spi->cur_comm == SPI_FULL_DUPLEX || in stm32f4_spi_irq_event()
826 spi->cur_comm == SPI_SIMPLEX_RX || in stm32f4_spi_irq_event()
827 spi->cur_comm == SPI_3WIRE_RX)) { in stm32f4_spi_irq_event()
834 dev_dbg(spi->dev, "spurious IT (sr=0x%08x)\n", sr); in stm32f4_spi_irq_event()
835 spin_unlock(&spi->lock); in stm32f4_spi_irq_event()
840 dev_warn(spi->dev, "Overrun: received value discarded\n"); in stm32f4_spi_irq_event()
843 readl_relaxed(spi->base + STM32F4_SPI_DR); in stm32f4_spi_irq_event()
844 readl_relaxed(spi->base + STM32F4_SPI_SR); in stm32f4_spi_irq_event()
856 if (spi->tx_buf) in stm32f4_spi_irq_event()
858 if (spi->tx_len == 0) in stm32f4_spi_irq_event()
864 if (spi->rx_len == 0) in stm32f4_spi_irq_event()
866 else if (spi->tx_buf)/* Load data for discontinuous mode */ in stm32f4_spi_irq_event()
877 spin_unlock(&spi->lock); in stm32f4_spi_irq_event()
881 spin_unlock(&spi->lock); in stm32f4_spi_irq_event()
886 * stm32f4_spi_irq_thread - Thread of interrupt handler for SPI controller
902 * stm32h7_spi_irq_thread - Thread of interrupt handler for SPI controller
914 spin_lock_irqsave(&spi->lock, flags); in stm32h7_spi_irq_thread()
916 sr = readl_relaxed(spi->base + STM32H7_SPI_SR); in stm32h7_spi_irq_thread()
917 ier = readl_relaxed(spi->base + STM32H7_SPI_IER); in stm32h7_spi_irq_thread()
924 * Full-Duplex, need to poll RXP event to know if there are remaining in stm32h7_spi_irq_thread()
927 if (spi->rx_buf && !spi->cur_usedma) in stm32h7_spi_irq_thread()
931 dev_dbg(spi->dev, "spurious IT (sr=0x%08x, ier=0x%08x)\n", in stm32h7_spi_irq_thread()
933 spin_unlock_irqrestore(&spi->lock, flags); in stm32h7_spi_irq_thread()
942 dev_dbg_ratelimited(spi->dev, "Communication suspended\n"); in stm32h7_spi_irq_thread()
943 if (!spi->cur_usedma && (spi->rx_buf && (spi->rx_len > 0))) in stm32h7_spi_irq_thread()
946 * If communication is suspended while using DMA, it means in stm32h7_spi_irq_thread()
949 if (spi->cur_usedma) in stm32h7_spi_irq_thread()
954 dev_warn(spi->dev, "Mode fault: transfer aborted\n"); in stm32h7_spi_irq_thread()
959 dev_warn(spi->dev, "Overrun: received value discarded\n"); in stm32h7_spi_irq_thread()
960 if (!spi->cur_usedma && (spi->rx_buf && (spi->rx_len > 0))) in stm32h7_spi_irq_thread()
963 * If overrun is detected while using DMA, it means that in stm32h7_spi_irq_thread()
966 if (spi->cur_usedma) in stm32h7_spi_irq_thread()
971 if (!spi->cur_usedma && (spi->rx_buf && (spi->rx_len > 0))) in stm32h7_spi_irq_thread()
977 if (!spi->cur_usedma && (spi->tx_buf && (spi->tx_len > 0))) in stm32h7_spi_irq_thread()
981 if (!spi->cur_usedma && (spi->rx_buf && (spi->rx_len > 0))) in stm32h7_spi_irq_thread()
984 writel_relaxed(sr & mask, spi->base + STM32H7_SPI_IFCR); in stm32h7_spi_irq_thread()
986 spin_unlock_irqrestore(&spi->lock, flags); in stm32h7_spi_irq_thread()
997 * stm32_spi_prepare_msg - set up the controller to transfer a single message
1005 struct spi_device *spi_dev = msg->spi; in stm32_spi_prepare_msg()
1006 struct device_node *np = spi_dev->dev.of_node; in stm32_spi_prepare_msg()
1011 spi->cur_midi = 0; in stm32_spi_prepare_msg()
1012 if (np && !of_property_read_u32(np, "st,spi-midi-ns", &spi->cur_midi)) in stm32_spi_prepare_msg()
1013 dev_dbg(spi->dev, "%dns inter-data idleness\n", spi->cur_midi); in stm32_spi_prepare_msg()
1015 if (spi_dev->mode & SPI_CPOL) in stm32_spi_prepare_msg()
1016 setb |= spi->cfg->regs->cpol.mask; in stm32_spi_prepare_msg()
1018 clrb |= spi->cfg->regs->cpol.mask; in stm32_spi_prepare_msg()
1020 if (spi_dev->mode & SPI_CPHA) in stm32_spi_prepare_msg()
1021 setb |= spi->cfg->regs->cpha.mask; in stm32_spi_prepare_msg()
1023 clrb |= spi->cfg->regs->cpha.mask; in stm32_spi_prepare_msg()
1025 if (spi_dev->mode & SPI_LSB_FIRST) in stm32_spi_prepare_msg()
1026 setb |= spi->cfg->regs->lsb_first.mask; in stm32_spi_prepare_msg()
1028 clrb |= spi->cfg->regs->lsb_first.mask; in stm32_spi_prepare_msg()
1030 dev_dbg(spi->dev, "cpol=%d cpha=%d lsb_first=%d cs_high=%d\n", in stm32_spi_prepare_msg()
1031 spi_dev->mode & SPI_CPOL, in stm32_spi_prepare_msg()
1032 spi_dev->mode & SPI_CPHA, in stm32_spi_prepare_msg()
1033 spi_dev->mode & SPI_LSB_FIRST, in stm32_spi_prepare_msg()
1034 spi_dev->mode & SPI_CS_HIGH); in stm32_spi_prepare_msg()
1036 spin_lock_irqsave(&spi->lock, flags); in stm32_spi_prepare_msg()
1041 (readl_relaxed(spi->base + spi->cfg->regs->cpol.reg) & in stm32_spi_prepare_msg()
1043 spi->base + spi->cfg->regs->cpol.reg); in stm32_spi_prepare_msg()
1045 spin_unlock_irqrestore(&spi->lock, flags); in stm32_spi_prepare_msg()
1051 * stm32f4_spi_dma_tx_cb - dma callback
1054 * DMA callback is called when the transfer is complete for DMA TX channel.
1060 if (spi->cur_comm == SPI_SIMPLEX_TX || spi->cur_comm == SPI_3WIRE_TX) { in stm32f4_spi_dma_tx_cb()
1061 spi_finalize_current_transfer(spi->master); in stm32f4_spi_dma_tx_cb()
1067 * stm32f4_spi_dma_rx_cb - dma callback
1070 * DMA callback is called when the transfer is complete for DMA RX channel.
1076 spi_finalize_current_transfer(spi->master); in stm32f4_spi_dma_rx_cb()
1081 * stm32h7_spi_dma_cb - dma callback
1084 * DMA callback is called when the transfer is complete or when an error
1093 spin_lock_irqsave(&spi->lock, flags); in stm32h7_spi_dma_cb()
1095 sr = readl_relaxed(spi->base + STM32H7_SPI_SR); in stm32h7_spi_dma_cb()
1097 spin_unlock_irqrestore(&spi->lock, flags); in stm32h7_spi_dma_cb()
1100 dev_warn(spi->dev, "DMA error (sr=0x%08x)\n", sr); in stm32h7_spi_dma_cb()
1106 * stm32_spi_dma_config - configure dma slave channel depending on current
1110 * @dir: direction of the dma transfer
1117 u32 maxburst; in stm32_spi_dma_config() local
1119 if (spi->cur_bpw <= 8) in stm32_spi_dma_config()
1121 else if (spi->cur_bpw <= 16) in stm32_spi_dma_config()
1126 if (spi->cfg->has_fifo) { in stm32_spi_dma_config()
1127 /* Valid for DMA Half or Full Fifo threshold */ in stm32_spi_dma_config()
1128 if (spi->cur_fthlv == 2) in stm32_spi_dma_config()
1129 maxburst = 1; in stm32_spi_dma_config()
1131 maxburst = spi->cur_fthlv; in stm32_spi_dma_config()
1133 maxburst = 1; in stm32_spi_dma_config()
1137 dma_conf->direction = dir; in stm32_spi_dma_config()
1138 if (dma_conf->direction == DMA_DEV_TO_MEM) { /* RX */ in stm32_spi_dma_config()
1139 dma_conf->src_addr = spi->phys_addr + spi->cfg->regs->rx.reg; in stm32_spi_dma_config()
1140 dma_conf->src_addr_width = buswidth; in stm32_spi_dma_config()
1141 dma_conf->src_maxburst = maxburst; in stm32_spi_dma_config()
1143 dev_dbg(spi->dev, "Rx DMA config buswidth=%d, maxburst=%d\n", in stm32_spi_dma_config()
1144 buswidth, maxburst); in stm32_spi_dma_config()
1145 } else if (dma_conf->direction == DMA_MEM_TO_DEV) { /* TX */ in stm32_spi_dma_config()
1146 dma_conf->dst_addr = spi->phys_addr + spi->cfg->regs->tx.reg; in stm32_spi_dma_config()
1147 dma_conf->dst_addr_width = buswidth; in stm32_spi_dma_config()
1148 dma_conf->dst_maxburst = maxburst; in stm32_spi_dma_config()
1150 dev_dbg(spi->dev, "Tx DMA config buswidth=%d, maxburst=%d\n", in stm32_spi_dma_config()
1151 buswidth, maxburst); in stm32_spi_dma_config()
1156 * stm32f4_spi_transfer_one_irq - transfer a single spi_transfer using
1169 if (spi->cur_comm == SPI_SIMPLEX_TX || spi->cur_comm == SPI_3WIRE_TX) { in stm32f4_spi_transfer_one_irq()
1171 } else if (spi->cur_comm == SPI_FULL_DUPLEX || in stm32f4_spi_transfer_one_irq()
1172 spi->cur_comm == SPI_SIMPLEX_RX || in stm32f4_spi_transfer_one_irq()
1173 spi->cur_comm == SPI_3WIRE_RX) { in stm32f4_spi_transfer_one_irq()
1174 /* In transmit-only mode, the OVR flag is set in the SR register in stm32f4_spi_transfer_one_irq()
1180 return -EINVAL; in stm32f4_spi_transfer_one_irq()
1183 spin_lock_irqsave(&spi->lock, flags); in stm32f4_spi_transfer_one_irq()
1190 if (spi->tx_buf) in stm32f4_spi_transfer_one_irq()
1193 spin_unlock_irqrestore(&spi->lock, flags); in stm32f4_spi_transfer_one_irq()
1199 * stm32h7_spi_transfer_one_irq - transfer a single spi_transfer using
1212 if (spi->tx_buf && spi->rx_buf) /* Full Duplex */ in stm32h7_spi_transfer_one_irq()
1214 else if (spi->tx_buf) /* Half-Duplex TX dir or Simplex TX */ in stm32h7_spi_transfer_one_irq()
1216 else if (spi->rx_buf) /* Half-Duplex RX dir or Simplex RX */ in stm32h7_spi_transfer_one_irq()
1223 spin_lock_irqsave(&spi->lock, flags); in stm32h7_spi_transfer_one_irq()
1228 if (spi->tx_buf) in stm32h7_spi_transfer_one_irq()
1233 writel_relaxed(ier, spi->base + STM32H7_SPI_IER); in stm32h7_spi_transfer_one_irq()
1235 spin_unlock_irqrestore(&spi->lock, flags); in stm32h7_spi_transfer_one_irq()
1241 * stm32f4_spi_transfer_one_dma_start - Set SPI driver registers to start
1242 * transfer using DMA
1247 /* In DMA mode end of transfer is handled by DMA TX or RX callback. */ in stm32f4_spi_transfer_one_dma_start()
1248 if (spi->cur_comm == SPI_SIMPLEX_RX || spi->cur_comm == SPI_3WIRE_RX || in stm32f4_spi_transfer_one_dma_start()
1249 spi->cur_comm == SPI_FULL_DUPLEX) { in stm32f4_spi_transfer_one_dma_start()
1251 * In transmit-only mode, the OVR flag is set in the SR register in stm32f4_spi_transfer_one_dma_start()
1262 * stm32h7_spi_transfer_one_dma_start - Set SPI driver registers to start
1263 * transfer using DMA
1280 * stm32_spi_transfer_one_dma - transfer a single spi_transfer using DMA
1294 spin_lock_irqsave(&spi->lock, flags); in stm32_spi_transfer_one_dma()
1297 if (spi->rx_buf && spi->dma_rx) { in stm32_spi_transfer_one_dma()
1299 dmaengine_slave_config(spi->dma_rx, &rx_dma_conf); in stm32_spi_transfer_one_dma()
1301 /* Enable Rx DMA request */ in stm32_spi_transfer_one_dma()
1302 stm32_spi_set_bits(spi, spi->cfg->regs->dma_rx_en.reg, in stm32_spi_transfer_one_dma()
1303 spi->cfg->regs->dma_rx_en.mask); in stm32_spi_transfer_one_dma()
1306 spi->dma_rx, xfer->rx_sg.sgl, in stm32_spi_transfer_one_dma()
1307 xfer->rx_sg.nents, in stm32_spi_transfer_one_dma()
1313 if (spi->tx_buf && spi->dma_tx) { in stm32_spi_transfer_one_dma()
1315 dmaengine_slave_config(spi->dma_tx, &tx_dma_conf); in stm32_spi_transfer_one_dma()
1318 spi->dma_tx, xfer->tx_sg.sgl, in stm32_spi_transfer_one_dma()
1319 xfer->tx_sg.nents, in stm32_spi_transfer_one_dma()
1324 if ((spi->tx_buf && spi->dma_tx && !tx_dma_desc) || in stm32_spi_transfer_one_dma()
1325 (spi->rx_buf && spi->dma_rx && !rx_dma_desc)) in stm32_spi_transfer_one_dma()
1328 if (spi->cur_comm == SPI_FULL_DUPLEX && (!tx_dma_desc || !rx_dma_desc)) in stm32_spi_transfer_one_dma()
1332 rx_dma_desc->callback = spi->cfg->dma_rx_cb; in stm32_spi_transfer_one_dma()
1333 rx_dma_desc->callback_param = spi; in stm32_spi_transfer_one_dma()
1336 dev_err(spi->dev, "Rx DMA submit failed\n"); in stm32_spi_transfer_one_dma()
1339 /* Enable Rx DMA channel */ in stm32_spi_transfer_one_dma()
1340 dma_async_issue_pending(spi->dma_rx); in stm32_spi_transfer_one_dma()
1344 if (spi->cur_comm == SPI_SIMPLEX_TX || in stm32_spi_transfer_one_dma()
1345 spi->cur_comm == SPI_3WIRE_TX) { in stm32_spi_transfer_one_dma()
1346 tx_dma_desc->callback = spi->cfg->dma_tx_cb; in stm32_spi_transfer_one_dma()
1347 tx_dma_desc->callback_param = spi; in stm32_spi_transfer_one_dma()
1351 dev_err(spi->dev, "Tx DMA submit failed\n"); in stm32_spi_transfer_one_dma()
1354 /* Enable Tx DMA channel */ in stm32_spi_transfer_one_dma()
1355 dma_async_issue_pending(spi->dma_tx); in stm32_spi_transfer_one_dma()
1357 /* Enable Tx DMA request */ in stm32_spi_transfer_one_dma()
1358 stm32_spi_set_bits(spi, spi->cfg->regs->dma_tx_en.reg, in stm32_spi_transfer_one_dma()
1359 spi->cfg->regs->dma_tx_en.mask); in stm32_spi_transfer_one_dma()
1362 spi->cfg->transfer_one_dma_start(spi); in stm32_spi_transfer_one_dma()
1364 spin_unlock_irqrestore(&spi->lock, flags); in stm32_spi_transfer_one_dma()
1369 if (spi->dma_rx) in stm32_spi_transfer_one_dma()
1370 dmaengine_terminate_all(spi->dma_rx); in stm32_spi_transfer_one_dma()
1373 stm32_spi_clr_bits(spi, spi->cfg->regs->dma_rx_en.reg, in stm32_spi_transfer_one_dma()
1374 spi->cfg->regs->dma_rx_en.mask); in stm32_spi_transfer_one_dma()
1376 spin_unlock_irqrestore(&spi->lock, flags); in stm32_spi_transfer_one_dma()
1378 dev_info(spi->dev, "DMA issue: fall back to irq transfer\n"); in stm32_spi_transfer_one_dma()
1380 spi->cur_usedma = false; in stm32_spi_transfer_one_dma()
1381 return spi->cfg->transfer_one_irq(spi); in stm32_spi_transfer_one_dma()
1385 * stm32f4_spi_set_bpw - Configure bits per word
1390 if (spi->cur_bpw == 16) in stm32f4_spi_set_bpw()
1397 * stm32h7_spi_set_bpw - configure bits per word
1405 bpw = spi->cur_bpw - 1; in stm32h7_spi_set_bpw()
1411 spi->cur_fthlv = stm32h7_spi_prepare_fthlv(spi, spi->cur_xferlen); in stm32h7_spi_set_bpw()
1412 fthlv = spi->cur_fthlv - 1; in stm32h7_spi_set_bpw()
1419 (readl_relaxed(spi->base + STM32H7_SPI_CFG1) & in stm32h7_spi_set_bpw()
1421 spi->base + STM32H7_SPI_CFG1); in stm32h7_spi_set_bpw()
1425 * stm32_spi_set_mbr - Configure baud rate divisor in master mode
1433 clrb |= spi->cfg->regs->br.mask; in stm32_spi_set_mbr()
1434 setb |= ((u32)mbrdiv << spi->cfg->regs->br.shift) & in stm32_spi_set_mbr()
1435 spi->cfg->regs->br.mask; in stm32_spi_set_mbr()
1437 writel_relaxed((readl_relaxed(spi->base + spi->cfg->regs->br.reg) & in stm32_spi_set_mbr()
1439 spi->base + spi->cfg->regs->br.reg); in stm32_spi_set_mbr()
1443 * stm32_spi_communication_type - return transfer communication type
1452 if (spi_dev->mode & SPI_3WIRE) { /* MISO/MOSI signals shared */ in stm32_spi_communication_type()
1454 * SPI_3WIRE and xfer->tx_buf != NULL and xfer->rx_buf != NULL in stm32_spi_communication_type()
1459 if (!transfer->tx_buf) in stm32_spi_communication_type()
1464 if (!transfer->tx_buf) in stm32_spi_communication_type()
1466 else if (!transfer->rx_buf) in stm32_spi_communication_type()
1474 * stm32f4_spi_set_mode - configure communication mode
1495 return -EINVAL; in stm32f4_spi_set_mode()
1502 * stm32h7_spi_set_mode - configure communication mode
1530 (readl_relaxed(spi->base + STM32H7_SPI_CFG2) & in stm32h7_spi_set_mode()
1532 spi->base + STM32H7_SPI_CFG2); in stm32h7_spi_set_mode()
1538 * stm32h7_spi_data_idleness - configure minimum time delay inserted between two
1548 if ((len > 1) && (spi->cur_midi > 0)) { in stm32h7_spi_data_idleness()
1549 u32 sck_period_ns = DIV_ROUND_UP(SPI_1HZ_NS, spi->cur_speed); in stm32h7_spi_data_idleness()
1550 u32 midi = min((u32)DIV_ROUND_UP(spi->cur_midi, sck_period_ns), in stm32h7_spi_data_idleness()
1554 dev_dbg(spi->dev, "period=%dns, midi=%d(=%dns)\n", in stm32h7_spi_data_idleness()
1560 writel_relaxed((readl_relaxed(spi->base + STM32H7_SPI_CFG2) & in stm32h7_spi_data_idleness()
1562 spi->base + STM32H7_SPI_CFG2); in stm32h7_spi_data_idleness()
1566 * stm32h7_spi_number_of_data - configure number of data at current transfer
1578 writel_relaxed((readl_relaxed(spi->base + STM32H7_SPI_CR2) & in stm32h7_spi_number_of_data()
1580 spi->base + STM32H7_SPI_CR2); in stm32h7_spi_number_of_data()
1582 return -EMSGSIZE; in stm32h7_spi_number_of_data()
1589 * stm32_spi_transfer_one_setup - common setup to transfer a single
1590 * spi_transfer either using DMA or
1605 spin_lock_irqsave(&spi->lock, flags); in stm32_spi_transfer_one_setup()
1607 spi->cur_xferlen = transfer->len; in stm32_spi_transfer_one_setup()
1609 spi->cur_bpw = transfer->bits_per_word; in stm32_spi_transfer_one_setup()
1610 spi->cfg->set_bpw(spi); in stm32_spi_transfer_one_setup()
1612 /* Update spi->cur_speed with real clock speed */ in stm32_spi_transfer_one_setup()
1613 mbr = stm32_spi_prepare_mbr(spi, transfer->speed_hz, in stm32_spi_transfer_one_setup()
1614 spi->cfg->baud_rate_div_min, in stm32_spi_transfer_one_setup()
1615 spi->cfg->baud_rate_div_max); in stm32_spi_transfer_one_setup()
1621 transfer->speed_hz = spi->cur_speed; in stm32_spi_transfer_one_setup()
1625 ret = spi->cfg->set_mode(spi, comm_type); in stm32_spi_transfer_one_setup()
1629 spi->cur_comm = comm_type; in stm32_spi_transfer_one_setup()
1631 if (spi->cfg->set_data_idleness) in stm32_spi_transfer_one_setup()
1632 spi->cfg->set_data_idleness(spi, transfer->len); in stm32_spi_transfer_one_setup()
1634 if (spi->cur_bpw <= 8) in stm32_spi_transfer_one_setup()
1635 nb_words = transfer->len; in stm32_spi_transfer_one_setup()
1636 else if (spi->cur_bpw <= 16) in stm32_spi_transfer_one_setup()
1637 nb_words = DIV_ROUND_UP(transfer->len * 8, 16); in stm32_spi_transfer_one_setup()
1639 nb_words = DIV_ROUND_UP(transfer->len * 8, 32); in stm32_spi_transfer_one_setup()
1641 if (spi->cfg->set_number_of_data) { in stm32_spi_transfer_one_setup()
1642 ret = spi->cfg->set_number_of_data(spi, nb_words); in stm32_spi_transfer_one_setup()
1647 dev_dbg(spi->dev, "transfer communication mode set to %d\n", in stm32_spi_transfer_one_setup()
1648 spi->cur_comm); in stm32_spi_transfer_one_setup()
1649 dev_dbg(spi->dev, in stm32_spi_transfer_one_setup()
1650 "data frame of %d-bit, data packet of %d data frames\n", in stm32_spi_transfer_one_setup()
1651 spi->cur_bpw, spi->cur_fthlv); in stm32_spi_transfer_one_setup()
1652 dev_dbg(spi->dev, "speed set to %dHz\n", spi->cur_speed); in stm32_spi_transfer_one_setup()
1653 dev_dbg(spi->dev, "transfer of %d bytes (%d data frames)\n", in stm32_spi_transfer_one_setup()
1654 spi->cur_xferlen, nb_words); in stm32_spi_transfer_one_setup()
1655 dev_dbg(spi->dev, "dma %s\n", in stm32_spi_transfer_one_setup()
1656 (spi->cur_usedma) ? "enabled" : "disabled"); in stm32_spi_transfer_one_setup()
1659 spin_unlock_irqrestore(&spi->lock, flags); in stm32_spi_transfer_one_setup()
1665 * stm32_spi_transfer_one - transfer a single spi_transfer
1680 spi->tx_buf = transfer->tx_buf; in stm32_spi_transfer_one()
1681 spi->rx_buf = transfer->rx_buf; in stm32_spi_transfer_one()
1682 spi->tx_len = spi->tx_buf ? transfer->len : 0; in stm32_spi_transfer_one()
1683 spi->rx_len = spi->rx_buf ? transfer->len : 0; in stm32_spi_transfer_one()
1685 spi->cur_usedma = (master->can_dma && in stm32_spi_transfer_one()
1686 master->can_dma(master, spi_dev, transfer)); in stm32_spi_transfer_one()
1690 dev_err(spi->dev, "SPI transfer setup failed\n"); in stm32_spi_transfer_one()
1694 if (spi->cur_usedma) in stm32_spi_transfer_one()
1697 return spi->cfg->transfer_one_irq(spi); in stm32_spi_transfer_one()
1701 * stm32_spi_unprepare_msg - relax the hardware
1710 spi->cfg->disable(spi); in stm32_spi_unprepare_msg()
1716 * stm32f4_spi_config - Configure SPI controller as SPI master
1723 spin_lock_irqsave(&spi->lock, flags); in stm32f4_spi_config()
1730 * - SS input value high in stm32f4_spi_config()
1731 * - transmitter half duplex direction in stm32f4_spi_config()
1732 * - Set the master mode (default Motorola mode) in stm32f4_spi_config()
1733 * - Consider 1 master/n slaves configuration and in stm32f4_spi_config()
1741 spin_unlock_irqrestore(&spi->lock, flags); in stm32f4_spi_config()
1747 * stm32h7_spi_config - Configure SPI controller as SPI master
1754 spin_lock_irqsave(&spi->lock, flags); in stm32h7_spi_config()
1761 * - SS input value high in stm32h7_spi_config()
1762 * - transmitter half duplex direction in stm32h7_spi_config()
1763 * - automatic communication suspend when RX-Fifo is full in stm32h7_spi_config()
1770 * - Set the master mode (default Motorola mode) in stm32h7_spi_config()
1771 * - Consider 1 master/n slaves configuration and in stm32h7_spi_config()
1773 * - keep control of all associated GPIOs in stm32h7_spi_config()
1779 spin_unlock_irqrestore(&spi->lock, flags); in stm32h7_spi_config()
1823 { .compatible = "st,stm32h7-spi", .data = (void *)&stm32h7_spi_cfg },
1824 { .compatible = "st,stm32f4-spi", .data = (void *)&stm32f4_spi_cfg },
1836 master = spi_alloc_master(&pdev->dev, sizeof(struct stm32_spi)); in stm32_spi_probe()
1838 dev_err(&pdev->dev, "spi master allocation failed\n"); in stm32_spi_probe()
1839 return -ENOMEM; in stm32_spi_probe()
1844 spi->dev = &pdev->dev; in stm32_spi_probe()
1845 spi->master = master; in stm32_spi_probe()
1846 spin_lock_init(&spi->lock); in stm32_spi_probe()
1848 spi->cfg = (const struct stm32_spi_cfg *) in stm32_spi_probe()
1849 of_match_device(pdev->dev.driver->of_match_table, in stm32_spi_probe()
1850 &pdev->dev)->data; in stm32_spi_probe()
1853 spi->base = devm_ioremap_resource(&pdev->dev, res); in stm32_spi_probe()
1854 if (IS_ERR(spi->base)) { in stm32_spi_probe()
1855 ret = PTR_ERR(spi->base); in stm32_spi_probe()
1859 spi->phys_addr = (dma_addr_t)res->start; in stm32_spi_probe()
1861 spi->irq = platform_get_irq(pdev, 0); in stm32_spi_probe()
1862 if (spi->irq <= 0) { in stm32_spi_probe()
1863 ret = dev_err_probe(&pdev->dev, spi->irq, "failed to get irq\n"); in stm32_spi_probe()
1866 ret = devm_request_threaded_irq(&pdev->dev, spi->irq, in stm32_spi_probe()
1867 spi->cfg->irq_handler_event, in stm32_spi_probe()
1868 spi->cfg->irq_handler_thread, in stm32_spi_probe()
1869 IRQF_ONESHOT, pdev->name, master); in stm32_spi_probe()
1871 dev_err(&pdev->dev, "irq%d request failed: %d\n", spi->irq, in stm32_spi_probe()
1876 spi->clk = devm_clk_get(&pdev->dev, NULL); in stm32_spi_probe()
1877 if (IS_ERR(spi->clk)) { in stm32_spi_probe()
1878 ret = PTR_ERR(spi->clk); in stm32_spi_probe()
1879 dev_err(&pdev->dev, "clk get failed: %d\n", ret); in stm32_spi_probe()
1883 ret = clk_prepare_enable(spi->clk); in stm32_spi_probe()
1885 dev_err(&pdev->dev, "clk enable failed: %d\n", ret); in stm32_spi_probe()
1888 spi->clk_rate = clk_get_rate(spi->clk); in stm32_spi_probe()
1889 if (!spi->clk_rate) { in stm32_spi_probe()
1890 dev_err(&pdev->dev, "clk rate = 0\n"); in stm32_spi_probe()
1891 ret = -EINVAL; in stm32_spi_probe()
1895 spi->rst = devm_reset_control_get_exclusive(&pdev->dev, NULL); in stm32_spi_probe()
1896 if (!IS_ERR(spi->rst)) { in stm32_spi_probe()
1897 reset_control_assert(spi->rst); in stm32_spi_probe()
1899 reset_control_deassert(spi->rst); in stm32_spi_probe()
1902 if (spi->cfg->has_fifo) in stm32_spi_probe()
1903 spi->fifo_size = spi->cfg->get_fifo_size(spi); in stm32_spi_probe()
1905 ret = spi->cfg->config(spi); in stm32_spi_probe()
1907 dev_err(&pdev->dev, "controller configuration failed: %d\n", in stm32_spi_probe()
1912 master->dev.of_node = pdev->dev.of_node; in stm32_spi_probe()
1913 master->auto_runtime_pm = true; in stm32_spi_probe()
1914 master->bus_num = pdev->id; in stm32_spi_probe()
1915 master->mode_bits = SPI_CPHA | SPI_CPOL | SPI_CS_HIGH | SPI_LSB_FIRST | in stm32_spi_probe()
1917 master->bits_per_word_mask = spi->cfg->get_bpw_mask(spi); in stm32_spi_probe()
1918 master->max_speed_hz = spi->clk_rate / spi->cfg->baud_rate_div_min; in stm32_spi_probe()
1919 master->min_speed_hz = spi->clk_rate / spi->cfg->baud_rate_div_max; in stm32_spi_probe()
1920 master->use_gpio_descriptors = true; in stm32_spi_probe()
1921 master->prepare_message = stm32_spi_prepare_msg; in stm32_spi_probe()
1922 master->transfer_one = stm32_spi_transfer_one; in stm32_spi_probe()
1923 master->unprepare_message = stm32_spi_unprepare_msg; in stm32_spi_probe()
1924 master->flags = SPI_MASTER_MUST_TX; in stm32_spi_probe()
1926 spi->dma_tx = dma_request_chan(spi->dev, "tx"); in stm32_spi_probe()
1927 if (IS_ERR(spi->dma_tx)) { in stm32_spi_probe()
1928 ret = PTR_ERR(spi->dma_tx); in stm32_spi_probe()
1929 spi->dma_tx = NULL; in stm32_spi_probe()
1930 if (ret == -EPROBE_DEFER) in stm32_spi_probe()
1933 dev_warn(&pdev->dev, "failed to request tx dma channel\n"); in stm32_spi_probe()
1935 master->dma_tx = spi->dma_tx; in stm32_spi_probe()
1938 spi->dma_rx = dma_request_chan(spi->dev, "rx"); in stm32_spi_probe()
1939 if (IS_ERR(spi->dma_rx)) { in stm32_spi_probe()
1940 ret = PTR_ERR(spi->dma_rx); in stm32_spi_probe()
1941 spi->dma_rx = NULL; in stm32_spi_probe()
1942 if (ret == -EPROBE_DEFER) in stm32_spi_probe()
1945 dev_warn(&pdev->dev, "failed to request rx dma channel\n"); in stm32_spi_probe()
1947 master->dma_rx = spi->dma_rx; in stm32_spi_probe()
1950 if (spi->dma_tx || spi->dma_rx) in stm32_spi_probe()
1951 master->can_dma = stm32_spi_can_dma; in stm32_spi_probe()
1953 pm_runtime_set_active(&pdev->dev); in stm32_spi_probe()
1954 pm_runtime_enable(&pdev->dev); in stm32_spi_probe()
1956 ret = devm_spi_register_master(&pdev->dev, master); in stm32_spi_probe()
1958 dev_err(&pdev->dev, "spi master registration failed: %d\n", in stm32_spi_probe()
1963 if (!master->cs_gpiods) { in stm32_spi_probe()
1964 dev_err(&pdev->dev, "no CS gpios available\n"); in stm32_spi_probe()
1965 ret = -EINVAL; in stm32_spi_probe()
1969 dev_info(&pdev->dev, "driver initialized\n"); in stm32_spi_probe()
1974 pm_runtime_disable(&pdev->dev); in stm32_spi_probe()
1976 if (spi->dma_tx) in stm32_spi_probe()
1977 dma_release_channel(spi->dma_tx); in stm32_spi_probe()
1978 if (spi->dma_rx) in stm32_spi_probe()
1979 dma_release_channel(spi->dma_rx); in stm32_spi_probe()
1981 clk_disable_unprepare(spi->clk); in stm32_spi_probe()
1993 spi->cfg->disable(spi); in stm32_spi_remove()
1995 if (master->dma_tx) in stm32_spi_remove()
1996 dma_release_channel(master->dma_tx); in stm32_spi_remove()
1997 if (master->dma_rx) in stm32_spi_remove()
1998 dma_release_channel(master->dma_rx); in stm32_spi_remove()
2000 clk_disable_unprepare(spi->clk); in stm32_spi_remove()
2002 pm_runtime_disable(&pdev->dev); in stm32_spi_remove()
2004 pinctrl_pm_select_sleep_state(&pdev->dev); in stm32_spi_remove()
2015 clk_disable_unprepare(spi->clk); in stm32_spi_runtime_suspend()
2030 return clk_prepare_enable(spi->clk); in stm32_spi_runtime_resume()
2059 clk_disable_unprepare(spi->clk); in stm32_spi_resume()
2069 spi->cfg->config(spi); in stm32_spi_resume()