Lines Matching +full:cs +full:- +full:x
1 // SPDX-License-Identifier: GPL-2.0-or-later
15 #include <linux/dma-mapping.h>
30 #include <linux/platform_data/spi-omap2-mcspi.h>
47 /* per-channel banks, 0x14 bytes each, first is: */
54 /* per-register bitmasks: */
90 /* We have 2 DMA channels per CS, one for RX and one for TX */
115 struct list_head cs; member
149 writel_relaxed(val, mcspi->base + idx); in mcspi_write_reg()
156 return readl_relaxed(mcspi->base + idx); in mcspi_read_reg()
162 struct omap2_mcspi_cs *cs = spi->controller_state; in mcspi_write_cs_reg() local
164 writel_relaxed(val, cs->base + idx); in mcspi_write_cs_reg()
169 struct omap2_mcspi_cs *cs = spi->controller_state; in mcspi_read_cs_reg() local
171 return readl_relaxed(cs->base + idx); in mcspi_read_cs_reg()
176 struct omap2_mcspi_cs *cs = spi->controller_state; in mcspi_cached_chconf0() local
178 return cs->chconf0; in mcspi_cached_chconf0()
183 struct omap2_mcspi_cs *cs = spi->controller_state; in mcspi_write_chconf0() local
185 cs->chconf0 = val; in mcspi_write_chconf0()
222 struct omap2_mcspi_cs *cs = spi->controller_state; in omap2_mcspi_set_enable() local
225 l = cs->chctrl0; in omap2_mcspi_set_enable()
230 cs->chctrl0 = l; in omap2_mcspi_set_enable()
231 mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCTRL0, cs->chctrl0); in omap2_mcspi_set_enable()
232 /* Flash post-writes */ in omap2_mcspi_set_enable()
238 struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master); in omap2_mcspi_set_cs()
245 if (spi->mode & SPI_CS_HIGH) in omap2_mcspi_set_cs()
248 if (spi->controller_state) { in omap2_mcspi_set_cs()
249 int err = pm_runtime_get_sync(mcspi->dev); in omap2_mcspi_set_cs()
251 pm_runtime_put_noidle(mcspi->dev); in omap2_mcspi_set_cs()
252 dev_err(mcspi->dev, "failed to get sync: %d\n", err); in omap2_mcspi_set_cs()
265 pm_runtime_mark_last_busy(mcspi->dev); in omap2_mcspi_set_cs()
266 pm_runtime_put_autosuspend(mcspi->dev); in omap2_mcspi_set_cs()
273 struct omap2_mcspi_regs *ctx = &mcspi->ctx; in omap2_mcspi_set_mode()
289 ctx->modulctrl = l; in omap2_mcspi_set_mode()
295 struct spi_master *master = spi->master; in omap2_mcspi_set_fifo()
296 struct omap2_mcspi_cs *cs = spi->controller_state; in omap2_mcspi_set_fifo() local
306 bytes_per_word = mcspi_bytes_per_word(cs->word_len); in omap2_mcspi_set_fifo()
307 if (t->len % bytes_per_word != 0) in omap2_mcspi_set_fifo()
310 if (t->rx_buf != NULL && t->tx_buf != NULL) in omap2_mcspi_set_fifo()
315 wcnt = t->len / bytes_per_word; in omap2_mcspi_set_fifo()
320 if (t->rx_buf != NULL) { in omap2_mcspi_set_fifo()
322 xferlevel |= (bytes_per_word - 1) << 8; in omap2_mcspi_set_fifo()
325 if (t->tx_buf != NULL) { in omap2_mcspi_set_fifo()
327 xferlevel |= bytes_per_word - 1; in omap2_mcspi_set_fifo()
332 mcspi->fifo_depth = max_fifo_depth; in omap2_mcspi_set_fifo()
338 if (t->rx_buf != NULL) in omap2_mcspi_set_fifo()
341 if (t->tx_buf != NULL) in omap2_mcspi_set_fifo()
345 mcspi->fifo_depth = 0; in omap2_mcspi_set_fifo()
356 return -ETIMEDOUT; in mcspi_wait_for_reg_bit()
366 struct completion *x) in mcspi_wait_for_completion() argument
368 if (spi_controller_is_slave(mcspi->master)) { in mcspi_wait_for_completion()
369 if (wait_for_completion_interruptible(x) || in mcspi_wait_for_completion()
370 mcspi->slave_aborted) in mcspi_wait_for_completion()
371 return -EINTR; in mcspi_wait_for_completion()
373 wait_for_completion(x); in mcspi_wait_for_completion()
382 struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master); in omap2_mcspi_rx_callback()
383 struct omap2_mcspi_dma *mcspi_dma = &mcspi->dma_channels[spi->chip_select]; in omap2_mcspi_rx_callback()
388 complete(&mcspi_dma->dma_rx_completion); in omap2_mcspi_rx_callback()
394 struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master); in omap2_mcspi_tx_callback()
395 struct omap2_mcspi_dma *mcspi_dma = &mcspi->dma_channels[spi->chip_select]; in omap2_mcspi_tx_callback()
400 complete(&mcspi_dma->dma_tx_completion); in omap2_mcspi_tx_callback()
411 mcspi = spi_master_get_devdata(spi->master); in omap2_mcspi_tx_dma()
412 mcspi_dma = &mcspi->dma_channels[spi->chip_select]; in omap2_mcspi_tx_dma()
414 dmaengine_slave_config(mcspi_dma->dma_tx, &cfg); in omap2_mcspi_tx_dma()
416 tx = dmaengine_prep_slave_sg(mcspi_dma->dma_tx, xfer->tx_sg.sgl, in omap2_mcspi_tx_dma()
417 xfer->tx_sg.nents, in omap2_mcspi_tx_dma()
421 tx->callback = omap2_mcspi_tx_callback; in omap2_mcspi_tx_dma()
422 tx->callback_param = spi; in omap2_mcspi_tx_dma()
427 dma_async_issue_pending(mcspi_dma->dma_tx); in omap2_mcspi_tx_dma()
440 int nb_sizes = 0, out_mapped_nents[2], ret, x; in omap2_mcspi_rx_dma() local
445 struct omap2_mcspi_cs *cs = spi->controller_state; in omap2_mcspi_rx_dma() local
446 void __iomem *chstat_reg = cs->base + OMAP2_MCSPI_CHSTAT0; in omap2_mcspi_rx_dma()
449 mcspi = spi_master_get_devdata(spi->master); in omap2_mcspi_rx_dma()
450 mcspi_dma = &mcspi->dma_channels[spi->chip_select]; in omap2_mcspi_rx_dma()
451 count = xfer->len; in omap2_mcspi_rx_dma()
454 * In the "End-of-Transfer Procedure" section for DMA RX in OMAP35x TRM in omap2_mcspi_rx_dma()
458 if (mcspi->fifo_depth == 0) in omap2_mcspi_rx_dma()
461 word_len = cs->word_len; in omap2_mcspi_rx_dma()
472 dmaengine_slave_config(mcspi_dma->dma_rx, &cfg); in omap2_mcspi_rx_dma()
478 if ((l & OMAP2_MCSPI_CHCONF_TURBO) && mcspi->fifo_depth == 0) in omap2_mcspi_rx_dma()
483 sizes[0] = count - transfer_reduction; in omap2_mcspi_rx_dma()
495 ret = sg_split(xfer->rx_sg.sgl, xfer->rx_sg.nents, 0, nb_sizes, in omap2_mcspi_rx_dma()
499 dev_err(&spi->dev, "sg_split failed\n"); in omap2_mcspi_rx_dma()
503 tx = dmaengine_prep_slave_sg(mcspi_dma->dma_rx, sg_out[0], in omap2_mcspi_rx_dma()
507 tx->callback = omap2_mcspi_rx_callback; in omap2_mcspi_rx_dma()
508 tx->callback_param = spi; in omap2_mcspi_rx_dma()
514 dma_async_issue_pending(mcspi_dma->dma_rx); in omap2_mcspi_rx_dma()
517 ret = mcspi_wait_for_completion(mcspi, &mcspi_dma->dma_rx_completion); in omap2_mcspi_rx_dma()
518 if (ret || mcspi->slave_aborted) { in omap2_mcspi_rx_dma()
519 dmaengine_terminate_sync(mcspi_dma->dma_rx); in omap2_mcspi_rx_dma()
524 for (x = 0; x < nb_sizes; x++) in omap2_mcspi_rx_dma()
525 kfree(sg_out[x]); in omap2_mcspi_rx_dma()
527 if (mcspi->fifo_depth > 0) in omap2_mcspi_rx_dma()
536 elements = element_count - 1; in omap2_mcspi_rx_dma()
539 elements--; in omap2_mcspi_rx_dma()
547 ((u8 *)xfer->rx_buf)[elements++] = w; in omap2_mcspi_rx_dma()
549 ((u16 *)xfer->rx_buf)[elements++] = w; in omap2_mcspi_rx_dma()
551 ((u32 *)xfer->rx_buf)[elements++] = w; in omap2_mcspi_rx_dma()
554 dev_err(&spi->dev, "DMA RX penultimate word empty\n"); in omap2_mcspi_rx_dma()
555 count -= (bytes_per_word << 1); in omap2_mcspi_rx_dma()
565 ((u8 *)xfer->rx_buf)[elements] = w; in omap2_mcspi_rx_dma()
567 ((u16 *)xfer->rx_buf)[elements] = w; in omap2_mcspi_rx_dma()
569 ((u32 *)xfer->rx_buf)[elements] = w; in omap2_mcspi_rx_dma()
571 dev_err(&spi->dev, "DMA RX last word empty\n"); in omap2_mcspi_rx_dma()
572 count -= mcspi_bytes_per_word(word_len); in omap2_mcspi_rx_dma()
582 struct omap2_mcspi_cs *cs = spi->controller_state; in omap2_mcspi_txrx_dma() local
594 mcspi = spi_master_get_devdata(spi->master); in omap2_mcspi_txrx_dma()
595 mcspi_dma = &mcspi->dma_channels[spi->chip_select]; in omap2_mcspi_txrx_dma()
597 if (cs->word_len <= 8) { in omap2_mcspi_txrx_dma()
600 } else if (cs->word_len <= 16) { in omap2_mcspi_txrx_dma()
608 count = xfer->len; in omap2_mcspi_txrx_dma()
611 cfg.src_addr = cs->phys + OMAP2_MCSPI_RX0; in omap2_mcspi_txrx_dma()
612 cfg.dst_addr = cs->phys + OMAP2_MCSPI_TX0; in omap2_mcspi_txrx_dma()
618 rx = xfer->rx_buf; in omap2_mcspi_txrx_dma()
619 tx = xfer->tx_buf; in omap2_mcspi_txrx_dma()
621 mcspi->slave_aborted = false; in omap2_mcspi_txrx_dma()
622 reinit_completion(&mcspi_dma->dma_tx_completion); in omap2_mcspi_txrx_dma()
623 reinit_completion(&mcspi_dma->dma_rx_completion); in omap2_mcspi_txrx_dma()
624 reinit_completion(&mcspi->txdone); in omap2_mcspi_txrx_dma()
627 if (spi_controller_is_slave(spi->master)) in omap2_mcspi_txrx_dma()
628 mcspi_write_reg(spi->master, in omap2_mcspi_txrx_dma()
640 ret = mcspi_wait_for_completion(mcspi, &mcspi_dma->dma_tx_completion); in omap2_mcspi_txrx_dma()
641 if (ret || mcspi->slave_aborted) { in omap2_mcspi_txrx_dma()
642 dmaengine_terminate_sync(mcspi_dma->dma_tx); in omap2_mcspi_txrx_dma()
647 if (spi_controller_is_slave(mcspi->master)) { in omap2_mcspi_txrx_dma()
648 ret = mcspi_wait_for_completion(mcspi, &mcspi->txdone); in omap2_mcspi_txrx_dma()
649 if (ret || mcspi->slave_aborted) in omap2_mcspi_txrx_dma()
653 if (mcspi->fifo_depth > 0) { in omap2_mcspi_txrx_dma()
654 irqstat_reg = mcspi->base + OMAP2_MCSPI_IRQSTATUS; in omap2_mcspi_txrx_dma()
658 dev_err(&spi->dev, "EOW timed out\n"); in omap2_mcspi_txrx_dma()
660 mcspi_write_reg(mcspi->master, OMAP2_MCSPI_IRQSTATUS, in omap2_mcspi_txrx_dma()
666 chstat_reg = cs->base + OMAP2_MCSPI_CHSTAT0; in omap2_mcspi_txrx_dma()
667 if (mcspi->fifo_depth > 0) { in omap2_mcspi_txrx_dma()
671 dev_err(&spi->dev, "TXFFE timed out\n"); in omap2_mcspi_txrx_dma()
676 dev_err(&spi->dev, "TXS timed out\n"); in omap2_mcspi_txrx_dma()
681 dev_err(&spi->dev, "EOT timed out\n"); in omap2_mcspi_txrx_dma()
690 struct omap2_mcspi_cs *cs = spi->controller_state; in omap2_mcspi_txrx_pio() local
693 void __iomem *base = cs->base; in omap2_mcspi_txrx_pio()
699 count = xfer->len; in omap2_mcspi_txrx_pio()
701 word_len = cs->word_len; in omap2_mcspi_txrx_pio()
705 /* We store the pre-calculated register addresses on stack to speed in omap2_mcspi_txrx_pio()
718 rx = xfer->rx_buf; in omap2_mcspi_txrx_pio()
719 tx = xfer->tx_buf; in omap2_mcspi_txrx_pio()
722 c -= 1; in omap2_mcspi_txrx_pio()
726 dev_err(&spi->dev, "TXS timed out\n"); in omap2_mcspi_txrx_pio()
729 dev_vdbg(&spi->dev, "write-%d %02x\n", in omap2_mcspi_txrx_pio()
736 dev_err(&spi->dev, "RXS timed out\n"); in omap2_mcspi_txrx_pio()
744 dev_vdbg(&spi->dev, "read-%d %02x\n", in omap2_mcspi_txrx_pio()
745 word_len, *(rx - 1)); in omap2_mcspi_txrx_pio()
748 dev_err(&spi->dev, in omap2_mcspi_txrx_pio()
758 dev_vdbg(&spi->dev, "read-%d %02x\n", in omap2_mcspi_txrx_pio()
759 word_len, *(rx - 1)); in omap2_mcspi_txrx_pio()
766 rx = xfer->rx_buf; in omap2_mcspi_txrx_pio()
767 tx = xfer->tx_buf; in omap2_mcspi_txrx_pio()
769 c -= 2; in omap2_mcspi_txrx_pio()
773 dev_err(&spi->dev, "TXS timed out\n"); in omap2_mcspi_txrx_pio()
776 dev_vdbg(&spi->dev, "write-%d %04x\n", in omap2_mcspi_txrx_pio()
783 dev_err(&spi->dev, "RXS timed out\n"); in omap2_mcspi_txrx_pio()
791 dev_vdbg(&spi->dev, "read-%d %04x\n", in omap2_mcspi_txrx_pio()
792 word_len, *(rx - 1)); in omap2_mcspi_txrx_pio()
795 dev_err(&spi->dev, in omap2_mcspi_txrx_pio()
805 dev_vdbg(&spi->dev, "read-%d %04x\n", in omap2_mcspi_txrx_pio()
806 word_len, *(rx - 1)); in omap2_mcspi_txrx_pio()
813 rx = xfer->rx_buf; in omap2_mcspi_txrx_pio()
814 tx = xfer->tx_buf; in omap2_mcspi_txrx_pio()
816 c -= 4; in omap2_mcspi_txrx_pio()
820 dev_err(&spi->dev, "TXS timed out\n"); in omap2_mcspi_txrx_pio()
823 dev_vdbg(&spi->dev, "write-%d %08x\n", in omap2_mcspi_txrx_pio()
830 dev_err(&spi->dev, "RXS timed out\n"); in omap2_mcspi_txrx_pio()
838 dev_vdbg(&spi->dev, "read-%d %08x\n", in omap2_mcspi_txrx_pio()
839 word_len, *(rx - 1)); in omap2_mcspi_txrx_pio()
842 dev_err(&spi->dev, in omap2_mcspi_txrx_pio()
852 dev_vdbg(&spi->dev, "read-%d %08x\n", in omap2_mcspi_txrx_pio()
853 word_len, *(rx - 1)); in omap2_mcspi_txrx_pio()
859 if (xfer->rx_buf == NULL) { in omap2_mcspi_txrx_pio()
862 dev_err(&spi->dev, "TXS timed out\n"); in omap2_mcspi_txrx_pio()
865 dev_err(&spi->dev, "EOT timed out\n"); in omap2_mcspi_txrx_pio()
875 return count - c; in omap2_mcspi_txrx_pio()
893 struct omap2_mcspi_cs *cs = spi->controller_state; in omap2_mcspi_setup_transfer() local
896 u8 word_len = spi->bits_per_word; in omap2_mcspi_setup_transfer()
897 u32 speed_hz = spi->max_speed_hz; in omap2_mcspi_setup_transfer()
899 mcspi = spi_master_get_devdata(spi->master); in omap2_mcspi_setup_transfer()
901 if (t != NULL && t->bits_per_word) in omap2_mcspi_setup_transfer()
902 word_len = t->bits_per_word; in omap2_mcspi_setup_transfer()
904 cs->word_len = word_len; in omap2_mcspi_setup_transfer()
906 if (t && t->speed_hz) in omap2_mcspi_setup_transfer()
907 speed_hz = t->speed_hz; in omap2_mcspi_setup_transfer()
915 div = (OMAP2_MCSPI_MAX_FREQ + speed_hz - 1) / speed_hz; in omap2_mcspi_setup_transfer()
917 clkd = (div - 1) & 0xf; in omap2_mcspi_setup_transfer()
918 extclk = (div - 1) >> 4; in omap2_mcspi_setup_transfer()
924 /* standard 4-wire master mode: SCK, MOSI/out, MISO/in, nCS in omap2_mcspi_setup_transfer()
927 if (mcspi->pin_dir == MCSPI_PINDIR_D0_IN_D1_OUT) { in omap2_mcspi_setup_transfer()
939 l |= (word_len - 1) << 7; in omap2_mcspi_setup_transfer()
942 if (!(spi->mode & SPI_CS_HIGH)) in omap2_mcspi_setup_transfer()
943 l |= OMAP2_MCSPI_CHCONF_EPOL; /* active-low; normal */ in omap2_mcspi_setup_transfer()
955 cs->chctrl0 &= ~OMAP2_MCSPI_CHCTRL_EXTCLK_MASK; in omap2_mcspi_setup_transfer()
956 cs->chctrl0 |= extclk << 8; in omap2_mcspi_setup_transfer()
957 mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCTRL0, cs->chctrl0); in omap2_mcspi_setup_transfer()
961 if (spi->mode & SPI_CPOL) in omap2_mcspi_setup_transfer()
965 if (spi->mode & SPI_CPHA) in omap2_mcspi_setup_transfer()
972 cs->mode = spi->mode; in omap2_mcspi_setup_transfer()
974 dev_dbg(&spi->dev, "setup: speed %d, sample %s edge, clk %s\n", in omap2_mcspi_setup_transfer()
976 (spi->mode & SPI_CPHA) ? "trailing" : "leading", in omap2_mcspi_setup_transfer()
977 (spi->mode & SPI_CPOL) ? "inverted" : "normal"); in omap2_mcspi_setup_transfer()
991 mcspi_dma->dma_rx = dma_request_chan(mcspi->dev, in omap2_mcspi_request_dma()
992 mcspi_dma->dma_rx_ch_name); in omap2_mcspi_request_dma()
993 if (IS_ERR(mcspi_dma->dma_rx)) { in omap2_mcspi_request_dma()
994 ret = PTR_ERR(mcspi_dma->dma_rx); in omap2_mcspi_request_dma()
995 mcspi_dma->dma_rx = NULL; in omap2_mcspi_request_dma()
999 mcspi_dma->dma_tx = dma_request_chan(mcspi->dev, in omap2_mcspi_request_dma()
1000 mcspi_dma->dma_tx_ch_name); in omap2_mcspi_request_dma()
1001 if (IS_ERR(mcspi_dma->dma_tx)) { in omap2_mcspi_request_dma()
1002 ret = PTR_ERR(mcspi_dma->dma_tx); in omap2_mcspi_request_dma()
1003 mcspi_dma->dma_tx = NULL; in omap2_mcspi_request_dma()
1004 dma_release_channel(mcspi_dma->dma_rx); in omap2_mcspi_request_dma()
1005 mcspi_dma->dma_rx = NULL; in omap2_mcspi_request_dma()
1008 init_completion(&mcspi_dma->dma_rx_completion); in omap2_mcspi_request_dma()
1009 init_completion(&mcspi_dma->dma_tx_completion); in omap2_mcspi_request_dma()
1021 for (i = 0; i < master->num_chipselect; i++) { in omap2_mcspi_release_dma()
1022 mcspi_dma = &mcspi->dma_channels[i]; in omap2_mcspi_release_dma()
1024 if (mcspi_dma->dma_rx) { in omap2_mcspi_release_dma()
1025 dma_release_channel(mcspi_dma->dma_rx); in omap2_mcspi_release_dma()
1026 mcspi_dma->dma_rx = NULL; in omap2_mcspi_release_dma()
1028 if (mcspi_dma->dma_tx) { in omap2_mcspi_release_dma()
1029 dma_release_channel(mcspi_dma->dma_tx); in omap2_mcspi_release_dma()
1030 mcspi_dma->dma_tx = NULL; in omap2_mcspi_release_dma()
1038 struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master); in omap2_mcspi_setup()
1039 struct omap2_mcspi_regs *ctx = &mcspi->ctx; in omap2_mcspi_setup()
1040 struct omap2_mcspi_cs *cs = spi->controller_state; in omap2_mcspi_setup() local
1042 if (!cs) { in omap2_mcspi_setup()
1043 cs = kzalloc(sizeof *cs, GFP_KERNEL); in omap2_mcspi_setup()
1044 if (!cs) in omap2_mcspi_setup()
1045 return -ENOMEM; in omap2_mcspi_setup()
1046 cs->base = mcspi->base + spi->chip_select * 0x14; in omap2_mcspi_setup()
1047 cs->phys = mcspi->phys + spi->chip_select * 0x14; in omap2_mcspi_setup()
1048 cs->mode = 0; in omap2_mcspi_setup()
1049 cs->chconf0 = 0; in omap2_mcspi_setup()
1050 cs->chctrl0 = 0; in omap2_mcspi_setup()
1051 spi->controller_state = cs; in omap2_mcspi_setup()
1053 list_add_tail(&cs->node, &ctx->cs); in omap2_mcspi_setup()
1056 ret = pm_runtime_get_sync(mcspi->dev); in omap2_mcspi_setup()
1058 pm_runtime_put_noidle(mcspi->dev); in omap2_mcspi_setup()
1064 pm_runtime_mark_last_busy(mcspi->dev); in omap2_mcspi_setup()
1065 pm_runtime_put_autosuspend(mcspi->dev); in omap2_mcspi_setup()
1072 struct omap2_mcspi_cs *cs; in omap2_mcspi_cleanup() local
1074 if (spi->controller_state) { in omap2_mcspi_cleanup()
1076 cs = spi->controller_state; in omap2_mcspi_cleanup()
1077 list_del(&cs->node); in omap2_mcspi_cleanup()
1079 kfree(cs); in omap2_mcspi_cleanup()
1088 irqstat = mcspi_read_reg(mcspi->master, OMAP2_MCSPI_IRQSTATUS); in omap2_mcspi_irq_handler()
1093 mcspi_write_reg(mcspi->master, OMAP2_MCSPI_IRQENABLE, 0); in omap2_mcspi_irq_handler()
1095 complete(&mcspi->txdone); in omap2_mcspi_irq_handler()
1103 struct omap2_mcspi_dma *mcspi_dma = mcspi->dma_channels; in omap2_mcspi_slave_abort()
1105 mcspi->slave_aborted = true; in omap2_mcspi_slave_abort()
1106 complete(&mcspi_dma->dma_rx_completion); in omap2_mcspi_slave_abort()
1107 complete(&mcspi_dma->dma_tx_completion); in omap2_mcspi_slave_abort()
1108 complete(&mcspi->txdone); in omap2_mcspi_slave_abort()
1118 /* We only enable one channel at a time -- the one whose message is in omap2_mcspi_transfer_one()
1119 * -- although this controller would gladly in omap2_mcspi_transfer_one()
1122 * chipselect with the FORCE bit ... CS != channel enable. in omap2_mcspi_transfer_one()
1127 struct omap2_mcspi_cs *cs; in omap2_mcspi_transfer_one() local
1134 mcspi_dma = mcspi->dma_channels + spi->chip_select; in omap2_mcspi_transfer_one()
1135 cs = spi->controller_state; in omap2_mcspi_transfer_one()
1136 cd = spi->controller_data; in omap2_mcspi_transfer_one()
1139 * The slave driver could have changed spi->mode in which case in omap2_mcspi_transfer_one()
1140 * it will be different from cs->mode (the current hardware setup). in omap2_mcspi_transfer_one()
1145 if (spi->mode != cs->mode) in omap2_mcspi_transfer_one()
1150 if (spi->cs_gpiod) in omap2_mcspi_transfer_one()
1151 omap2_mcspi_set_cs(spi, spi->mode & SPI_CS_HIGH); in omap2_mcspi_transfer_one()
1154 (t->speed_hz != spi->max_speed_hz) || in omap2_mcspi_transfer_one()
1155 (t->bits_per_word != spi->bits_per_word)) { in omap2_mcspi_transfer_one()
1160 if (t->speed_hz == spi->max_speed_hz && in omap2_mcspi_transfer_one()
1161 t->bits_per_word == spi->bits_per_word) in omap2_mcspi_transfer_one()
1164 if (cd && cd->cs_per_word) { in omap2_mcspi_transfer_one()
1165 chconf = mcspi->ctx.modulctrl; in omap2_mcspi_transfer_one()
1168 mcspi->ctx.modulctrl = in omap2_mcspi_transfer_one()
1176 if (t->tx_buf == NULL) in omap2_mcspi_transfer_one()
1178 else if (t->rx_buf == NULL) in omap2_mcspi_transfer_one()
1181 if (cd && cd->turbo_mode && t->tx_buf == NULL) { in omap2_mcspi_transfer_one()
1183 if (t->len > ((cs->word_len + 7) >> 3)) in omap2_mcspi_transfer_one()
1189 if (t->len) { in omap2_mcspi_transfer_one()
1192 if ((mcspi_dma->dma_rx && mcspi_dma->dma_tx) && in omap2_mcspi_transfer_one()
1193 master->cur_msg_mapped && in omap2_mcspi_transfer_one()
1194 master->can_dma(master, spi, t)) in omap2_mcspi_transfer_one()
1200 if (t->tx_buf == NULL) in omap2_mcspi_transfer_one()
1201 writel_relaxed(0, cs->base in omap2_mcspi_transfer_one()
1204 if ((mcspi_dma->dma_rx && mcspi_dma->dma_tx) && in omap2_mcspi_transfer_one()
1205 master->cur_msg_mapped && in omap2_mcspi_transfer_one()
1206 master->can_dma(master, spi, t)) in omap2_mcspi_transfer_one()
1211 if (count != t->len) { in omap2_mcspi_transfer_one()
1212 status = -EIO; in omap2_mcspi_transfer_one()
1219 if (mcspi->fifo_depth > 0) in omap2_mcspi_transfer_one()
1229 if (cd && cd->cs_per_word) { in omap2_mcspi_transfer_one()
1230 chconf = mcspi->ctx.modulctrl; in omap2_mcspi_transfer_one()
1233 mcspi->ctx.modulctrl = in omap2_mcspi_transfer_one()
1239 if (spi->cs_gpiod) in omap2_mcspi_transfer_one()
1240 omap2_mcspi_set_cs(spi, !(spi->mode & SPI_CS_HIGH)); in omap2_mcspi_transfer_one()
1242 if (mcspi->fifo_depth > 0 && t) in omap2_mcspi_transfer_one()
1252 struct omap2_mcspi_regs *ctx = &mcspi->ctx; in omap2_mcspi_prepare_message()
1253 struct omap2_mcspi_cs *cs; in omap2_mcspi_prepare_message() local
1260 list_for_each_entry(cs, &ctx->cs, node) { in omap2_mcspi_prepare_message()
1261 if (msg->spi->controller_state == cs) in omap2_mcspi_prepare_message()
1264 if ((cs->chconf0 & OMAP2_MCSPI_CHCONF_FORCE)) { in omap2_mcspi_prepare_message()
1265 cs->chconf0 &= ~OMAP2_MCSPI_CHCONF_FORCE; in omap2_mcspi_prepare_message()
1266 writel_relaxed(cs->chconf0, in omap2_mcspi_prepare_message()
1267 cs->base + OMAP2_MCSPI_CHCONF0); in omap2_mcspi_prepare_message()
1268 readl_relaxed(cs->base + OMAP2_MCSPI_CHCONF0); in omap2_mcspi_prepare_message()
1279 struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master); in omap2_mcspi_can_dma()
1281 &mcspi->dma_channels[spi->chip_select]; in omap2_mcspi_can_dma()
1283 if (!mcspi_dma->dma_rx || !mcspi_dma->dma_tx) in omap2_mcspi_can_dma()
1289 master->dma_rx = mcspi_dma->dma_rx; in omap2_mcspi_can_dma()
1290 master->dma_tx = mcspi_dma->dma_tx; in omap2_mcspi_can_dma()
1292 return (xfer->len >= DMA_MIN_BYTES); in omap2_mcspi_can_dma()
1297 struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master); in omap2_mcspi_max_xfer_size()
1299 &mcspi->dma_channels[spi->chip_select]; in omap2_mcspi_max_xfer_size()
1301 if (mcspi->max_xfer_len && mcspi_dma->dma_rx) in omap2_mcspi_max_xfer_size()
1302 return mcspi->max_xfer_len; in omap2_mcspi_max_xfer_size()
1309 struct spi_master *master = mcspi->master; in omap2_mcspi_controller_setup()
1310 struct omap2_mcspi_regs *ctx = &mcspi->ctx; in omap2_mcspi_controller_setup()
1313 ret = pm_runtime_get_sync(mcspi->dev); in omap2_mcspi_controller_setup()
1315 pm_runtime_put_noidle(mcspi->dev); in omap2_mcspi_controller_setup()
1322 ctx->wakeupenable = OMAP2_MCSPI_WAKEUPENABLE_WKEN; in omap2_mcspi_controller_setup()
1325 pm_runtime_mark_last_busy(mcspi->dev); in omap2_mcspi_controller_setup()
1326 pm_runtime_put_autosuspend(mcspi->dev); in omap2_mcspi_controller_setup()
1331 * When SPI wake up from off-mode, CS is in activate state. If it was in
1339 struct omap2_mcspi_regs *ctx = &mcspi->ctx; in omap_mcspi_runtime_resume()
1340 struct omap2_mcspi_cs *cs; in omap_mcspi_runtime_resume() local
1343 mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, ctx->modulctrl); in omap_mcspi_runtime_resume()
1344 mcspi_write_reg(master, OMAP2_MCSPI_WAKEUPENABLE, ctx->wakeupenable); in omap_mcspi_runtime_resume()
1346 list_for_each_entry(cs, &ctx->cs, node) { in omap_mcspi_runtime_resume()
1348 * We need to toggle CS state for OMAP take this in omap_mcspi_runtime_resume()
1351 if ((cs->chconf0 & OMAP2_MCSPI_CHCONF_FORCE) == 0) { in omap_mcspi_runtime_resume()
1352 cs->chconf0 |= OMAP2_MCSPI_CHCONF_FORCE; in omap_mcspi_runtime_resume()
1353 writel_relaxed(cs->chconf0, in omap_mcspi_runtime_resume()
1354 cs->base + OMAP2_MCSPI_CHCONF0); in omap_mcspi_runtime_resume()
1355 cs->chconf0 &= ~OMAP2_MCSPI_CHCONF_FORCE; in omap_mcspi_runtime_resume()
1356 writel_relaxed(cs->chconf0, in omap_mcspi_runtime_resume()
1357 cs->base + OMAP2_MCSPI_CHCONF0); in omap_mcspi_runtime_resume()
1359 writel_relaxed(cs->chconf0, in omap_mcspi_runtime_resume()
1360 cs->base + OMAP2_MCSPI_CHCONF0); in omap_mcspi_runtime_resume()
1377 .max_xfer_len = SZ_4K - 1,
1382 .compatible = "ti,omap2-mcspi",
1386 .compatible = "ti,omap4-mcspi",
1390 .compatible = "ti,am654-mcspi",
1405 struct device_node *node = pdev->dev.of_node; in omap2_mcspi_probe()
1408 if (of_property_read_bool(node, "spi-slave")) in omap2_mcspi_probe()
1409 master = spi_alloc_slave(&pdev->dev, sizeof(*mcspi)); in omap2_mcspi_probe()
1411 master = spi_alloc_master(&pdev->dev, sizeof(*mcspi)); in omap2_mcspi_probe()
1413 return -ENOMEM; in omap2_mcspi_probe()
1415 /* the spi->mode bits understood by this driver: */ in omap2_mcspi_probe()
1416 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; in omap2_mcspi_probe()
1417 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32); in omap2_mcspi_probe()
1418 master->setup = omap2_mcspi_setup; in omap2_mcspi_probe()
1419 master->auto_runtime_pm = true; in omap2_mcspi_probe()
1420 master->prepare_message = omap2_mcspi_prepare_message; in omap2_mcspi_probe()
1421 master->can_dma = omap2_mcspi_can_dma; in omap2_mcspi_probe()
1422 master->transfer_one = omap2_mcspi_transfer_one; in omap2_mcspi_probe()
1423 master->set_cs = omap2_mcspi_set_cs; in omap2_mcspi_probe()
1424 master->cleanup = omap2_mcspi_cleanup; in omap2_mcspi_probe()
1425 master->slave_abort = omap2_mcspi_slave_abort; in omap2_mcspi_probe()
1426 master->dev.of_node = node; in omap2_mcspi_probe()
1427 master->max_speed_hz = OMAP2_MCSPI_MAX_FREQ; in omap2_mcspi_probe()
1428 master->min_speed_hz = OMAP2_MCSPI_MAX_FREQ >> 15; in omap2_mcspi_probe()
1429 master->use_gpio_descriptors = true; in omap2_mcspi_probe()
1434 mcspi->master = master; in omap2_mcspi_probe()
1436 match = of_match_device(omap_mcspi_of_match, &pdev->dev); in omap2_mcspi_probe()
1439 pdata = match->data; in omap2_mcspi_probe()
1441 of_property_read_u32(node, "ti,spi-num-cs", &num_cs); in omap2_mcspi_probe()
1442 master->num_chipselect = num_cs; in omap2_mcspi_probe()
1443 if (of_get_property(node, "ti,pindir-d0-out-d1-in", NULL)) in omap2_mcspi_probe()
1444 mcspi->pin_dir = MCSPI_PINDIR_D0_OUT_D1_IN; in omap2_mcspi_probe()
1446 pdata = dev_get_platdata(&pdev->dev); in omap2_mcspi_probe()
1447 master->num_chipselect = pdata->num_cs; in omap2_mcspi_probe()
1448 mcspi->pin_dir = pdata->pin_dir; in omap2_mcspi_probe()
1450 regs_offset = pdata->regs_offset; in omap2_mcspi_probe()
1451 if (pdata->max_xfer_len) { in omap2_mcspi_probe()
1452 mcspi->max_xfer_len = pdata->max_xfer_len; in omap2_mcspi_probe()
1453 master->max_transfer_size = omap2_mcspi_max_xfer_size; in omap2_mcspi_probe()
1457 mcspi->base = devm_ioremap_resource(&pdev->dev, r); in omap2_mcspi_probe()
1458 if (IS_ERR(mcspi->base)) { in omap2_mcspi_probe()
1459 status = PTR_ERR(mcspi->base); in omap2_mcspi_probe()
1462 mcspi->phys = r->start + regs_offset; in omap2_mcspi_probe()
1463 mcspi->base += regs_offset; in omap2_mcspi_probe()
1465 mcspi->dev = &pdev->dev; in omap2_mcspi_probe()
1467 INIT_LIST_HEAD(&mcspi->ctx.cs); in omap2_mcspi_probe()
1469 mcspi->dma_channels = devm_kcalloc(&pdev->dev, master->num_chipselect, in omap2_mcspi_probe()
1472 if (mcspi->dma_channels == NULL) { in omap2_mcspi_probe()
1473 status = -ENOMEM; in omap2_mcspi_probe()
1477 for (i = 0; i < master->num_chipselect; i++) { in omap2_mcspi_probe()
1478 sprintf(mcspi->dma_channels[i].dma_rx_ch_name, "rx%d", i); in omap2_mcspi_probe()
1479 sprintf(mcspi->dma_channels[i].dma_tx_ch_name, "tx%d", i); in omap2_mcspi_probe()
1482 &mcspi->dma_channels[i]); in omap2_mcspi_probe()
1483 if (status == -EPROBE_DEFER) in omap2_mcspi_probe()
1488 if (status == -EPROBE_DEFER) in omap2_mcspi_probe()
1491 dev_err(&pdev->dev, "no irq resource found\n"); in omap2_mcspi_probe()
1494 init_completion(&mcspi->txdone); in omap2_mcspi_probe()
1495 status = devm_request_irq(&pdev->dev, status, in omap2_mcspi_probe()
1496 omap2_mcspi_irq_handler, 0, pdev->name, in omap2_mcspi_probe()
1499 dev_err(&pdev->dev, "Cannot request IRQ"); in omap2_mcspi_probe()
1503 pm_runtime_use_autosuspend(&pdev->dev); in omap2_mcspi_probe()
1504 pm_runtime_set_autosuspend_delay(&pdev->dev, SPI_AUTOSUSPEND_TIMEOUT); in omap2_mcspi_probe()
1505 pm_runtime_enable(&pdev->dev); in omap2_mcspi_probe()
1511 status = devm_spi_register_controller(&pdev->dev, master); in omap2_mcspi_probe()
1518 pm_runtime_dont_use_autosuspend(&pdev->dev); in omap2_mcspi_probe()
1519 pm_runtime_put_sync(&pdev->dev); in omap2_mcspi_probe()
1520 pm_runtime_disable(&pdev->dev); in omap2_mcspi_probe()
1534 pm_runtime_dont_use_autosuspend(mcspi->dev); in omap2_mcspi_remove()
1535 pm_runtime_put_sync(mcspi->dev); in omap2_mcspi_remove()
1536 pm_runtime_disable(&pdev->dev); in omap2_mcspi_remove()
1552 dev_warn(mcspi->dev, "%s: failed to set pins: %i\n", in omap2_mcspi_suspend()
1557 dev_warn(mcspi->dev, "%s: master suspend failed: %i\n", in omap2_mcspi_suspend()
1571 dev_warn(mcspi->dev, "%s: failed to set pins: %i\n", in omap2_mcspi_resume()
1576 dev_warn(mcspi->dev, "%s: master resume failed: %i\n", in omap2_mcspi_resume()