Lines Matching +full:spi +full:- +full:lsb +full:- +full:first
1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Freescale SPI controller driver.
10 * CPM SPI and QE buffer descriptors mode support:
19 #include <linux/dma-mapping.h>
33 #include <linux/spi/spi.h>
34 #include <linux/spi/spi_bitbang.h>
45 #include "spi-fsl-lib.h"
46 #include "spi-fsl-cpm.h"
47 #include "spi-fsl-spi.h"
66 .compatible = "fsl,spi",
81 if (dev->of_node) { in fsl_spi_get_type()
82 match = of_match_node(of_fsl_spi_match, dev->of_node); in fsl_spi_get_type()
83 if (match && match->data) in fsl_spi_get_type()
84 return ((struct fsl_spi_match_data *)match->data)->type; in fsl_spi_get_type()
89 static void fsl_spi_change_mode(struct spi_device *spi) in fsl_spi_change_mode() argument
91 struct mpc8xxx_spi *mspi = spi_master_get_devdata(spi->master); in fsl_spi_change_mode()
92 struct spi_mpc8xxx_cs *cs = spi->controller_state; in fsl_spi_change_mode()
93 struct fsl_spi_reg __iomem *reg_base = mspi->reg_base; in fsl_spi_change_mode()
94 __be32 __iomem *mode = ®_base->mode; in fsl_spi_change_mode()
97 if (cs->hw_mode == mpc8xxx_spi_read_reg(mode)) in fsl_spi_change_mode()
100 /* Turn off IRQs locally to minimize time that SPI is disabled. */ in fsl_spi_change_mode()
103 /* Turn off SPI unit prior changing mode */ in fsl_spi_change_mode()
104 mpc8xxx_spi_write_reg(mode, cs->hw_mode & ~SPMODE_ENABLE); in fsl_spi_change_mode()
107 if (mspi->flags & SPI_CPM_MODE) { in fsl_spi_change_mode()
110 mpc8xxx_spi_write_reg(mode, cs->hw_mode); in fsl_spi_change_mode()
114 static void fsl_spi_chipselect(struct spi_device *spi, int value) in fsl_spi_chipselect() argument
116 struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master); in fsl_spi_chipselect()
118 bool pol = spi->mode & SPI_CS_HIGH; in fsl_spi_chipselect()
119 struct spi_mpc8xxx_cs *cs = spi->controller_state; in fsl_spi_chipselect()
121 pdata = spi->dev.parent->parent->platform_data; in fsl_spi_chipselect()
124 if (pdata->cs_control) in fsl_spi_chipselect()
125 pdata->cs_control(spi, !pol); in fsl_spi_chipselect()
129 mpc8xxx_spi->rx_shift = cs->rx_shift; in fsl_spi_chipselect()
130 mpc8xxx_spi->tx_shift = cs->tx_shift; in fsl_spi_chipselect()
131 mpc8xxx_spi->get_rx = cs->get_rx; in fsl_spi_chipselect()
132 mpc8xxx_spi->get_tx = cs->get_tx; in fsl_spi_chipselect()
134 fsl_spi_change_mode(spi); in fsl_spi_chipselect()
136 if (pdata->cs_control) in fsl_spi_chipselect()
137 pdata->cs_control(spi, pol); in fsl_spi_chipselect()
167 *rx_shift = 16; /* LSB in bit 16 */ in fsl_spi_grlib_set_shifts()
168 *tx_shift = 32 - bits_per_word; /* MSB in bit 31 */ in fsl_spi_grlib_set_shifts()
170 *rx_shift = 16 - bits_per_word; /* MSB in bit 15 */ in fsl_spi_grlib_set_shifts()
176 struct spi_device *spi, in mspi_apply_cpu_mode_quirks() argument
180 cs->rx_shift = 0; in mspi_apply_cpu_mode_quirks()
181 cs->tx_shift = 0; in mspi_apply_cpu_mode_quirks()
183 cs->get_rx = mpc8xxx_spi_rx_buf_u8; in mspi_apply_cpu_mode_quirks()
184 cs->get_tx = mpc8xxx_spi_tx_buf_u8; in mspi_apply_cpu_mode_quirks()
186 cs->get_rx = mpc8xxx_spi_rx_buf_u16; in mspi_apply_cpu_mode_quirks()
187 cs->get_tx = mpc8xxx_spi_tx_buf_u16; in mspi_apply_cpu_mode_quirks()
189 cs->get_rx = mpc8xxx_spi_rx_buf_u32; in mspi_apply_cpu_mode_quirks()
190 cs->get_tx = mpc8xxx_spi_tx_buf_u32; in mspi_apply_cpu_mode_quirks()
192 return -EINVAL; in mspi_apply_cpu_mode_quirks()
194 if (mpc8xxx_spi->set_shifts) in mspi_apply_cpu_mode_quirks()
195 mpc8xxx_spi->set_shifts(&cs->rx_shift, &cs->tx_shift, in mspi_apply_cpu_mode_quirks()
197 !(spi->mode & SPI_LSB_FIRST)); in mspi_apply_cpu_mode_quirks()
199 mpc8xxx_spi->rx_shift = cs->rx_shift; in mspi_apply_cpu_mode_quirks()
200 mpc8xxx_spi->tx_shift = cs->tx_shift; in mspi_apply_cpu_mode_quirks()
201 mpc8xxx_spi->get_rx = cs->get_rx; in mspi_apply_cpu_mode_quirks()
202 mpc8xxx_spi->get_tx = cs->get_tx; in mspi_apply_cpu_mode_quirks()
208 struct spi_device *spi, in mspi_apply_qe_mode_quirks() argument
213 * Unfortnatly that doesn't work for LSB so in mspi_apply_qe_mode_quirks()
215 /* Note: 32 bits word, LSB works iff in mspi_apply_qe_mode_quirks()
217 if (spi->mode & SPI_LSB_FIRST && in mspi_apply_qe_mode_quirks()
219 return -EINVAL; in mspi_apply_qe_mode_quirks()
225 static int fsl_spi_setup_transfer(struct spi_device *spi, in fsl_spi_setup_transfer() argument
232 struct spi_mpc8xxx_cs *cs = spi->controller_state; in fsl_spi_setup_transfer()
234 mpc8xxx_spi = spi_master_get_devdata(spi->master); in fsl_spi_setup_transfer()
237 bits_per_word = t->bits_per_word; in fsl_spi_setup_transfer()
238 hz = t->speed_hz; in fsl_spi_setup_transfer()
241 /* spi_transfer level calls that work per-word */ in fsl_spi_setup_transfer()
243 bits_per_word = spi->bits_per_word; in fsl_spi_setup_transfer()
246 hz = spi->max_speed_hz; in fsl_spi_setup_transfer()
248 if (!(mpc8xxx_spi->flags & SPI_CPM_MODE)) in fsl_spi_setup_transfer()
249 bits_per_word = mspi_apply_cpu_mode_quirks(cs, spi, in fsl_spi_setup_transfer()
252 else if (mpc8xxx_spi->flags & SPI_QE) in fsl_spi_setup_transfer()
253 bits_per_word = mspi_apply_qe_mode_quirks(cs, spi, in fsl_spi_setup_transfer()
262 bits_per_word = bits_per_word - 1; in fsl_spi_setup_transfer()
265 cs->hw_mode &= ~(SPMODE_LEN(0xF) | SPMODE_DIV16 in fsl_spi_setup_transfer()
268 cs->hw_mode |= SPMODE_LEN(bits_per_word); in fsl_spi_setup_transfer()
270 if ((mpc8xxx_spi->spibrg / hz) > 64) { in fsl_spi_setup_transfer()
271 cs->hw_mode |= SPMODE_DIV16; in fsl_spi_setup_transfer()
272 pm = (mpc8xxx_spi->spibrg - 1) / (hz * 64) + 1; in fsl_spi_setup_transfer()
275 dev_name(&spi->dev), hz, mpc8xxx_spi->spibrg / 1024); in fsl_spi_setup_transfer()
279 pm = (mpc8xxx_spi->spibrg - 1) / (hz * 4) + 1; in fsl_spi_setup_transfer()
282 pm--; in fsl_spi_setup_transfer()
284 cs->hw_mode |= SPMODE_PM(pm); in fsl_spi_setup_transfer()
286 fsl_spi_change_mode(spi); in fsl_spi_setup_transfer()
294 struct fsl_spi_reg __iomem *reg_base = mspi->reg_base; in fsl_spi_cpu_bufs()
296 mspi->count = len; in fsl_spi_cpu_bufs()
299 mpc8xxx_spi_write_reg(®_base->mask, SPIM_NE); in fsl_spi_cpu_bufs()
302 word = mspi->get_tx(mspi); in fsl_spi_cpu_bufs()
303 mpc8xxx_spi_write_reg(®_base->transmit, word); in fsl_spi_cpu_bufs()
308 static int fsl_spi_bufs(struct spi_device *spi, struct spi_transfer *t, in fsl_spi_bufs() argument
311 struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master); in fsl_spi_bufs()
313 unsigned int len = t->len; in fsl_spi_bufs()
317 reg_base = mpc8xxx_spi->reg_base; in fsl_spi_bufs()
318 bits_per_word = spi->bits_per_word; in fsl_spi_bufs()
319 if (t->bits_per_word) in fsl_spi_bufs()
320 bits_per_word = t->bits_per_word; in fsl_spi_bufs()
325 return -EINVAL; in fsl_spi_bufs()
331 return -EINVAL; in fsl_spi_bufs()
335 mpc8xxx_spi->tx = t->tx_buf; in fsl_spi_bufs()
336 mpc8xxx_spi->rx = t->rx_buf; in fsl_spi_bufs()
338 reinit_completion(&mpc8xxx_spi->done); in fsl_spi_bufs()
340 if (mpc8xxx_spi->flags & SPI_CPM_MODE) in fsl_spi_bufs()
347 wait_for_completion(&mpc8xxx_spi->done); in fsl_spi_bufs()
350 mpc8xxx_spi_write_reg(®_base->mask, 0); in fsl_spi_bufs()
352 if (mpc8xxx_spi->flags & SPI_CPM_MODE) in fsl_spi_bufs()
355 return mpc8xxx_spi->count; in fsl_spi_bufs()
362 struct spi_device *spi = m->spi; in fsl_spi_do_one_msg() local
363 struct spi_transfer *t, *first; in fsl_spi_do_one_msg() local
372 if (!(mpc8xxx_spi->flags & SPI_CPM_MODE)) { in fsl_spi_do_one_msg()
373 list_for_each_entry(t, &m->transfers, transfer_list) { in fsl_spi_do_one_msg()
374 if (t->len < 256 || t->bits_per_word != 8) in fsl_spi_do_one_msg()
376 if ((t->len & 3) == 0) in fsl_spi_do_one_msg()
377 t->bits_per_word = 32; in fsl_spi_do_one_msg()
378 else if ((t->len & 1) == 0) in fsl_spi_do_one_msg()
379 t->bits_per_word = 16; in fsl_spi_do_one_msg()
385 list_for_each_entry(t, &m->transfers, transfer_list) { in fsl_spi_do_one_msg()
387 first = t; in fsl_spi_do_one_msg()
388 cs_change = t->cs_change; in fsl_spi_do_one_msg()
389 if (first->speed_hz != t->speed_hz) { in fsl_spi_do_one_msg()
390 dev_err(&spi->dev, in fsl_spi_do_one_msg()
392 return -EINVAL; in fsl_spi_do_one_msg()
396 last_bpw = -1; in fsl_spi_do_one_msg()
398 status = -EINVAL; in fsl_spi_do_one_msg()
399 list_for_each_entry(t, &m->transfers, transfer_list) { in fsl_spi_do_one_msg()
400 if (cs_change || last_bpw != t->bits_per_word) in fsl_spi_do_one_msg()
401 status = fsl_spi_setup_transfer(spi, t); in fsl_spi_do_one_msg()
404 last_bpw = t->bits_per_word; in fsl_spi_do_one_msg()
407 fsl_spi_chipselect(spi, BITBANG_CS_ACTIVE); in fsl_spi_do_one_msg()
410 cs_change = t->cs_change; in fsl_spi_do_one_msg()
411 if (t->len) in fsl_spi_do_one_msg()
412 status = fsl_spi_bufs(spi, t, m->is_dma_mapped); in fsl_spi_do_one_msg()
414 status = -EMSGSIZE; in fsl_spi_do_one_msg()
417 m->actual_length += t->len; in fsl_spi_do_one_msg()
423 fsl_spi_chipselect(spi, BITBANG_CS_INACTIVE); in fsl_spi_do_one_msg()
428 m->status = status; in fsl_spi_do_one_msg()
432 fsl_spi_chipselect(spi, BITBANG_CS_INACTIVE); in fsl_spi_do_one_msg()
435 fsl_spi_setup_transfer(spi, NULL); in fsl_spi_do_one_msg()
440 static int fsl_spi_setup(struct spi_device *spi) in fsl_spi_setup() argument
446 struct spi_mpc8xxx_cs *cs = spi_get_ctldata(spi); in fsl_spi_setup()
448 if (!spi->max_speed_hz) in fsl_spi_setup()
449 return -EINVAL; in fsl_spi_setup()
454 return -ENOMEM; in fsl_spi_setup()
455 spi_set_ctldata(spi, cs); in fsl_spi_setup()
457 mpc8xxx_spi = spi_master_get_devdata(spi->master); in fsl_spi_setup()
459 reg_base = mpc8xxx_spi->reg_base; in fsl_spi_setup()
461 hw_mode = cs->hw_mode; /* Save original settings */ in fsl_spi_setup()
462 cs->hw_mode = mpc8xxx_spi_read_reg(®_base->mode); in fsl_spi_setup()
464 cs->hw_mode &= ~(SPMODE_CP_BEGIN_EDGECLK | SPMODE_CI_INACTIVEHIGH in fsl_spi_setup()
467 if (spi->mode & SPI_CPHA) in fsl_spi_setup()
468 cs->hw_mode |= SPMODE_CP_BEGIN_EDGECLK; in fsl_spi_setup()
469 if (spi->mode & SPI_CPOL) in fsl_spi_setup()
470 cs->hw_mode |= SPMODE_CI_INACTIVEHIGH; in fsl_spi_setup()
471 if (!(spi->mode & SPI_LSB_FIRST)) in fsl_spi_setup()
472 cs->hw_mode |= SPMODE_REV; in fsl_spi_setup()
473 if (spi->mode & SPI_LOOP) in fsl_spi_setup()
474 cs->hw_mode |= SPMODE_LOOP; in fsl_spi_setup()
476 retval = fsl_spi_setup_transfer(spi, NULL); in fsl_spi_setup()
478 cs->hw_mode = hw_mode; /* Restore settings */ in fsl_spi_setup()
482 /* Initialize chipselect - might be active for SPI_CS_HIGH mode */ in fsl_spi_setup()
483 fsl_spi_chipselect(spi, BITBANG_CS_INACTIVE); in fsl_spi_setup()
488 static void fsl_spi_cleanup(struct spi_device *spi) in fsl_spi_cleanup() argument
490 struct spi_mpc8xxx_cs *cs = spi_get_ctldata(spi); in fsl_spi_cleanup()
493 spi_set_ctldata(spi, NULL); in fsl_spi_cleanup()
498 struct fsl_spi_reg __iomem *reg_base = mspi->reg_base; in fsl_spi_cpu_irq()
500 /* We need handle RX first */ in fsl_spi_cpu_irq()
502 u32 rx_data = mpc8xxx_spi_read_reg(®_base->receive); in fsl_spi_cpu_irq()
504 if (mspi->rx) in fsl_spi_cpu_irq()
505 mspi->get_rx(rx_data, mspi); in fsl_spi_cpu_irq()
511 mpc8xxx_spi_read_reg(®_base->event)) & in fsl_spi_cpu_irq()
516 mpc8xxx_spi_write_reg(®_base->event, events); in fsl_spi_cpu_irq()
518 mspi->count -= 1; in fsl_spi_cpu_irq()
519 if (mspi->count) { in fsl_spi_cpu_irq()
520 u32 word = mspi->get_tx(mspi); in fsl_spi_cpu_irq()
522 mpc8xxx_spi_write_reg(®_base->transmit, word); in fsl_spi_cpu_irq()
524 complete(&mspi->done); in fsl_spi_cpu_irq()
533 struct fsl_spi_reg __iomem *reg_base = mspi->reg_base; in fsl_spi_irq()
536 events = mpc8xxx_spi_read_reg(®_base->event); in fsl_spi_irq()
540 dev_dbg(mspi->dev, "%s: events %x\n", __func__, events); in fsl_spi_irq()
542 if (mspi->flags & SPI_CPM_MODE) in fsl_spi_irq()
550 static void fsl_spi_grlib_cs_control(struct spi_device *spi, bool on) in fsl_spi_grlib_cs_control() argument
552 struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master); in fsl_spi_grlib_cs_control()
553 struct fsl_spi_reg __iomem *reg_base = mpc8xxx_spi->reg_base; in fsl_spi_grlib_cs_control()
555 u16 cs = spi->chip_select; in fsl_spi_grlib_cs_control()
557 if (spi->cs_gpiod) { in fsl_spi_grlib_cs_control()
558 gpiod_set_value(spi->cs_gpiod, on); in fsl_spi_grlib_cs_control()
559 } else if (cs < mpc8xxx_spi->native_chipselects) { in fsl_spi_grlib_cs_control()
560 slvsel = mpc8xxx_spi_read_reg(®_base->slvsel); in fsl_spi_grlib_cs_control()
562 mpc8xxx_spi_write_reg(®_base->slvsel, slvsel); in fsl_spi_grlib_cs_control()
571 struct fsl_spi_reg __iomem *reg_base = mpc8xxx_spi->reg_base; in fsl_spi_grlib_probe()
575 capabilities = mpc8xxx_spi_read_reg(®_base->cap); in fsl_spi_grlib_probe()
577 mpc8xxx_spi->set_shifts = fsl_spi_grlib_set_shifts; in fsl_spi_grlib_probe()
580 mpc8xxx_spi->max_bits_per_word = mbits + 1; in fsl_spi_grlib_probe()
582 mpc8xxx_spi->native_chipselects = 0; in fsl_spi_grlib_probe()
584 mpc8xxx_spi->native_chipselects = SPCAP_SSSZ(capabilities); in fsl_spi_grlib_probe()
585 mpc8xxx_spi_write_reg(®_base->slvsel, 0xffffffff); in fsl_spi_grlib_probe()
587 master->num_chipselect = mpc8xxx_spi->native_chipselects; in fsl_spi_grlib_probe()
588 pdata->cs_control = fsl_spi_grlib_cs_control; in fsl_spi_grlib_probe()
603 ret = -ENOMEM; in fsl_spi_probe()
611 master->setup = fsl_spi_setup; in fsl_spi_probe()
612 master->cleanup = fsl_spi_cleanup; in fsl_spi_probe()
613 master->transfer_one_message = fsl_spi_do_one_msg; in fsl_spi_probe()
614 master->use_gpio_descriptors = true; in fsl_spi_probe()
617 mpc8xxx_spi->max_bits_per_word = 32; in fsl_spi_probe()
618 mpc8xxx_spi->type = fsl_spi_get_type(dev); in fsl_spi_probe()
624 mpc8xxx_spi->reg_base = devm_ioremap_resource(dev, mem); in fsl_spi_probe()
625 if (IS_ERR(mpc8xxx_spi->reg_base)) { in fsl_spi_probe()
626 ret = PTR_ERR(mpc8xxx_spi->reg_base); in fsl_spi_probe()
630 if (mpc8xxx_spi->type == TYPE_GRLIB) in fsl_spi_probe()
633 master->bits_per_word_mask = in fsl_spi_probe()
635 SPI_BPW_RANGE_MASK(1, mpc8xxx_spi->max_bits_per_word); in fsl_spi_probe()
637 if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE) in fsl_spi_probe()
638 mpc8xxx_spi->set_shifts = fsl_spi_qe_cpu_set_shifts; in fsl_spi_probe()
640 if (mpc8xxx_spi->set_shifts) in fsl_spi_probe()
641 /* 8 bits per word and MSB first */ in fsl_spi_probe()
642 mpc8xxx_spi->set_shifts(&mpc8xxx_spi->rx_shift, in fsl_spi_probe()
643 &mpc8xxx_spi->tx_shift, 8, 1); in fsl_spi_probe()
645 /* Register for SPI Interrupt */ in fsl_spi_probe()
646 ret = devm_request_irq(dev, mpc8xxx_spi->irq, fsl_spi_irq, in fsl_spi_probe()
652 reg_base = mpc8xxx_spi->reg_base; in fsl_spi_probe()
654 /* SPI controller initializations */ in fsl_spi_probe()
655 mpc8xxx_spi_write_reg(®_base->mode, 0); in fsl_spi_probe()
656 mpc8xxx_spi_write_reg(®_base->mask, 0); in fsl_spi_probe()
657 mpc8xxx_spi_write_reg(®_base->command, 0); in fsl_spi_probe()
658 mpc8xxx_spi_write_reg(®_base->event, 0xffffffff); in fsl_spi_probe()
660 /* Enable SPI interface */ in fsl_spi_probe()
661 regval = pdata->initial_spmode | SPMODE_INIT_VAL | SPMODE_ENABLE; in fsl_spi_probe()
662 if (mpc8xxx_spi->max_bits_per_word < 8) { in fsl_spi_probe()
664 regval |= SPMODE_LEN(mpc8xxx_spi->max_bits_per_word - 1); in fsl_spi_probe()
666 if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE) in fsl_spi_probe()
669 mpc8xxx_spi_write_reg(®_base->mode, regval); in fsl_spi_probe()
676 mpc8xxx_spi->irq, mpc8xxx_spi_strmode(mpc8xxx_spi->flags)); in fsl_spi_probe()
688 static void fsl_spi_cs_control(struct spi_device *spi, bool on) in fsl_spi_cs_control() argument
690 if (spi->cs_gpiod) { in fsl_spi_cs_control()
691 gpiod_set_value(spi->cs_gpiod, on); in fsl_spi_cs_control()
693 struct device *dev = spi->dev.parent->parent; in fsl_spi_cs_control()
697 if (WARN_ON_ONCE(!pinfo->immr_spi_cs)) in fsl_spi_cs_control()
699 iowrite32be(on ? SPI_BOOT_SEL_BIT : 0, pinfo->immr_spi_cs); in fsl_spi_cs_control()
705 struct device *dev = &ofdev->dev; in of_fsl_spi_probe()
706 struct device_node *np = ofdev->dev.of_node; in of_fsl_spi_probe()
716 type = fsl_spi_get_type(&ofdev->dev); in of_fsl_spi_probe()
724 pinfo->immr_spi_cs = ioremap(get_immrbase() + IMMR_SPI_CS_OFFSET, 4); in of_fsl_spi_probe()
725 if (!pinfo->immr_spi_cs) in of_fsl_spi_probe()
726 return -ENOMEM; in of_fsl_spi_probe()
731 * device on the first "chipselect". Else we let the core code in of_fsl_spi_probe()
738 pdata->max_chipselect = 1; in of_fsl_spi_probe()
740 pdata->cs_control = fsl_spi_cs_control; in of_fsl_spi_probe()
777 * This is "legacy" platform driver, was used by the MPC8323E-RDB boards
778 * only. The driver should go away soon, since newer MPC8323E-RDB's device
788 if (!dev_get_platdata(&pdev->dev)) in plat_mpc8xxx_spi_probe()
789 return -EINVAL; in plat_mpc8xxx_spi_probe()
793 return -EINVAL; in plat_mpc8xxx_spi_probe()
797 return -EINVAL; in plat_mpc8xxx_spi_probe()
799 master = fsl_spi_probe(&pdev->dev, mem, irq); in plat_mpc8xxx_spi_probe()
855 MODULE_DESCRIPTION("Simple Freescale SPI Driver");