Lines Matching +full:cs +full:- +full:out
1 // SPDX-License-Identifier: GPL-2.0-only
3 * Memory-mapped interface driver for DW SPI Core
24 #include "spi-dw.h"
65 struct dw_spi *dws = spi_master_get_devdata(spi->master); in dw_spi_mscc_set_cs()
67 struct dw_spi_mscc *dwsmscc = dwsmmio->priv; in dw_spi_mscc_set_cs()
68 u32 cs = spi->chip_select; in dw_spi_mscc_set_cs() local
70 if (cs < 4) { in dw_spi_mscc_set_cs()
74 sw_mode |= MSCC_SPI_MST_SW_MODE_SW_SPI_CS(BIT(cs)); in dw_spi_mscc_set_cs()
76 writel(sw_mode, dwsmscc->spi_mst + MSCC_SPI_MST_SW_MODE); in dw_spi_mscc_set_cs()
88 dwsmscc = devm_kzalloc(&pdev->dev, sizeof(*dwsmscc), GFP_KERNEL); in dw_spi_mscc_init()
90 return -ENOMEM; in dw_spi_mscc_init()
92 dwsmscc->spi_mst = devm_platform_ioremap_resource(pdev, 1); in dw_spi_mscc_init()
93 if (IS_ERR(dwsmscc->spi_mst)) { in dw_spi_mscc_init()
94 dev_err(&pdev->dev, "SPI_MST region map failed\n"); in dw_spi_mscc_init()
95 return PTR_ERR(dwsmscc->spi_mst); in dw_spi_mscc_init()
98 dwsmscc->syscon = syscon_regmap_lookup_by_compatible(cpu_syscon); in dw_spi_mscc_init()
99 if (IS_ERR(dwsmscc->syscon)) in dw_spi_mscc_init()
100 return PTR_ERR(dwsmscc->syscon); in dw_spi_mscc_init()
102 /* Deassert all CS */ in dw_spi_mscc_init()
103 writel(0, dwsmscc->spi_mst + MSCC_SPI_MST_SW_MODE); in dw_spi_mscc_init()
106 regmap_update_bits(dwsmscc->syscon, MSCC_CPU_SYSTEM_CTRL_GENERAL_CTRL, in dw_spi_mscc_init()
110 dwsmmio->dws.set_cs = dw_spi_mscc_set_cs; in dw_spi_mscc_init()
111 dwsmmio->priv = dwsmscc; in dw_spi_mscc_init()
119 return dw_spi_mscc_init(pdev, dwsmmio, "mscc,ocelot-cpu-syscon", in dw_spi_mscc_ocelot_init()
126 return dw_spi_mscc_init(pdev, dwsmmio, "mscc,jaguar2-cpu-syscon", in dw_spi_mscc_jaguar2_init()
133 * is empty. The chip selects then needs to be driven by a CS override
138 struct dw_spi *dws = spi_master_get_devdata(spi->master); in dw_spi_sparx5_set_cs()
140 struct dw_spi_mscc *dwsmscc = dwsmmio->priv; in dw_spi_sparx5_set_cs()
141 u8 cs = spi->chip_select; in dw_spi_sparx5_set_cs() local
144 /* CS override drive enable */ in dw_spi_sparx5_set_cs()
145 regmap_write(dwsmscc->syscon, SPARX5_FORCE_ENA, 1); in dw_spi_sparx5_set_cs()
147 regmap_write(dwsmscc->syscon, SPARX5_FORCE_VAL, ~BIT(cs)); in dw_spi_sparx5_set_cs()
151 /* CS value */ in dw_spi_sparx5_set_cs()
152 regmap_write(dwsmscc->syscon, SPARX5_FORCE_VAL, ~0); in dw_spi_sparx5_set_cs()
155 /* CS override drive disable */ in dw_spi_sparx5_set_cs()
156 regmap_write(dwsmscc->syscon, SPARX5_FORCE_ENA, 0); in dw_spi_sparx5_set_cs()
165 const char *syscon_name = "microchip,sparx5-cpu-syscon"; in dw_spi_mscc_sparx5_init()
166 struct device *dev = &pdev->dev; in dw_spi_mscc_sparx5_init()
171 return -EOPNOTSUPP; in dw_spi_mscc_sparx5_init()
176 return -ENOMEM; in dw_spi_mscc_sparx5_init()
178 dwsmscc->syscon = in dw_spi_mscc_sparx5_init()
180 if (IS_ERR(dwsmscc->syscon)) { in dw_spi_mscc_sparx5_init()
182 return PTR_ERR(dwsmscc->syscon); in dw_spi_mscc_sparx5_init()
185 dwsmmio->dws.set_cs = dw_spi_sparx5_set_cs; in dw_spi_mscc_sparx5_init()
186 dwsmmio->priv = dwsmscc; in dw_spi_mscc_sparx5_init()
194 dwsmmio->dws.caps = DW_SPI_CAP_CS_OVERRIDE; in dw_spi_alpine_init()
202 dw_spi_dma_setup_generic(&dwsmmio->dws); in dw_spi_dw_apb_init()
210 dwsmmio->dws.caps = DW_SPI_CAP_DWC_SSI; in dw_spi_dwc_ssi_init()
212 dw_spi_dma_setup_generic(&dwsmmio->dws); in dw_spi_dwc_ssi_init()
220 dwsmmio->dws.caps = DW_SPI_CAP_KEEMBAY_MST | DW_SPI_CAP_DWC_SSI; in dw_spi_keembay_init()
235 dwsmmio = devm_kzalloc(&pdev->dev, sizeof(struct dw_spi_mmio), in dw_spi_mmio_probe()
238 return -ENOMEM; in dw_spi_mmio_probe()
240 dws = &dwsmmio->dws; in dw_spi_mmio_probe()
243 dws->regs = devm_platform_get_and_ioremap_resource(pdev, 0, &mem); in dw_spi_mmio_probe()
244 if (IS_ERR(dws->regs)) in dw_spi_mmio_probe()
245 return PTR_ERR(dws->regs); in dw_spi_mmio_probe()
247 dws->paddr = mem->start; in dw_spi_mmio_probe()
249 dws->irq = platform_get_irq(pdev, 0); in dw_spi_mmio_probe()
250 if (dws->irq < 0) in dw_spi_mmio_probe()
251 return dws->irq; /* -ENXIO */ in dw_spi_mmio_probe()
253 dwsmmio->clk = devm_clk_get(&pdev->dev, NULL); in dw_spi_mmio_probe()
254 if (IS_ERR(dwsmmio->clk)) in dw_spi_mmio_probe()
255 return PTR_ERR(dwsmmio->clk); in dw_spi_mmio_probe()
256 ret = clk_prepare_enable(dwsmmio->clk); in dw_spi_mmio_probe()
261 dwsmmio->pclk = devm_clk_get_optional(&pdev->dev, "pclk"); in dw_spi_mmio_probe()
262 if (IS_ERR(dwsmmio->pclk)) { in dw_spi_mmio_probe()
263 ret = PTR_ERR(dwsmmio->pclk); in dw_spi_mmio_probe()
266 ret = clk_prepare_enable(dwsmmio->pclk); in dw_spi_mmio_probe()
271 dwsmmio->rstc = devm_reset_control_get_optional_exclusive(&pdev->dev, "spi"); in dw_spi_mmio_probe()
272 if (IS_ERR(dwsmmio->rstc)) { in dw_spi_mmio_probe()
273 ret = PTR_ERR(dwsmmio->rstc); in dw_spi_mmio_probe()
276 reset_control_deassert(dwsmmio->rstc); in dw_spi_mmio_probe()
278 dws->bus_num = pdev->id; in dw_spi_mmio_probe()
280 dws->max_freq = clk_get_rate(dwsmmio->clk); in dw_spi_mmio_probe()
282 device_property_read_u32(&pdev->dev, "reg-io-width", &dws->reg_io_width); in dw_spi_mmio_probe()
286 device_property_read_u32(&pdev->dev, "num-cs", &num_cs); in dw_spi_mmio_probe()
288 dws->num_cs = num_cs; in dw_spi_mmio_probe()
290 init_func = device_get_match_data(&pdev->dev); in dw_spi_mmio_probe()
294 goto out; in dw_spi_mmio_probe()
297 pm_runtime_enable(&pdev->dev); in dw_spi_mmio_probe()
299 ret = dw_spi_add_host(&pdev->dev, dws); in dw_spi_mmio_probe()
301 goto out; in dw_spi_mmio_probe()
306 out: in dw_spi_mmio_probe()
307 pm_runtime_disable(&pdev->dev); in dw_spi_mmio_probe()
308 clk_disable_unprepare(dwsmmio->pclk); in dw_spi_mmio_probe()
310 clk_disable_unprepare(dwsmmio->clk); in dw_spi_mmio_probe()
311 reset_control_assert(dwsmmio->rstc); in dw_spi_mmio_probe()
320 dw_spi_remove_host(&dwsmmio->dws); in dw_spi_mmio_remove()
321 pm_runtime_disable(&pdev->dev); in dw_spi_mmio_remove()
322 clk_disable_unprepare(dwsmmio->pclk); in dw_spi_mmio_remove()
323 clk_disable_unprepare(dwsmmio->clk); in dw_spi_mmio_remove()
324 reset_control_assert(dwsmmio->rstc); in dw_spi_mmio_remove()
330 { .compatible = "snps,dw-apb-ssi", .data = dw_spi_dw_apb_init},
331 { .compatible = "mscc,ocelot-spi", .data = dw_spi_mscc_ocelot_init},
332 { .compatible = "mscc,jaguar2-spi", .data = dw_spi_mscc_jaguar2_init},
333 { .compatible = "amazon,alpine-dw-apb-ssi", .data = dw_spi_alpine_init},
334 { .compatible = "renesas,rzn1-spi", .data = dw_spi_dw_apb_init},
335 { .compatible = "snps,dwc-ssi-1.01a", .data = dw_spi_dwc_ssi_init},
336 { .compatible = "intel,keembay-ssi", .data = dw_spi_keembay_init},
337 { .compatible = "microchip,sparx5-spi", dw_spi_mscc_sparx5_init},
361 MODULE_AUTHOR("Jean-Hugues Deschenes <jean-hugues.deschenes@octasic.com>");
362 MODULE_DESCRIPTION("Memory-mapped I/O interface driver for DW SPI Core");