Lines Matching +full:rx +full:- +full:fifo +full:- +full:depth
1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <linux/dma-mapping.h>
16 #include <linux/spi/spi-mem.h>
20 #include "spi-dw.h"
29 u32 rx_sample_dly; /* RX sample delay */
63 snprintf(name, 32, "dw_spi%d", dws->master->bus_num); in dw_spi_debugfs_init()
64 dws->debugfs = debugfs_create_dir(name, NULL); in dw_spi_debugfs_init()
65 if (!dws->debugfs) in dw_spi_debugfs_init()
66 return -ENOMEM; in dw_spi_debugfs_init()
68 dws->regset.regs = dw_spi_dbgfs_regs; in dw_spi_debugfs_init()
69 dws->regset.nregs = ARRAY_SIZE(dw_spi_dbgfs_regs); in dw_spi_debugfs_init()
70 dws->regset.base = dws->regs; in dw_spi_debugfs_init()
71 debugfs_create_regset32("registers", 0400, dws->debugfs, &dws->regset); in dw_spi_debugfs_init()
78 debugfs_remove_recursive(dws->debugfs); in dw_spi_debugfs_remove()
94 struct dw_spi *dws = spi_controller_get_devdata(spi->controller); in dw_spi_set_cs()
95 bool cs_high = !!(spi->mode & SPI_CS_HIGH); in dw_spi_set_cs()
102 * support active-high or active-low CS level. in dw_spi_set_cs()
105 dw_writel(dws, DW_SPI_SER, BIT(spi->chip_select)); in dw_spi_set_cs()
111 /* Return the max entries we can fill into tx fifo */
116 tx_room = dws->fifo_len - dw_readl(dws, DW_SPI_TXFLR); in tx_max()
119 * Another concern is about the tx/rx mismatch, we in tx_max()
120 * though to use (dws->fifo_len - rxflr - txflr) as in tx_max()
122 * data which is out of tx/rx fifo and inside the in tx_max()
126 rxtx_gap = dws->fifo_len - (dws->rx_len - dws->tx_len); in tx_max()
128 return min3((u32)dws->tx_len, tx_room, rxtx_gap); in tx_max()
131 /* Return the max entries we should read out of rx fifo */
134 return min_t(u32, dws->rx_len, dw_readl(dws, DW_SPI_RXFLR)); in rx_max()
142 while (max--) { in dw_writer()
143 if (dws->tx) { in dw_writer()
144 if (dws->n_bytes == 1) in dw_writer()
145 txw = *(u8 *)(dws->tx); in dw_writer()
147 txw = *(u16 *)(dws->tx); in dw_writer()
149 dws->tx += dws->n_bytes; in dw_writer()
152 --dws->tx_len; in dw_writer()
161 while (max--) { in dw_reader()
163 if (dws->rx) { in dw_reader()
164 if (dws->n_bytes == 1) in dw_reader()
165 *(u8 *)(dws->rx) = rxw; in dw_reader()
167 *(u16 *)(dws->rx) = rxw; in dw_reader()
169 dws->rx += dws->n_bytes; in dw_reader()
171 --dws->rx_len; in dw_reader()
186 dev_err(&dws->master->dev, "RX FIFO overflow detected\n"); in dw_spi_check_status()
187 ret = -EIO; in dw_spi_check_status()
191 dev_err(&dws->master->dev, "RX FIFO underflow detected\n"); in dw_spi_check_status()
192 ret = -EIO; in dw_spi_check_status()
196 dev_err(&dws->master->dev, "TX FIFO overflow detected\n"); in dw_spi_check_status()
197 ret = -EIO; in dw_spi_check_status()
203 if (dws->master->cur_msg) in dw_spi_check_status()
204 dws->master->cur_msg->status = ret; in dw_spi_check_status()
216 spi_finalize_current_transfer(dws->master); in dw_spi_transfer_handler()
221 * Read data from the Rx FIFO every time we've got a chance executing in dw_spi_transfer_handler()
223 * procedure. Otherwise adjust the Rx FIFO Threshold level if it's a in dw_spi_transfer_handler()
228 if (!dws->rx_len) { in dw_spi_transfer_handler()
230 spi_finalize_current_transfer(dws->master); in dw_spi_transfer_handler()
231 } else if (dws->rx_len <= dw_readl(dws, DW_SPI_RXFTLR)) { in dw_spi_transfer_handler()
232 dw_writel(dws, DW_SPI_RXFTLR, dws->rx_len - 1); in dw_spi_transfer_handler()
236 * Send data out if Tx FIFO Empty IRQ is received. The IRQ will be in dw_spi_transfer_handler()
242 if (!dws->tx_len) in dw_spi_transfer_handler()
258 if (!master->cur_msg) { in dw_spi_irq()
263 return dws->transfer_handler(dws); in dw_spi_irq()
270 if (!(dws->caps & DW_SPI_CAP_DWC_SSI)) { in dw_spi_prepare_cr0()
279 cr0 |= ((spi->mode & SPI_CPOL) ? 1 : 0) << SPI_SCOL_OFFSET; in dw_spi_prepare_cr0()
280 cr0 |= ((spi->mode & SPI_CPHA) ? 1 : 0) << SPI_SCPH_OFFSET; in dw_spi_prepare_cr0()
283 cr0 |= ((spi->mode & SPI_LOOP) ? 1 : 0) << SPI_SRL_OFFSET; in dw_spi_prepare_cr0()
293 cr0 |= ((spi->mode & SPI_CPOL) ? 1 : 0) << DWC_SSI_CTRLR0_SCPOL_OFFSET; in dw_spi_prepare_cr0()
294 cr0 |= ((spi->mode & SPI_CPHA) ? 1 : 0) << DWC_SSI_CTRLR0_SCPH_OFFSET; in dw_spi_prepare_cr0()
297 cr0 |= ((spi->mode & SPI_LOOP) ? 1 : 0) << DWC_SSI_CTRLR0_SRL_OFFSET; in dw_spi_prepare_cr0()
299 if (dws->caps & DW_SPI_CAP_KEEMBAY_MST) in dw_spi_prepare_cr0()
310 u32 cr0 = chip->cr0; in dw_spi_update_config()
315 cr0 |= (cfg->dfs - 1); in dw_spi_update_config()
317 if (!(dws->caps & DW_SPI_CAP_DWC_SSI)) in dw_spi_update_config()
319 cr0 |= cfg->tmode << SPI_TMOD_OFFSET; in dw_spi_update_config()
322 cr0 |= cfg->tmode << DWC_SSI_CTRLR0_TMOD_OFFSET; in dw_spi_update_config()
326 if (cfg->tmode == SPI_TMOD_EPROMREAD || cfg->tmode == SPI_TMOD_RO) in dw_spi_update_config()
327 dw_writel(dws, DW_SPI_CTRLR1, cfg->ndf ? cfg->ndf - 1 : 0); in dw_spi_update_config()
330 clk_div = (DIV_ROUND_UP(dws->max_freq, cfg->freq) + 1) & 0xfffe; in dw_spi_update_config()
331 speed_hz = dws->max_freq / clk_div; in dw_spi_update_config()
333 if (dws->current_freq != speed_hz) { in dw_spi_update_config()
335 dws->current_freq = speed_hz; in dw_spi_update_config()
338 /* Update RX sample delay if required */ in dw_spi_update_config()
339 if (dws->cur_rx_sample_dly != chip->rx_sample_dly) { in dw_spi_update_config()
340 dw_writel(dws, DW_SPI_RX_SAMPLE_DLY, chip->rx_sample_dly); in dw_spi_update_config()
341 dws->cur_rx_sample_dly = chip->rx_sample_dly; in dw_spi_update_config()
352 * Originally Tx and Rx data lengths match. Rx FIFO Threshold level in dw_spi_irq_setup()
353 * will be adjusted at the final stage of the IRQ-based SPI transfer in dw_spi_irq_setup()
356 level = min_t(u16, dws->fifo_len / 2, dws->tx_len); in dw_spi_irq_setup()
358 dw_writel(dws, DW_SPI_RXFTLR, level - 1); in dw_spi_irq_setup()
360 dws->transfer_handler = dw_spi_transfer_handler; in dw_spi_irq_setup()
368 * The iterative procedure of the poll-based transfer is simple: write as much
369 * as possible to the Tx FIFO, wait until the pending to receive data is ready
370 * to be read, read it from the Rx FIFO and check whether the performed
373 * Note this method the same way as the IRQ-based transfer won't work well for
375 * automatic CS assertion/de-assertion.
385 nbits = dws->n_bytes * BITS_PER_BYTE; in dw_spi_poll_transfer()
390 delay.value = nbits * (dws->rx_len - dws->tx_len); in dw_spi_poll_transfer()
398 } while (dws->rx_len); in dw_spi_poll_transfer()
409 .dfs = transfer->bits_per_word, in dw_spi_transfer_one()
410 .freq = transfer->speed_hz, in dw_spi_transfer_one()
414 dws->dma_mapped = 0; in dw_spi_transfer_one()
415 dws->n_bytes = DIV_ROUND_UP(transfer->bits_per_word, BITS_PER_BYTE); in dw_spi_transfer_one()
416 dws->tx = (void *)transfer->tx_buf; in dw_spi_transfer_one()
417 dws->tx_len = transfer->len / dws->n_bytes; in dw_spi_transfer_one()
418 dws->rx = transfer->rx_buf; in dw_spi_transfer_one()
419 dws->rx_len = dws->tx_len; in dw_spi_transfer_one()
428 transfer->effective_speed_hz = dws->current_freq; in dw_spi_transfer_one()
431 if (master->can_dma && master->can_dma(master, spi, transfer)) in dw_spi_transfer_one()
432 dws->dma_mapped = master->cur_msg_mapped; in dw_spi_transfer_one()
437 if (dws->dma_mapped) { in dw_spi_transfer_one()
438 ret = dws->dma_ops->dma_setup(dws, transfer); in dw_spi_transfer_one()
445 if (dws->dma_mapped) in dw_spi_transfer_one()
446 return dws->dma_ops->dma_transfer(dws, transfer); in dw_spi_transfer_one()
447 else if (dws->irq == IRQ_NOTCONNECTED) in dw_spi_transfer_one()
460 if (dws->dma_mapped) in dw_spi_handle_err()
461 dws->dma_ops->dma_stop(dws); in dw_spi_handle_err()
468 if (op->data.dir == SPI_MEM_DATA_IN) in dw_spi_adjust_mem_op_size()
469 op->data.nbytes = clamp_val(op->data.nbytes, 0, SPI_NDF_MASK + 1); in dw_spi_adjust_mem_op_size()
477 if (op->data.buswidth > 1 || op->addr.buswidth > 1 || in dw_spi_supports_mem_op()
478 op->dummy.buswidth > 1 || op->cmd.buswidth > 1) in dw_spi_supports_mem_op()
491 * either use the pre-allocated buffer or create a temporary one. in dw_spi_init_mem_buf()
493 len = op->cmd.nbytes + op->addr.nbytes + op->dummy.nbytes; in dw_spi_init_mem_buf()
494 if (op->data.dir == SPI_MEM_DATA_OUT) in dw_spi_init_mem_buf()
495 len += op->data.nbytes; in dw_spi_init_mem_buf()
498 out = dws->buf; in dw_spi_init_mem_buf()
502 return -ENOMEM; in dw_spi_init_mem_buf()
510 for (i = 0; i < op->cmd.nbytes; ++i) in dw_spi_init_mem_buf()
511 out[i] = SPI_GET_BYTE(op->cmd.opcode, op->cmd.nbytes - i - 1); in dw_spi_init_mem_buf()
512 for (j = 0; j < op->addr.nbytes; ++i, ++j) in dw_spi_init_mem_buf()
513 out[i] = SPI_GET_BYTE(op->addr.val, op->addr.nbytes - j - 1); in dw_spi_init_mem_buf()
514 for (j = 0; j < op->dummy.nbytes; ++i, ++j) in dw_spi_init_mem_buf()
517 if (op->data.dir == SPI_MEM_DATA_OUT) in dw_spi_init_mem_buf()
518 memcpy(&out[i], op->data.buf.out, op->data.nbytes); in dw_spi_init_mem_buf()
520 dws->n_bytes = 1; in dw_spi_init_mem_buf()
521 dws->tx = out; in dw_spi_init_mem_buf()
522 dws->tx_len = len; in dw_spi_init_mem_buf()
523 if (op->data.dir == SPI_MEM_DATA_IN) { in dw_spi_init_mem_buf()
524 dws->rx = op->data.buf.in; in dw_spi_init_mem_buf()
525 dws->rx_len = op->data.nbytes; in dw_spi_init_mem_buf()
527 dws->rx = NULL; in dw_spi_init_mem_buf()
528 dws->rx_len = 0; in dw_spi_init_mem_buf()
536 if (dws->tx != dws->buf) in dw_spi_free_mem_buf()
537 kfree(dws->tx); in dw_spi_free_mem_buf()
547 * At initial stage we just pre-fill the Tx FIFO in with no rush, in dw_spi_write_then_read()
551 len = min(dws->fifo_len, dws->tx_len); in dw_spi_write_then_read()
552 buf = dws->tx; in dw_spi_write_then_read()
553 while (len--) in dw_spi_write_then_read()
559 * otherwise the CS de-assertion will happen whereupon the memory in dw_spi_write_then_read()
560 * operation will be pre-terminated. in dw_spi_write_then_read()
562 len = dws->tx_len - ((void *)buf - dws->tx); in dw_spi_write_then_read()
565 entries = readl_relaxed(dws->regs + DW_SPI_TXFLR); in dw_spi_write_then_read()
567 dev_err(&dws->master->dev, "CS de-assertion on Tx\n"); in dw_spi_write_then_read()
568 return -EIO; in dw_spi_write_then_read()
570 room = min(dws->fifo_len - entries, len); in dw_spi_write_then_read()
571 for (; room; --room, --len) in dw_spi_write_then_read()
576 * Data fetching will start automatically if the EEPROM-read mode is in dw_spi_write_then_read()
578 * prevent the Rx FIFO overflow causing the inbound data loss. in dw_spi_write_then_read()
580 len = dws->rx_len; in dw_spi_write_then_read()
581 buf = dws->rx; in dw_spi_write_then_read()
583 entries = readl_relaxed(dws->regs + DW_SPI_RXFLR); in dw_spi_write_then_read()
585 sts = readl_relaxed(dws->regs + DW_SPI_RISR); in dw_spi_write_then_read()
587 dev_err(&dws->master->dev, "FIFO overflow on Rx\n"); in dw_spi_write_then_read()
588 return -EIO; in dw_spi_write_then_read()
593 for (; entries; --entries, --len) in dw_spi_write_then_read()
613 ns = NSEC_PER_SEC / dws->current_freq * nents; in dw_spi_wait_mem_op_done()
614 ns *= dws->n_bytes * BITS_PER_BYTE; in dw_spi_wait_mem_op_done()
624 while (dw_spi_ctlr_busy(dws) && retry--) in dw_spi_wait_mem_op_done()
628 dev_err(&dws->master->dev, "Mem op hanged up\n"); in dw_spi_wait_mem_op_done()
629 return -EIO; in dw_spi_wait_mem_op_done()
644 * devices, which are selected by the native chip-select lane. It's
645 * specifically developed to workaround the problem with automatic chip-select
646 * lane toggle when there is no data in the Tx FIFO buffer. Luckily the current
647 * SPI-mem core calls exec_op() callback only if the GPIO-based CS is
652 struct dw_spi *dws = spi_controller_get_devdata(mem->spi->controller); in dw_spi_exec_mem_op()
666 * DW SPI EEPROM-read mode is required only for the SPI memory Data-IN in dw_spi_exec_mem_op()
667 * operation. Transmit-only mode is suitable for the rest of them. in dw_spi_exec_mem_op()
670 cfg.freq = clamp(mem->spi->max_speed_hz, 0U, dws->max_mem_freq); in dw_spi_exec_mem_op()
671 if (op->data.dir == SPI_MEM_DATA_IN) { in dw_spi_exec_mem_op()
673 cfg.ndf = op->data.nbytes; in dw_spi_exec_mem_op()
680 dw_spi_update_config(dws, mem->spi, &cfg); in dw_spi_exec_mem_op()
688 * (without any vendor-specific modifications) it doesn't provide a in dw_spi_exec_mem_op()
689 * direct way to set and clear the native chip-select signal. Instead in dw_spi_exec_mem_op()
690 * the controller asserts the CS lane if Tx FIFO isn't empty and a in dw_spi_exec_mem_op()
691 * transmission is going on, and automatically de-asserts it back to in dw_spi_exec_mem_op()
692 * the high level if the Tx FIFO doesn't have anything to be pushed in dw_spi_exec_mem_op()
693 * out. Due to that a multi-tasking or heavy IRQs activity might be in dw_spi_exec_mem_op()
694 * fatal, since the transfer procedure preemption may cause the Tx FIFO in dw_spi_exec_mem_op()
695 * getting empty and sudden CS de-assertion, which in the middle of the in dw_spi_exec_mem_op()
697 * EEPROM-read or Read-only DW SPI transfer modes imply the incoming in dw_spi_exec_mem_op()
698 * data being automatically pulled in into the Rx FIFO. So if the in dw_spi_exec_mem_op()
699 * driver software is late in fetching the data from the FIFO before in dw_spi_exec_mem_op()
701 * sure the executed memory operations are CS-atomic and to prevent the in dw_spi_exec_mem_op()
702 * Rx FIFO overflow we have to disable the local interrupts so to block in dw_spi_exec_mem_op()
706 * the problems described above. The CS de-assertion and Rx FIFO in dw_spi_exec_mem_op()
708 * CPU not working fast enough, so the write-then-read algo implemented in dw_spi_exec_mem_op()
712 * dws->max_mem_freq parameter. in dw_spi_exec_mem_op()
717 ret = dw_spi_write_then_read(dws, mem->spi); in dw_spi_exec_mem_op()
724 * status only if there hasn't been any run-time error detected. In the in dw_spi_exec_mem_op()
735 dw_spi_stop_mem_op(dws, mem->spi); in dw_spi_exec_mem_op()
748 * has fixed the automatic CS assertion/de-assertion peculiarity, then it will
749 * be safer to use the normal SPI-messages-based transfers implementation.
753 if (!dws->mem_ops.exec_op && !(dws->caps & DW_SPI_CAP_CS_OVERRIDE) && in dw_spi_init_mem_ops()
754 !dws->set_cs) { in dw_spi_init_mem_ops()
755 dws->mem_ops.adjust_op_size = dw_spi_adjust_mem_op_size; in dw_spi_init_mem_ops()
756 dws->mem_ops.supports_op = dw_spi_supports_mem_op; in dw_spi_init_mem_ops()
757 dws->mem_ops.exec_op = dw_spi_exec_mem_op; in dw_spi_init_mem_ops()
758 if (!dws->max_mem_freq) in dw_spi_init_mem_ops()
759 dws->max_mem_freq = dws->max_freq; in dw_spi_init_mem_ops()
766 struct dw_spi *dws = spi_controller_get_devdata(spi->controller); in dw_spi_setup()
772 struct dw_spi *dws = spi_controller_get_devdata(spi->controller); in dw_spi_setup()
777 return -ENOMEM; in dw_spi_setup()
779 /* Get specific / default rx-sample-delay */ in dw_spi_setup()
780 if (device_property_read_u32(&spi->dev, in dw_spi_setup()
781 "rx-sample-delay-ns", in dw_spi_setup()
784 rx_sample_dly_ns = dws->def_rx_sample_dly_ns; in dw_spi_setup()
785 chip->rx_sample_dly = DIV_ROUND_CLOSEST(rx_sample_dly_ns, in dw_spi_setup()
787 dws->max_freq); in dw_spi_setup()
795 chip->cr0 = dw_spi_prepare_cr0(dws, spi); in dw_spi_setup()
808 /* Restart the controller, disable all interrupts, clean rx fifo */
814 * Try to detect the FIFO depth if not set by interface driver, in spi_hw_init()
815 * the depth could be from 2 to 256 from HW spec in spi_hw_init()
817 if (!dws->fifo_len) { in spi_hw_init()
818 u32 fifo; in spi_hw_init() local
820 for (fifo = 1; fifo < 256; fifo++) { in spi_hw_init()
821 dw_writel(dws, DW_SPI_TXFTLR, fifo); in spi_hw_init()
822 if (fifo != dw_readl(dws, DW_SPI_TXFTLR)) in spi_hw_init()
827 dws->fifo_len = (fifo == 1) ? 0 : fifo; in spi_hw_init()
828 dev_dbg(dev, "Detected FIFO size: %u bytes\n", dws->fifo_len); in spi_hw_init()
832 if (dws->caps & DW_SPI_CAP_CS_OVERRIDE) in spi_hw_init()
842 return -EINVAL; in dw_spi_add_host()
846 return -ENOMEM; in dw_spi_add_host()
848 dws->master = master; in dw_spi_add_host()
849 dws->dma_addr = (dma_addr_t)(dws->paddr + DW_SPI_DR); in dw_spi_add_host()
856 ret = request_irq(dws->irq, dw_spi_irq, IRQF_SHARED, dev_name(dev), in dw_spi_add_host()
858 if (ret < 0 && ret != -ENOTCONN) { in dw_spi_add_host()
865 master->use_gpio_descriptors = true; in dw_spi_add_host()
866 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LOOP; in dw_spi_add_host()
867 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16); in dw_spi_add_host()
868 master->bus_num = dws->bus_num; in dw_spi_add_host()
869 master->num_chipselect = dws->num_cs; in dw_spi_add_host()
870 master->setup = dw_spi_setup; in dw_spi_add_host()
871 master->cleanup = dw_spi_cleanup; in dw_spi_add_host()
872 if (dws->set_cs) in dw_spi_add_host()
873 master->set_cs = dws->set_cs; in dw_spi_add_host()
875 master->set_cs = dw_spi_set_cs; in dw_spi_add_host()
876 master->transfer_one = dw_spi_transfer_one; in dw_spi_add_host()
877 master->handle_err = dw_spi_handle_err; in dw_spi_add_host()
878 if (dws->mem_ops.exec_op) in dw_spi_add_host()
879 master->mem_ops = &dws->mem_ops; in dw_spi_add_host()
880 master->max_speed_hz = dws->max_freq; in dw_spi_add_host()
881 master->dev.of_node = dev->of_node; in dw_spi_add_host()
882 master->dev.fwnode = dev->fwnode; in dw_spi_add_host()
883 master->flags = SPI_MASTER_GPIO_SS; in dw_spi_add_host()
884 master->auto_runtime_pm = true; in dw_spi_add_host()
886 /* Get default rx sample delay */ in dw_spi_add_host()
887 device_property_read_u32(dev, "rx-sample-delay-ns", in dw_spi_add_host()
888 &dws->def_rx_sample_dly_ns); in dw_spi_add_host()
890 if (dws->dma_ops && dws->dma_ops->dma_init) { in dw_spi_add_host()
891 ret = dws->dma_ops->dma_init(dev, dws); in dw_spi_add_host()
895 master->can_dma = dws->dma_ops->can_dma; in dw_spi_add_host()
896 master->flags |= SPI_CONTROLLER_MUST_TX; in dw_spi_add_host()
902 dev_err(&master->dev, "problem registering spi master\n"); in dw_spi_add_host()
910 if (dws->dma_ops && dws->dma_ops->dma_exit) in dw_spi_add_host()
911 dws->dma_ops->dma_exit(dws); in dw_spi_add_host()
913 free_irq(dws->irq, master); in dw_spi_add_host()
924 spi_unregister_controller(dws->master); in dw_spi_remove_host()
926 if (dws->dma_ops && dws->dma_ops->dma_exit) in dw_spi_remove_host()
927 dws->dma_ops->dma_exit(dws); in dw_spi_remove_host()
931 free_irq(dws->irq, dws->master); in dw_spi_remove_host()
939 ret = spi_controller_suspend(dws->master); in dw_spi_suspend_host()
950 spi_hw_init(&dws->master->dev, dws); in dw_spi_resume_host()
951 return spi_controller_resume(dws->master); in dw_spi_resume_host()