1 // SPDX-License-Identifier: GPL-2.0
56 #define SWRM_DP_PORT_CTRL_BANK(n, m)	(0x1124 + 0x100 * (n - 1) + 0x40 * m)
57 #define SWRM_DP_BLOCK_CTRL3_BANK(n, m)	(0x1138 + 0x100 * (n - 1) + 0x40 * m)
109 	int (*reg_read)(struct qcom_swrm_ctrl *ctrl, int reg, u32 *val);
110 	int (*reg_write)(struct qcom_swrm_ctrl *ctrl, int reg, int val);
130 static int qcom_swrm_ahb_reg_read(struct qcom_swrm_ctrl *ctrl, int reg,  in qcom_swrm_ahb_reg_read()  argument
133 	struct regmap *wcd_regmap = ctrl->regmap;  in qcom_swrm_ahb_reg_read()
150 static int qcom_swrm_ahb_reg_write(struct qcom_swrm_ctrl *ctrl,  in qcom_swrm_ahb_reg_write()  argument
153 	struct regmap *wcd_regmap = ctrl->regmap;  in qcom_swrm_ahb_reg_write()
170 static int qcom_swrm_cpu_reg_read(struct qcom_swrm_ctrl *ctrl, int reg,  in qcom_swrm_cpu_reg_read()  argument
173 	*val = readl(ctrl->mmio + reg);  in qcom_swrm_cpu_reg_read()
177 static int qcom_swrm_cpu_reg_write(struct qcom_swrm_ctrl *ctrl, int reg,  in qcom_swrm_cpu_reg_write()  argument
180 	writel(val, ctrl->mmio + reg);  in qcom_swrm_cpu_reg_write()
184 static int qcom_swrm_cmd_fifo_wr_cmd(struct qcom_swrm_ctrl *ctrl, u8 cmd_data,  in qcom_swrm_cmd_fifo_wr_cmd()  argument
192 	spin_lock_irqsave(&ctrl->comp_lock, flags);  in qcom_swrm_cmd_fifo_wr_cmd()
193 	ctrl->comp = ∁  in qcom_swrm_cmd_fifo_wr_cmd()
194 	spin_unlock_irqrestore(&ctrl->comp_lock, flags);  in qcom_swrm_cmd_fifo_wr_cmd()
197 	ret = ctrl->reg_write(ctrl, SWRM_CMD_FIFO_WR_CMD, val);  in qcom_swrm_cmd_fifo_wr_cmd()
201 	ret = wait_for_completion_timeout(ctrl->comp,  in qcom_swrm_cmd_fifo_wr_cmd()
209 	spin_lock_irqsave(&ctrl->comp_lock, flags);  in qcom_swrm_cmd_fifo_wr_cmd()
210 	ctrl->comp = NULL;  in qcom_swrm_cmd_fifo_wr_cmd()
211 	spin_unlock_irqrestore(&ctrl->comp_lock, flags);  in qcom_swrm_cmd_fifo_wr_cmd()
216 static int qcom_swrm_cmd_fifo_rd_cmd(struct qcom_swrm_ctrl *ctrl,  in qcom_swrm_cmd_fifo_rd_cmd()  argument
218 				     u32 len, u8 *rval)  in qcom_swrm_cmd_fifo_rd_cmd()  argument
225 	spin_lock_irqsave(&ctrl->comp_lock, flags);  in qcom_swrm_cmd_fifo_rd_cmd()
226 	ctrl->comp = ∁  in qcom_swrm_cmd_fifo_rd_cmd()
227 	spin_unlock_irqrestore(&ctrl->comp_lock, flags);  in qcom_swrm_cmd_fifo_rd_cmd()
229 	val = SWRM_REG_VAL_PACK(len, dev_addr, SWRM_SPECIAL_CMD_ID, reg_addr);  in qcom_swrm_cmd_fifo_rd_cmd()
230 	ret = ctrl->reg_write(ctrl, SWRM_CMD_FIFO_RD_CMD, val);  in qcom_swrm_cmd_fifo_rd_cmd()
234 	ret = wait_for_completion_timeout(ctrl->comp,  in qcom_swrm_cmd_fifo_rd_cmd()
244 	for (i = 0; i < len; i++) {  in qcom_swrm_cmd_fifo_rd_cmd()
245 		ctrl->reg_read(ctrl, SWRM_CMD_FIFO_RD_FIFO_ADDR, &val);  in qcom_swrm_cmd_fifo_rd_cmd()
250 	spin_lock_irqsave(&ctrl->comp_lock, flags);  in qcom_swrm_cmd_fifo_rd_cmd()
251 	ctrl->comp = NULL;  in qcom_swrm_cmd_fifo_rd_cmd()
252 	spin_unlock_irqrestore(&ctrl->comp_lock, flags);  in qcom_swrm_cmd_fifo_rd_cmd()
257 static void qcom_swrm_get_device_status(struct qcom_swrm_ctrl *ctrl)  in qcom_swrm_get_device_status()  argument
262 	ctrl->reg_read(ctrl, SWRM_MCP_SLV_STATUS, &val);  in qcom_swrm_get_device_status()
269 		ctrl->status[i] = s;  in qcom_swrm_get_device_status()
275 	struct qcom_swrm_ctrl *ctrl = dev_id;  in qcom_swrm_irq_handler()  local
279 	ctrl->reg_read(ctrl, SWRM_INTERRUPT_STATUS, &sts);  in qcom_swrm_irq_handler()
282 		ctrl->reg_read(ctrl, SWRM_CMD_FIFO_STATUS, &value);  in qcom_swrm_irq_handler()
283 		dev_err_ratelimited(ctrl->dev,  in qcom_swrm_irq_handler()
286 		ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CMD, 0x1);  in qcom_swrm_irq_handler()
291 		schedule_work(&ctrl->slave_work);  in qcom_swrm_irq_handler()
298 	ctrl->reg_write(ctrl, SWRM_INTERRUPT_CLEAR, sts);  in qcom_swrm_irq_handler()
301 		spin_lock_irqsave(&ctrl->comp_lock, flags);  in qcom_swrm_irq_handler()
302 		if (ctrl->comp)  in qcom_swrm_irq_handler()
303 			complete(ctrl->comp);  in qcom_swrm_irq_handler()
304 		spin_unlock_irqrestore(&ctrl->comp_lock, flags);  in qcom_swrm_irq_handler()
309 static int qcom_swrm_init(struct qcom_swrm_ctrl *ctrl)  in qcom_swrm_init()  argument
314 	val = FIELD_PREP(SWRM_MCP_FRAME_CTRL_BANK_ROW_CTRL_BMSK, ctrl->rows_index);  in qcom_swrm_init()
315 	val |= FIELD_PREP(SWRM_MCP_FRAME_CTRL_BANK_COL_CTRL_BMSK, ctrl->cols_index);  in qcom_swrm_init()
317 	ctrl->reg_write(ctrl, SWRM_MCP_FRAME_CTRL_BANK_ADDR(0), val);  in qcom_swrm_init()
320 	ctrl->reg_write(ctrl, SWRM_ENUMERATOR_CFG_ADDR, 0);  in qcom_swrm_init()
323 	ctrl->reg_write(ctrl, SWRM_INTERRUPT_MASK_ADDR,  in qcom_swrm_init()
327 	ctrl->reg_read(ctrl, SWRM_MCP_CFG_ADDR, &val);  in qcom_swrm_init()
329 	ctrl->reg_write(ctrl, SWRM_MCP_CFG_ADDR, val);  in qcom_swrm_init()
332 	ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CFG_ADDR, SWRM_RD_WR_CMD_RETRIES);  in qcom_swrm_init()
335 	ctrl->reg_write(ctrl, SWRM_COMP_CFG_ADDR,  in qcom_swrm_init()
340 	if (ctrl->mmio) {  in qcom_swrm_init()
341 		ctrl->reg_write(ctrl, SWRM_INTERRUPT_CPU_EN,  in qcom_swrm_init()
350 	struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);  in qcom_swrm_xfer_msg()  local
351 	int ret, i, len;  in qcom_swrm_xfer_msg()  local
353 	if (msg->flags == SDW_MSG_FLAG_READ) {  in qcom_swrm_xfer_msg()
354 		for (i = 0; i < msg->len;) {  in qcom_swrm_xfer_msg()
355 			if ((msg->len - i) < QCOM_SWRM_MAX_RD_LEN)  in qcom_swrm_xfer_msg()
356 				len = msg->len - i;  in qcom_swrm_xfer_msg()
358 				len = QCOM_SWRM_MAX_RD_LEN;  in qcom_swrm_xfer_msg()
360 			ret = qcom_swrm_cmd_fifo_rd_cmd(ctrl, msg->dev_num,  in qcom_swrm_xfer_msg()
361 							msg->addr + i, len,  in qcom_swrm_xfer_msg()
362 						       &msg->buf[i]);  in qcom_swrm_xfer_msg()
366 			i = i + len;  in qcom_swrm_xfer_msg()
368 	} else if (msg->flags == SDW_MSG_FLAG_WRITE) {  in qcom_swrm_xfer_msg()
369 		for (i = 0; i < msg->len; i++) {  in qcom_swrm_xfer_msg()
370 			ret = qcom_swrm_cmd_fifo_wr_cmd(ctrl, msg->buf[i],  in qcom_swrm_xfer_msg()
371 							msg->dev_num,  in qcom_swrm_xfer_msg()
372 						       msg->addr + i);  in qcom_swrm_xfer_msg()
383 	u32 reg = SWRM_MCP_FRAME_CTRL_BANK_ADDR(bus->params.next_bank);  in qcom_swrm_pre_bank_switch()
384 	struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);  in qcom_swrm_pre_bank_switch()  local
387 	ctrl->reg_read(ctrl, reg, &val);  in qcom_swrm_pre_bank_switch()
389 	u32p_replace_bits(&val, ctrl->cols_index, SWRM_MCP_FRAME_CTRL_BANK_COL_CTRL_BMSK);  in qcom_swrm_pre_bank_switch()
390 	u32p_replace_bits(&val, ctrl->rows_index, SWRM_MCP_FRAME_CTRL_BANK_ROW_CTRL_BMSK);  in qcom_swrm_pre_bank_switch()
392 	return ctrl->reg_write(ctrl, reg, val);  in qcom_swrm_pre_bank_switch()
407 	struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);  in qcom_swrm_transport_params()  local
409 	int reg = SWRM_DP_PORT_CTRL_BANK((params->port_num), bank);  in qcom_swrm_transport_params()
412 	value = params->offset1 << SWRM_DP_PORT_CTRL_OFFSET1_SHFT;  in qcom_swrm_transport_params()
413 	value |= params->offset2 << SWRM_DP_PORT_CTRL_OFFSET2_SHFT;  in qcom_swrm_transport_params()
414 	value |= params->sample_interval - 1;  in qcom_swrm_transport_params()
416 	ret = ctrl->reg_write(ctrl, reg, value);  in qcom_swrm_transport_params()
418 	if (!ret && params->blk_pkg_mode) {  in qcom_swrm_transport_params()
419 		reg = SWRM_DP_BLOCK_CTRL3_BANK(params->port_num, bank);  in qcom_swrm_transport_params()
421 		ret = ctrl->reg_write(ctrl, reg, 1);  in qcom_swrm_transport_params()
431 	u32 reg = SWRM_DP_PORT_CTRL_BANK(enable_ch->port_num, bank);  in qcom_swrm_port_enable()
432 	struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);  in qcom_swrm_port_enable()  local
435 	ctrl->reg_read(ctrl, reg, &val);  in qcom_swrm_port_enable()
437 	if (enable_ch->enable)  in qcom_swrm_port_enable()
438 		val |= (enable_ch->ch_mask << SWRM_DP_PORT_CTRL_EN_CHAN_SHFT);  in qcom_swrm_port_enable()
442 	return ctrl->reg_write(ctrl, reg, val);  in qcom_swrm_port_enable()
458 	struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);  in qcom_swrm_compute_params()  local
465 	list_for_each_entry(m_rt, &bus->m_rt_list, bus_node) {  in qcom_swrm_compute_params()
466 		list_for_each_entry(p_rt, &m_rt->port_list, port_node) {  in qcom_swrm_compute_params()
467 			pcfg = &ctrl->pconfig[p_rt->num - 1];  in qcom_swrm_compute_params()
468 			p_rt->transport_params.port_num = p_rt->num;  in qcom_swrm_compute_params()
469 			p_rt->transport_params.sample_interval = pcfg->si + 1;  in qcom_swrm_compute_params()
470 			p_rt->transport_params.offset1 = pcfg->off1;  in qcom_swrm_compute_params()
471 			p_rt->transport_params.offset2 = pcfg->off2;  in qcom_swrm_compute_params()
472 			p_rt->transport_params.blk_pkg_mode = pcfg->bp_mode;  in qcom_swrm_compute_params()
475 		list_for_each_entry(s_rt, &m_rt->slave_rt_list, m_rt_node) {  in qcom_swrm_compute_params()
476 			list_for_each_entry(p_rt, &s_rt->port_list, port_node) {  in qcom_swrm_compute_params()
477 				pcfg = &ctrl->pconfig[i];  in qcom_swrm_compute_params()
478 				p_rt->transport_params.port_num = p_rt->num;  in qcom_swrm_compute_params()
479 				p_rt->transport_params.sample_interval =  in qcom_swrm_compute_params()
480 					pcfg->si + 1;  in qcom_swrm_compute_params()
481 				p_rt->transport_params.offset1 = pcfg->off1;  in qcom_swrm_compute_params()
482 				p_rt->transport_params.offset2 = pcfg->off2;  in qcom_swrm_compute_params()
483 				p_rt->transport_params.blk_pkg_mode = pcfg->bp_mode;  in qcom_swrm_compute_params()
498 	struct qcom_swrm_ctrl *ctrl =  in qcom_swrm_slave_wq()  local
501 	qcom_swrm_get_device_status(ctrl);  in qcom_swrm_slave_wq()
502 	sdw_handle_slave_status(&ctrl->bus, ctrl->status);  in qcom_swrm_slave_wq()
506 static void qcom_swrm_stream_free_ports(struct qcom_swrm_ctrl *ctrl,  in qcom_swrm_stream_free_ports()  argument
513 	mutex_lock(&ctrl->port_lock);  in qcom_swrm_stream_free_ports()
515 	list_for_each_entry(m_rt, &stream->master_list, stream_node) {  in qcom_swrm_stream_free_ports()
516 		if (m_rt->direction == SDW_DATA_DIR_RX)  in qcom_swrm_stream_free_ports()
517 			port_mask = &ctrl->dout_port_mask;  in qcom_swrm_stream_free_ports()
519 			port_mask = &ctrl->din_port_mask;  in qcom_swrm_stream_free_ports()
521 		list_for_each_entry(p_rt, &m_rt->port_list, port_node)  in qcom_swrm_stream_free_ports()
522 			clear_bit(p_rt->num - 1, port_mask);  in qcom_swrm_stream_free_ports()
525 	mutex_unlock(&ctrl->port_lock);  in qcom_swrm_stream_free_ports()
528 static int qcom_swrm_stream_alloc_ports(struct qcom_swrm_ctrl *ctrl,  in qcom_swrm_stream_alloc_ports()  argument
541 	mutex_lock(&ctrl->port_lock);  in qcom_swrm_stream_alloc_ports()
542 	list_for_each_entry(m_rt, &stream->master_list, stream_node) {  in qcom_swrm_stream_alloc_ports()
543 		if (m_rt->direction == SDW_DATA_DIR_RX) {  in qcom_swrm_stream_alloc_ports()
544 			maxport = ctrl->num_dout_ports;  in qcom_swrm_stream_alloc_ports()
545 			port_mask = &ctrl->dout_port_mask;  in qcom_swrm_stream_alloc_ports()
547 			maxport = ctrl->num_din_ports;  in qcom_swrm_stream_alloc_ports()
548 			port_mask = &ctrl->din_port_mask;  in qcom_swrm_stream_alloc_ports()
551 		list_for_each_entry(s_rt, &m_rt->slave_rt_list, m_rt_node) {  in qcom_swrm_stream_alloc_ports()
552 			list_for_each_entry(p_rt, &s_rt->port_list, port_node) {  in qcom_swrm_stream_alloc_ports()
553 				/* Port numbers start from 1 - 14*/  in qcom_swrm_stream_alloc_ports()
555 				if (pn > (maxport - 1)) {  in qcom_swrm_stream_alloc_ports()
556 					dev_err(ctrl->dev, "All ports busy\n");  in qcom_swrm_stream_alloc_ports()
557 					ret = -EBUSY;  in qcom_swrm_stream_alloc_ports()
562 				pconfig[nports].ch_mask = p_rt->ch_mask;  in qcom_swrm_stream_alloc_ports()
576 	sconfig.type = stream->type;  in qcom_swrm_stream_alloc_ports()
578 	sdw_stream_add_master(&ctrl->bus, &sconfig, pconfig,  in qcom_swrm_stream_alloc_ports()
583 			clear_bit(pconfig[i].num - 1, port_mask);  in qcom_swrm_stream_alloc_ports()
586 	mutex_unlock(&ctrl->port_lock);  in qcom_swrm_stream_alloc_ports()
595 	struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev);  in qcom_swrm_hw_params()  local
596 	struct sdw_stream_runtime *sruntime = ctrl->sruntime[dai->id];  in qcom_swrm_hw_params()
599 	ret = qcom_swrm_stream_alloc_ports(ctrl, sruntime, params,  in qcom_swrm_hw_params()
600 					   substream->stream);  in qcom_swrm_hw_params()
602 		qcom_swrm_stream_free_ports(ctrl, sruntime);  in qcom_swrm_hw_params()
610 	struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev);  in qcom_swrm_hw_free()  local
611 	struct sdw_stream_runtime *sruntime = ctrl->sruntime[dai->id];  in qcom_swrm_hw_free()
613 	qcom_swrm_stream_free_ports(ctrl, sruntime);  in qcom_swrm_hw_free()
614 	sdw_stream_remove_master(&ctrl->bus, sruntime);  in qcom_swrm_hw_free()
622 	struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev);  in qcom_swrm_set_sdw_stream()  local
624 	ctrl->sruntime[dai->id] = stream;  in qcom_swrm_set_sdw_stream()
631 	struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev);  in qcom_swrm_get_sdw_stream()  local
633 	return ctrl->sruntime[dai->id];  in qcom_swrm_get_sdw_stream()
639 	struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev);  in qcom_swrm_startup()  local
640 	struct snd_soc_pcm_runtime *rtd = substream->private_data;  in qcom_swrm_startup()
645 	sruntime = sdw_alloc_stream(dai->name);  in qcom_swrm_startup()
647 		return -ENOMEM;  in qcom_swrm_startup()
649 	ctrl->sruntime[dai->id] = sruntime;  in qcom_swrm_startup()
653 						 substream->stream);  in qcom_swrm_startup()
654 		if (ret < 0 && ret != -ENOTSUPP) {  in qcom_swrm_startup()
655 			dev_err(dai->dev, "Failed to set sdw stream on %s",  in qcom_swrm_startup()
656 				codec_dai->name);  in qcom_swrm_startup()
668 	struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev);  in qcom_swrm_shutdown()  local
670 	sdw_release_stream(ctrl->sruntime[dai->id]);  in qcom_swrm_shutdown()
671 	ctrl->sruntime[dai->id] = NULL;  in qcom_swrm_shutdown()
687 static int qcom_swrm_register_dais(struct qcom_swrm_ctrl *ctrl)  in qcom_swrm_register_dais()  argument
689 	int num_dais = ctrl->num_dout_ports + ctrl->num_din_ports;  in qcom_swrm_register_dais()
692 	struct device *dev = ctrl->dev;  in qcom_swrm_register_dais()
698 		return -ENOMEM;  in qcom_swrm_register_dais()
703 			return -ENOMEM;  in qcom_swrm_register_dais()
705 		if (i < ctrl->num_dout_ports)  in qcom_swrm_register_dais()
710 		stream->channels_min = 1;  in qcom_swrm_register_dais()
711 		stream->channels_max = 1;  in qcom_swrm_register_dais()
712 		stream->rates = SNDRV_PCM_RATE_48000;  in qcom_swrm_register_dais()
713 		stream->formats = SNDRV_PCM_FMTBIT_S16_LE;  in qcom_swrm_register_dais()
719 	return devm_snd_soc_register_component(ctrl->dev,  in qcom_swrm_register_dais()
724 static int qcom_swrm_get_port_config(struct qcom_swrm_ctrl *ctrl)  in qcom_swrm_get_port_config()  argument
726 	struct device_node *np = ctrl->dev->of_node;  in qcom_swrm_get_port_config()
733 	ctrl->reg_read(ctrl, SWRM_COMP_PARAMS, &val);  in qcom_swrm_get_port_config()
735 	ctrl->num_dout_ports = FIELD_GET(SWRM_COMP_PARAMS_DOUT_PORTS_MASK, val);  in qcom_swrm_get_port_config()
736 	ctrl->num_din_ports = FIELD_GET(SWRM_COMP_PARAMS_DIN_PORTS_MASK, val);  in qcom_swrm_get_port_config()
738 	ret = of_property_read_u32(np, "qcom,din-ports", &val);  in qcom_swrm_get_port_config()
742 	if (val > ctrl->num_din_ports)  in qcom_swrm_get_port_config()
743 		return -EINVAL;  in qcom_swrm_get_port_config()
745 	ctrl->num_din_ports = val;  in qcom_swrm_get_port_config()
747 	ret = of_property_read_u32(np, "qcom,dout-ports", &val);  in qcom_swrm_get_port_config()
751 	if (val > ctrl->num_dout_ports)  in qcom_swrm_get_port_config()
752 		return -EINVAL;  in qcom_swrm_get_port_config()
754 	ctrl->num_dout_ports = val;  in qcom_swrm_get_port_config()
756 	nports = ctrl->num_dout_ports + ctrl->num_din_ports;  in qcom_swrm_get_port_config()
758 	ret = of_property_read_u8_array(np, "qcom,ports-offset1",  in qcom_swrm_get_port_config()
763 	ret = of_property_read_u8_array(np, "qcom,ports-offset2",  in qcom_swrm_get_port_config()
768 	ret = of_property_read_u8_array(np, "qcom,ports-sinterval-low",  in qcom_swrm_get_port_config()
773 	ret = of_property_read_u8_array(np, "qcom,ports-block-pack-mode",  in qcom_swrm_get_port_config()
776 		ctrl->pconfig[i].si = si[i];  in qcom_swrm_get_port_config()
777 		ctrl->pconfig[i].off1 = off1[i];  in qcom_swrm_get_port_config()
778 		ctrl->pconfig[i].off2 = off2[i];  in qcom_swrm_get_port_config()
779 		ctrl->pconfig[i].bp_mode = bp_mode[i];  in qcom_swrm_get_port_config()
787 	struct device *dev = &pdev->dev;
790 	struct qcom_swrm_ctrl *ctrl;  local
795 	ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL);
796 	if (!ctrl)
797 		return -ENOMEM;
800 	ctrl->rows_index = sdw_find_row_index(data->default_rows);
801 	ctrl->cols_index = sdw_find_col_index(data->default_cols);
803 	if (dev->parent->bus == &slimbus_bus) {
807 		ctrl->reg_read = qcom_swrm_ahb_reg_read;
808 		ctrl->reg_write = qcom_swrm_ahb_reg_write;
809 		ctrl->regmap = dev_get_regmap(dev->parent, NULL);
810 		if (!ctrl->regmap)
811 			return -EINVAL;
813 		ctrl->reg_read = qcom_swrm_cpu_reg_read;
814 		ctrl->reg_write = qcom_swrm_cpu_reg_write;
815 		ctrl->mmio = devm_platform_ioremap_resource(pdev, 0);
816 		if (IS_ERR(ctrl->mmio))
817 			return PTR_ERR(ctrl->mmio);
820 	ctrl->irq = of_irq_get(dev->of_node, 0);
821 	if (ctrl->irq < 0) {
822 		ret = ctrl->irq;
826 	ctrl->hclk = devm_clk_get(dev, "iface");
827 	if (IS_ERR(ctrl->hclk)) {
828 		ret = PTR_ERR(ctrl->hclk);
832 	clk_prepare_enable(ctrl->hclk);
834 	ctrl->dev = dev;
835 	dev_set_drvdata(&pdev->dev, ctrl);
836 	spin_lock_init(&ctrl->comp_lock);
837 	mutex_init(&ctrl->port_lock);
838 	INIT_WORK(&ctrl->slave_work, qcom_swrm_slave_wq);
840 	ctrl->bus.ops = &qcom_swrm_ops;
841 	ctrl->bus.port_ops = &qcom_swrm_port_ops;
842 	ctrl->bus.compute_params = &qcom_swrm_compute_params;
844 	ret = qcom_swrm_get_port_config(ctrl);
848 	params = &ctrl->bus.params;
849 	params->max_dr_freq = DEFAULT_CLK_FREQ;
850 	params->curr_dr_freq = DEFAULT_CLK_FREQ;
851 	params->col = data->default_cols;
852 	params->row = data->default_rows;
853 	ctrl->reg_read(ctrl, SWRM_MCP_STATUS, &val);
854 	params->curr_bank = val & SWRM_MCP_STATUS_BANK_NUM_MASK;
855 	params->next_bank = !params->curr_bank;
857 	prop = &ctrl->bus.prop;
858 	prop->max_clk_freq = DEFAULT_CLK_FREQ;
859 	prop->num_clk_gears = 0;
860 	prop->num_clk_freq = MAX_FREQ_NUM;
861 	prop->clk_freq = &qcom_swrm_freq_tbl[0];
862 	prop->default_col = data->default_cols;
863 	prop->default_row = data->default_rows;
865 	ctrl->reg_read(ctrl, SWRM_COMP_HW_VERSION, &ctrl->version);
867 	ret = devm_request_threaded_irq(dev, ctrl->irq, NULL,
871 					"soundwire", ctrl);
877 	ret = sdw_bus_master_add(&ctrl->bus, dev, dev->fwnode);
884 	qcom_swrm_init(ctrl);
885 	ret = qcom_swrm_register_dais(ctrl);
890 		 (ctrl->version >> 24) & 0xff, (ctrl->version >> 16) & 0xff,
891 		 ctrl->version & 0xffff);
896 	sdw_bus_master_delete(&ctrl->bus);
898 	clk_disable_unprepare(ctrl->hclk);
905 	struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(&pdev->dev);  local
907 	sdw_bus_master_delete(&ctrl->bus);
908 	clk_disable_unprepare(ctrl->hclk);
914 	{ .compatible = "qcom,soundwire-v1.3.0", .data = &swrm_v1_3_data },
915 	{ .compatible = "qcom,soundwire-v1.5.1", .data = &swrm_v1_5_data },
925 		.name	= "qcom-soundwire",