Lines Matching +full:resume +full:- +full:offset
1 // SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
2 // Copyright(c) 2015-17 Intel Corporation.
31 * flags reused in each byte, with master0 using the ls-byte, etc.
70 #define SDW_SHIM_SYNC_SYNCPRD_VAL_24 (24000 / SDW_CADENCE_GSYNC_KHZ - 1)
71 #define SDW_SHIM_SYNC_SYNCPRD_VAL_38_4 (38400 / SDW_CADENCE_GSYNC_KHZ - 1)
128 static inline int intel_readl(void __iomem *base, int offset) in intel_readl() argument
130 return readl(base + offset); in intel_readl()
133 static inline void intel_writel(void __iomem *base, int offset, int value) in intel_writel() argument
135 writel(value, base + offset); in intel_writel()
138 static inline u16 intel_readw(void __iomem *base, int offset) in intel_readw() argument
140 return readw(base + offset); in intel_readw()
143 static inline void intel_writew(void __iomem *base, int offset, u16 value) in intel_writew() argument
145 writew(value, base + offset); in intel_writew()
148 static int intel_wait_bit(void __iomem *base, int offset, u32 mask, u32 target) in intel_wait_bit() argument
154 reg_read = readl(base + offset); in intel_wait_bit()
158 timeout--; in intel_wait_bit()
162 return -EAGAIN; in intel_wait_bit()
165 static int intel_clear_bit(void __iomem *base, int offset, u32 value, u32 mask) in intel_clear_bit() argument
167 writel(value, base + offset); in intel_clear_bit()
168 return intel_wait_bit(base, offset, mask, 0); in intel_clear_bit()
171 static int intel_set_bit(void __iomem *base, int offset, u32 value, u32 mask) in intel_set_bit() argument
173 writel(value, base + offset); in intel_set_bit()
174 return intel_wait_bit(base, offset, mask, mask); in intel_set_bit()
194 return scnprintf(buf + pos, RD_BUF - pos, "%4x\t%4x\n", reg, value); in intel_sprintf()
199 struct sdw_intel *sdw = s_file->private; in intel_reg_show()
200 void __iomem *s = sdw->link_res->shim; in intel_reg_show()
201 void __iomem *a = sdw->link_res->alh; in intel_reg_show()
209 return -ENOMEM; in intel_reg_show()
214 ret += scnprintf(buf + ret, RD_BUF - ret, "\nShim\n"); in intel_reg_show()
222 ret += scnprintf(buf + ret, RD_BUF - ret, "\nLink%d\n", i); in intel_reg_show()
230 ret += scnprintf(buf + ret, RD_BUF - ret, "\n PCMSyCH registers\n"); in intel_reg_show()
234 * cleanup to remove hard-coded Intel configurations in intel_reg_show()
243 ret += scnprintf(buf + ret, RD_BUF - ret, "\n PDMSCAP, IOCTL, CTMCTL\n"); in intel_reg_show()
250 ret += scnprintf(buf + ret, RD_BUF - ret, "\nWake registers\n"); in intel_reg_show()
254 ret += scnprintf(buf + ret, RD_BUF - ret, "\nALH STRMzCFG\n"); in intel_reg_show()
268 struct sdw_bus *bus = &sdw->cdns.bus; in intel_set_m_datamode()
271 return -EINVAL; in intel_set_m_datamode()
276 bus->params.m_data_mode = value; in intel_set_m_datamode()
286 struct sdw_bus *bus = &sdw->cdns.bus; in intel_set_s_datamode()
289 return -EINVAL; in intel_set_s_datamode()
294 bus->params.s_data_mode = value; in intel_set_s_datamode()
303 struct dentry *root = sdw->cdns.bus.debugfs; in intel_debugfs_init()
308 sdw->debugfs = debugfs_create_dir("intel-sdw", root); in intel_debugfs_init()
310 debugfs_create_file("intel-registers", 0400, sdw->debugfs, sdw, in intel_debugfs_init()
313 debugfs_create_file("intel-m-datamode", 0200, sdw->debugfs, sdw, in intel_debugfs_init()
316 debugfs_create_file("intel-s-datamode", 0200, sdw->debugfs, sdw, in intel_debugfs_init()
319 sdw_cdns_debugfs_init(&sdw->cdns, sdw->debugfs); in intel_debugfs_init()
324 debugfs_remove_recursive(sdw->debugfs); in intel_debugfs_exit()
337 unsigned int link_id = sdw->instance; in intel_link_power_up()
338 void __iomem *shim = sdw->link_res->shim; in intel_link_power_up()
339 u32 *shim_mask = sdw->link_res->shim_mask; in intel_link_power_up()
340 struct sdw_bus *bus = &sdw->cdns.bus; in intel_link_power_up()
341 struct sdw_master_prop *prop = &bus->prop; in intel_link_power_up()
348 mutex_lock(sdw->link_res->shim_lock); in intel_link_power_up()
352 * to generate the SoundWire SSP - which defines a 'safe' in intel_link_power_up()
360 if (prop->mclk_freq % 6000000) in intel_link_power_up()
366 dev_dbg(sdw->cdns.dev, "%s: powering up all links\n", __func__); in intel_link_power_up()
369 dev_dbg(sdw->cdns.dev, in intel_link_power_up()
383 /* only power-up enabled links */ in intel_link_power_up()
384 spa_mask = FIELD_PREP(SDW_SHIM_LCTL_SPA_MASK, sdw->link_res->link_mask); in intel_link_power_up()
385 cpa_mask = FIELD_PREP(SDW_SHIM_LCTL_CPA_MASK, sdw->link_res->link_mask); in intel_link_power_up()
391 dev_err(sdw->cdns.dev, "Failed to power up link: %d\n", ret); in intel_link_power_up()
399 dev_err(sdw->cdns.dev, in intel_link_power_up()
407 sdw->cdns.link_up = true; in intel_link_power_up()
409 mutex_unlock(sdw->link_res->shim_lock); in intel_link_power_up()
417 void __iomem *shim = sdw->link_res->shim; in intel_shim_glue_to_master_ip()
418 unsigned int link_id = sdw->instance; in intel_shim_glue_to_master_ip()
447 unsigned int link_id = sdw->instance; in intel_shim_master_ip_to_glue()
448 void __iomem *shim = sdw->link_res->shim; in intel_shim_master_ip_to_glue()
467 void __iomem *shim = sdw->link_res->shim; in intel_shim_init()
468 unsigned int link_id = sdw->instance; in intel_shim_init()
472 mutex_lock(sdw->link_res->shim_lock); in intel_shim_init()
499 mutex_unlock(sdw->link_res->shim_lock); in intel_shim_init()
506 void __iomem *shim = sdw->link_res->shim; in intel_shim_wake()
507 unsigned int link_id = sdw->instance; in intel_shim_wake()
510 mutex_lock(sdw->link_res->shim_lock); in intel_shim_wake()
527 mutex_unlock(sdw->link_res->shim_lock); in intel_shim_wake()
533 unsigned int link_id = sdw->instance; in intel_link_power_down()
534 void __iomem *shim = sdw->link_res->shim; in intel_link_power_down()
535 u32 *shim_mask = sdw->link_res->shim_mask; in intel_link_power_down()
538 mutex_lock(sdw->link_res->shim_lock); in intel_link_power_down()
543 dev_err(sdw->cdns.dev, in intel_link_power_down()
544 "%s: Unbalanced power-up/down calls\n", __func__); in intel_link_power_down()
550 dev_dbg(sdw->cdns.dev, "%s: powering down all links\n", __func__); in intel_link_power_down()
555 /* only power-down enabled links */ in intel_link_power_down()
556 spa_mask = FIELD_PREP(SDW_SHIM_LCTL_SPA_MASK, ~sdw->link_res->link_mask); in intel_link_power_down()
557 cpa_mask = FIELD_PREP(SDW_SHIM_LCTL_CPA_MASK, sdw->link_res->link_mask); in intel_link_power_down()
566 mutex_unlock(sdw->link_res->shim_lock); in intel_link_power_down()
569 dev_err(sdw->cdns.dev, "%s: could not power down link\n", __func__); in intel_link_power_down()
574 sdw->cdns.link_up = false; in intel_link_power_down()
580 void __iomem *shim = sdw->link_res->shim; in intel_shim_sync_arm()
583 mutex_lock(sdw->link_res->shim_lock); in intel_shim_sync_arm()
587 sync_reg |= (SDW_SHIM_SYNC_CMDSYNC << sdw->instance); in intel_shim_sync_arm()
590 mutex_unlock(sdw->link_res->shim_lock); in intel_shim_sync_arm()
595 void __iomem *shim = sdw->link_res->shim; in intel_shim_sync_go_unlocked()
613 dev_err(sdw->cdns.dev, "SyncGO clear failed: %d\n", ret); in intel_shim_sync_go_unlocked()
622 mutex_lock(sdw->link_res->shim_lock); in intel_shim_sync_go()
626 mutex_unlock(sdw->link_res->shim_lock); in intel_shim_sync_go()
637 void __iomem *shim = sdw->link_res->shim; in intel_pdi_init()
638 unsigned int link_id = sdw->instance; in intel_pdi_init()
644 config->pcm_bd = FIELD_GET(SDW_SHIM_PCMSCAP_BSS, pcm_cap); in intel_pdi_init()
645 config->pcm_in = FIELD_GET(SDW_SHIM_PCMSCAP_ISS, pcm_cap); in intel_pdi_init()
646 config->pcm_out = FIELD_GET(SDW_SHIM_PCMSCAP_OSS, pcm_cap); in intel_pdi_init()
648 dev_dbg(sdw->cdns.dev, "PCM cap bd:%d in:%d out:%d\n", in intel_pdi_init()
649 config->pcm_bd, config->pcm_in, config->pcm_out); in intel_pdi_init()
654 config->pdm_bd = FIELD_GET(SDW_SHIM_PDMSCAP_BSS, pdm_cap); in intel_pdi_init()
655 config->pdm_in = FIELD_GET(SDW_SHIM_PDMSCAP_ISS, pdm_cap); in intel_pdi_init()
656 config->pdm_out = FIELD_GET(SDW_SHIM_PDMSCAP_OSS, pdm_cap); in intel_pdi_init()
658 dev_dbg(sdw->cdns.dev, "PDM cap bd:%d in:%d out:%d\n", in intel_pdi_init()
659 config->pdm_bd, config->pdm_in, config->pdm_out); in intel_pdi_init()
665 void __iomem *shim = sdw->link_res->shim; in intel_pdi_get_ch_cap()
666 unsigned int link_id = sdw->instance; in intel_pdi_get_ch_cap()
700 pdi->ch_count = intel_pdi_get_ch_cap(sdw, pdi->num, pcm); in intel_pdi_get_ch_update()
701 ch_count += pdi->ch_count; in intel_pdi_get_ch_update()
712 intel_pdi_get_ch_update(sdw, stream->bd, stream->num_bd, in intel_pdi_stream_ch_update()
713 &stream->num_ch_bd, pcm); in intel_pdi_stream_ch_update()
715 intel_pdi_get_ch_update(sdw, stream->in, stream->num_in, in intel_pdi_stream_ch_update()
716 &stream->num_ch_in, pcm); in intel_pdi_stream_ch_update()
718 intel_pdi_get_ch_update(sdw, stream->out, stream->num_out, in intel_pdi_stream_ch_update()
719 &stream->num_ch_out, pcm); in intel_pdi_stream_ch_update()
727 intel_pdi_stream_ch_update(sdw, &sdw->cdns.pcm, true); in intel_pdi_ch_update()
728 intel_pdi_stream_ch_update(sdw, &sdw->cdns.pdm, false); in intel_pdi_ch_update()
736 void __iomem *shim = sdw->link_res->shim; in intel_pdi_shim_configure()
737 unsigned int link_id = sdw->instance; in intel_pdi_shim_configure()
741 pdi->intel_alh_id = (link_id * 16) + pdi->num + 3; in intel_pdi_shim_configure()
742 if (pdi->num >= 2) in intel_pdi_shim_configure()
743 pdi->intel_alh_id += 2; in intel_pdi_shim_configure()
749 if (pdi->type != SDW_STREAM_PCM) in intel_pdi_shim_configure()
752 if (pdi->dir == SDW_DATA_DIR_RX) in intel_pdi_shim_configure()
757 u32p_replace_bits(&pdi_conf, pdi->intel_alh_id, SDW_SHIM_PCMSYCM_STREAM); in intel_pdi_shim_configure()
758 u32p_replace_bits(&pdi_conf, pdi->l_ch_num, SDW_SHIM_PCMSYCM_LCHN); in intel_pdi_shim_configure()
759 u32p_replace_bits(&pdi_conf, pdi->h_ch_num, SDW_SHIM_PCMSYCM_HCHN); in intel_pdi_shim_configure()
761 intel_writew(shim, SDW_SHIM_PCMSYCHM(link_id, pdi->num), pdi_conf); in intel_pdi_shim_configure()
767 void __iomem *alh = sdw->link_res->alh; in intel_pdi_alh_configure()
768 unsigned int link_id = sdw->instance; in intel_pdi_alh_configure()
772 pdi->intel_alh_id = (link_id * 16) + pdi->num + 3; in intel_pdi_alh_configure()
773 if (pdi->num >= 2) in intel_pdi_alh_configure()
774 pdi->intel_alh_id += 2; in intel_pdi_alh_configure()
777 conf = intel_readl(alh, SDW_ALH_STRMZCFG(pdi->intel_alh_id)); in intel_pdi_alh_configure()
780 u32p_replace_bits(&conf, pdi->ch_count - 1, SDW_ALH_STRMZCFG_CHN); in intel_pdi_alh_configure()
782 intel_writel(alh, SDW_ALH_STRMZCFG(pdi->intel_alh_id), conf); in intel_pdi_alh_configure()
791 struct sdw_intel_link_res *res = sdw->link_res; in intel_params_stream()
800 if (res->ops && res->ops->params_stream && res->dev) in intel_params_stream()
801 return res->ops->params_stream(res->dev, in intel_params_stream()
803 return -EIO; in intel_params_stream()
811 struct sdw_intel_link_res *res = sdw->link_res; in intel_free_stream()
818 if (res->ops && res->ops->free_stream && res->dev) in intel_free_stream()
819 return res->ops->free_stream(res->dev, in intel_free_stream()
834 /* Write to register only for multi-link */ in intel_pre_bank_switch()
835 if (!bus->multi_link) in intel_pre_bank_switch()
847 void __iomem *shim = sdw->link_res->shim; in intel_post_bank_switch()
850 /* Write to register only for multi-link */ in intel_post_bank_switch()
851 if (!bus->multi_link) in intel_post_bank_switch()
854 mutex_lock(sdw->link_res->shim_lock); in intel_post_bank_switch()
874 mutex_unlock(sdw->link_res->shim_lock); in intel_post_bank_switch()
877 dev_err(sdw->cdns.dev, "Post bank switch failed: %d\n", ret); in intel_post_bank_switch()
892 ret = pm_runtime_get_sync(cdns->dev); in intel_startup()
893 if (ret < 0 && ret != -EACCES) { in intel_startup()
894 dev_err_ratelimited(cdns->dev, in intel_startup()
897 pm_runtime_put_noidle(cdns->dev); in intel_startup()
919 return -EIO; in intel_hw_params()
922 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) in intel_hw_params()
927 if (dma->stream_type == SDW_STREAM_PDM) in intel_hw_params()
931 pdi = sdw_cdns_alloc_pdi(cdns, &cdns->pcm, ch, dir, dai->id); in intel_hw_params()
933 pdi = sdw_cdns_alloc_pdi(cdns, &cdns->pdm, ch, dir, dai->id); in intel_hw_params()
936 ret = -EINVAL; in intel_hw_params()
940 /* do run-time configurations for SHIM, ALH and PDI/PORT */ in intel_hw_params()
946 dma->suspended = false; in intel_hw_params()
947 dma->pdi = pdi; in intel_hw_params()
948 dma->hw_params = params; in intel_hw_params()
952 sdw->instance, in intel_hw_params()
953 pdi->intel_alh_id); in intel_hw_params()
960 sconfig.type = dma->stream_type; in intel_hw_params()
962 if (dma->stream_type == SDW_STREAM_PDM) { in intel_hw_params()
972 ret = -ENOMEM; in intel_hw_params()
976 pconfig->num = pdi->num; in intel_hw_params()
977 pconfig->ch_mask = (1 << ch) - 1; in intel_hw_params()
979 ret = sdw_stream_add_master(&cdns->bus, &sconfig, in intel_hw_params()
980 pconfig, 1, dma->stream); in intel_hw_params()
982 dev_err(cdns->dev, "add master to stream failed:%d\n", ret); in intel_hw_params()
1000 dev_err(dai->dev, "failed to get dma data in %s", in intel_prepare()
1002 return -EIO; in intel_prepare()
1005 if (dma->suspended) { in intel_prepare()
1006 dma->suspended = false; in intel_prepare()
1009 * .prepare() is called after system resume, where we in intel_prepare()
1017 ch = params_channels(dma->hw_params); in intel_prepare()
1018 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) in intel_prepare()
1023 intel_pdi_shim_configure(sdw, dma->pdi); in intel_prepare()
1024 intel_pdi_alh_configure(sdw, dma->pdi); in intel_prepare()
1025 sdw_cdns_config_stream(cdns, ch, dir, dma->pdi); in intel_prepare()
1029 dma->hw_params, in intel_prepare()
1030 sdw->instance, in intel_prepare()
1031 dma->pdi->intel_alh_id); in intel_prepare()
1047 return -EIO; in intel_hw_free()
1050 * The sdw stream state will transition to RELEASED when stream-> in intel_hw_free()
1052 * DEPREPARED for the first cpu-dai and to RELEASED for the last in intel_hw_free()
1053 * cpu-dai. in intel_hw_free()
1055 ret = sdw_stream_remove_master(&cdns->bus, dma->stream); in intel_hw_free()
1057 dev_err(dai->dev, "remove master from stream %s failed: %d\n", in intel_hw_free()
1058 dma->stream->name, ret); in intel_hw_free()
1062 ret = intel_free_stream(sdw, substream, dai, sdw->instance); in intel_hw_free()
1064 dev_err(dai->dev, "intel_free_stream: failed %d", ret); in intel_hw_free()
1068 dma->hw_params = NULL; in intel_hw_free()
1069 dma->pdi = NULL; in intel_hw_free()
1079 pm_runtime_mark_last_busy(cdns->dev); in intel_shutdown()
1080 pm_runtime_put_autosuspend(cdns->dev); in intel_shutdown()
1094 dma = dai->playback_dma_data; in intel_component_dais_suspend()
1096 dma->suspended = true; in intel_component_dais_suspend()
1098 dma = dai->capture_dma_data; in intel_component_dais_suspend()
1100 dma->suspended = true; in intel_component_dais_suspend()
1124 dma = dai->playback_dma_data; in intel_get_sdw_stream()
1126 dma = dai->capture_dma_data; in intel_get_sdw_stream()
1129 return ERR_PTR(-EINVAL); in intel_get_sdw_stream()
1131 return dma->stream; in intel_get_sdw_stream()
1171 dais[i].name = devm_kasprintf(cdns->dev, GFP_KERNEL, in intel_create_dai()
1173 cdns->instance, i); in intel_create_dai()
1175 return -ENOMEM; in intel_create_dai()
1202 struct sdw_cdns *cdns = &sdw->cdns; in intel_register_dai()
1208 num_dai = cdns->pcm.num_pdi + cdns->pdm.num_pdi; in intel_register_dai()
1210 dais = devm_kcalloc(cdns->dev, num_dai, sizeof(*dais), GFP_KERNEL); in intel_register_dai()
1212 return -ENOMEM; in intel_register_dai()
1215 stream = &cdns->pcm; in intel_register_dai()
1217 ret = intel_create_dai(cdns, dais, INTEL_PDI_IN, cdns->pcm.num_in, in intel_register_dai()
1218 off, stream->num_ch_in, true); in intel_register_dai()
1222 off += cdns->pcm.num_in; in intel_register_dai()
1223 ret = intel_create_dai(cdns, dais, INTEL_PDI_OUT, cdns->pcm.num_out, in intel_register_dai()
1224 off, stream->num_ch_out, true); in intel_register_dai()
1228 off += cdns->pcm.num_out; in intel_register_dai()
1229 ret = intel_create_dai(cdns, dais, INTEL_PDI_BD, cdns->pcm.num_bd, in intel_register_dai()
1230 off, stream->num_ch_bd, true); in intel_register_dai()
1235 stream = &cdns->pdm; in intel_register_dai()
1236 off += cdns->pcm.num_bd; in intel_register_dai()
1237 ret = intel_create_dai(cdns, dais, INTEL_PDI_IN, cdns->pdm.num_in, in intel_register_dai()
1238 off, stream->num_ch_in, false); in intel_register_dai()
1242 off += cdns->pdm.num_in; in intel_register_dai()
1243 ret = intel_create_dai(cdns, dais, INTEL_PDI_OUT, cdns->pdm.num_out, in intel_register_dai()
1244 off, stream->num_ch_out, false); in intel_register_dai()
1248 off += cdns->pdm.num_out; in intel_register_dai()
1249 ret = intel_create_dai(cdns, dais, INTEL_PDI_BD, cdns->pdm.num_bd, in intel_register_dai()
1250 off, stream->num_ch_bd, false); in intel_register_dai()
1254 return snd_soc_register_component(cdns->dev, &dai_component, in intel_register_dai()
1260 struct sdw_master_prop *prop = &bus->prop; in sdw_master_read_intel_prop()
1267 "mipi-sdw-link-%d-subproperties", bus->link_id); in sdw_master_read_intel_prop()
1269 link = device_get_named_child_node(bus->dev, name); in sdw_master_read_intel_prop()
1271 dev_err(bus->dev, "Master node %s not found\n", name); in sdw_master_read_intel_prop()
1272 return -EIO; in sdw_master_read_intel_prop()
1276 "intel-sdw-ip-clock", in sdw_master_read_intel_prop()
1277 &prop->mclk_freq); in sdw_master_read_intel_prop()
1280 prop->mclk_freq /= 2; in sdw_master_read_intel_prop()
1283 "intel-quirk-mask", in sdw_master_read_intel_prop()
1287 prop->hw_disabled = true; in sdw_master_read_intel_prop()
1297 /* read Intel-specific properties */ in intel_prop_read()
1320 clock_stop = sdw_cdns_is_clock_stop(&sdw->cdns); in intel_init()
1332 struct device *dev = &pdev->dev; in intel_master_probe()
1340 return -ENOMEM; in intel_master_probe()
1342 cdns = &sdw->cdns; in intel_master_probe()
1343 bus = &cdns->bus; in intel_master_probe()
1345 sdw->instance = pdev->id; in intel_master_probe()
1346 sdw->link_res = dev_get_platdata(dev); in intel_master_probe()
1347 cdns->dev = dev; in intel_master_probe()
1348 cdns->registers = sdw->link_res->registers; in intel_master_probe()
1349 cdns->instance = sdw->instance; in intel_master_probe()
1350 cdns->msg_count = 0; in intel_master_probe()
1352 bus->link_id = pdev->id; in intel_master_probe()
1358 bus->ops = &sdw_intel_ops; in intel_master_probe()
1364 sdw->cdns.bus.compute_params = sdw_compute_params; in intel_master_probe()
1366 ret = sdw_bus_master_add(bus, dev, dev->fwnode); in intel_master_probe()
1372 if (bus->prop.hw_disabled) in intel_master_probe()
1375 bus->link_id); in intel_master_probe()
1380 bus->prop.err_threshold = 0; in intel_master_probe()
1388 struct device *dev = &pdev->dev; in intel_master_startup()
1391 struct sdw_bus *bus = &cdns->bus; in intel_master_startup()
1397 if (bus->prop.hw_disabled) { in intel_master_startup()
1400 sdw->instance); in intel_master_startup()
1404 link_flags = md_flags >> (bus->link_id * 8); in intel_master_startup()
1407 dev_dbg(dev, "Multi-link is disabled\n"); in intel_master_startup()
1408 bus->multi_link = false; in intel_master_startup()
1411 * hardware-based synchronization is required regardless in intel_master_startup()
1412 * of the number of segments used by a stream: SSP-based in intel_master_startup()
1413 * synchronization is gated by gsync when the multi-master in intel_master_startup()
1416 bus->multi_link = true; in intel_master_startup()
1417 bus->hw_sync_min_links = 1; in intel_master_startup()
1487 clock_stop_quirks = sdw->link_res->clock_stop_quirks; in intel_master_startup()
1504 * there are no Slave devices populated or if the power-on is in intel_master_startup()
1508 * Conditionally force the pm_runtime core to re-evaluate the in intel_master_startup()
1527 struct device *dev = &pdev->dev; in intel_master_remove()
1530 struct sdw_bus *bus = &cdns->bus; in intel_master_remove()
1537 if (!bus->prop.hw_disabled) { in intel_master_remove()
1549 struct device *dev = &pdev->dev; in intel_master_process_wakeen_event()
1556 bus = &sdw->cdns.bus; in intel_master_process_wakeen_event()
1558 if (bus->prop.hw_disabled) { in intel_master_process_wakeen_event()
1559 dev_dbg(dev, "SoundWire master %d is disabled, ignoring\n", bus->link_id); in intel_master_process_wakeen_event()
1563 shim = sdw->link_res->shim; in intel_master_process_wakeen_event()
1566 if (!(wake_sts & BIT(sdw->instance))) in intel_master_process_wakeen_event()
1573 * resume the Master, which will generate a bus reset and result in in intel_master_process_wakeen_event()
1574 * Slaves re-attaching and be re-enumerated. The SoundWire physical in intel_master_process_wakeen_event()
1594 struct sdw_bus *bus = &cdns->bus; in intel_suspend()
1598 if (bus->prop.hw_disabled) { in intel_suspend()
1600 bus->link_id); in intel_suspend()
1607 clock_stop_quirks = sdw->link_res->clock_stop_quirks; in intel_suspend()
1611 !pm_runtime_suspended(dev->parent)) { in intel_suspend()
1648 struct sdw_bus *bus = &cdns->bus; in intel_suspend_runtime()
1652 if (bus->prop.hw_disabled) { in intel_suspend_runtime()
1654 bus->link_id); in intel_suspend_runtime()
1658 clock_stop_quirks = sdw->link_res->clock_stop_quirks; in intel_suspend_runtime()
1700 ret = -EINVAL; in intel_suspend_runtime()
1710 struct sdw_bus *bus = &cdns->bus; in intel_resume()
1715 if (bus->prop.hw_disabled) { in intel_resume()
1717 bus->link_id); in intel_resume()
1721 link_flags = md_flags >> (bus->link_id * 8); in intel_resume()
1733 link_flags = md_flags >> (bus->link_id * 8); in intel_resume()
1753 dev_err(dev, "cannot enable interrupts during resume\n"); in intel_resume()
1764 ret = sdw_cdns_init(&sdw->cdns); in intel_resume()
1766 dev_err(dev, "unable to initialize Cadence IP during resume\n"); in intel_resume()
1772 dev_err(dev, "unable to exit bus reset sequence during resume\n"); in intel_resume()
1779 dev_err(dev, "sync go failed during resume\n"); in intel_resume()
1785 * after system resume, the pm_runtime suspend() may kick in in intel_resume()
1803 struct sdw_bus *bus = &cdns->bus; in intel_resume_runtime()
1811 if (bus->prop.hw_disabled) { in intel_resume_runtime()
1813 bus->link_id); in intel_resume_runtime()
1817 link_flags = md_flags >> (bus->link_id * 8); in intel_resume_runtime()
1820 clock_stop_quirks = sdw->link_res->clock_stop_quirks; in intel_resume_runtime()
1837 dev_err(dev, "cannot enable interrupts during resume\n"); in intel_resume_runtime()
1848 ret = sdw_cdns_init(&sdw->cdns); in intel_resume_runtime()
1850 dev_err(dev, "unable to initialize Cadence IP during resume\n"); in intel_resume_runtime()
1856 dev_err(dev, "unable to exit bus reset sequence during resume\n"); in intel_resume_runtime()
1863 dev_err(dev, "sync go failed during resume\n"); in intel_resume_runtime()
1881 clock_stop0 = sdw_cdns_is_clock_stop(&sdw->cdns); in intel_resume_runtime()
1895 dev_err(dev, "cannot enable interrupts during resume\n"); in intel_resume_runtime()
1907 * Re-initialize the IP since it was powered-off in intel_resume_runtime()
1909 sdw_cdns_init(&sdw->cdns); in intel_resume_runtime()
1914 dev_err(dev, "cannot enable interrupts during resume\n"); in intel_resume_runtime()
1921 dev_err(dev, "unable to restart clock during resume\n"); in intel_resume_runtime()
1928 dev_err(dev, "unable to exit bus reset sequence during resume\n"); in intel_resume_runtime()
1935 dev_err(sdw->cdns.dev, "sync go failed during resume\n"); in intel_resume_runtime()
1942 clock_stop0 = sdw_cdns_is_clock_stop(&sdw->cdns); in intel_resume_runtime()
1954 dev_err(dev, "cannot enable interrupts during resume\n"); in intel_resume_runtime()
1960 dev_err(dev, "unable to resume master during resume\n"); in intel_resume_runtime()
1966 ret = -EINVAL; in intel_resume_runtime()
1983 .name = "intel-sdw",
1991 MODULE_ALIAS("platform:intel-sdw");