Lines Matching full:coreclk
103 * @coreclk: core clock frequency
111 u32 coreclk; member
296 u32 refclk, coreclk, mcuclk, inte, deci; in xvcu_set_vcu_pll_info() local
305 coreclk = xvcu_read(xvcu->logicore_reg_ba, VCU_CORE_CLK) * MHZ; in xvcu_set_vcu_pll_info()
307 if (!mcuclk || !coreclk) { in xvcu_set_vcu_pll_info()
314 dev_dbg(xvcu->dev, "Core clock from logicoreIP is %uHz\n", coreclk); in xvcu_set_vcu_pll_info()
351 mod = pll_clk % coreclk; in xvcu_set_vcu_pll_info()
353 divisor_core = pll_clk / coreclk; in xvcu_set_vcu_pll_info()
354 } else if (coreclk - mod < LIMIT) { in xvcu_set_vcu_pll_info()
355 divisor_core = pll_clk / coreclk; in xvcu_set_vcu_pll_info()
377 xvcu->coreclk = pll_clk / divisor_core; in xvcu_set_vcu_pll_info()
380 dev_dbg(xvcu->dev, "Actual Core clock freq is %uHz\n", xvcu->coreclk); in xvcu_set_vcu_pll_info()