brcmstb/pm/pm-arm.c

6  * S3: power off all of the chip except the Always ON (AON) island; keep DDR is
8  * S5: (a.k.a. S3 cold boot) much like S3, except DDR is powered down, so we
368  * from SRAM, in order to allow DDR to come back up safely before we continue.
579 		.compatible = "brcm,brcmstb-ddr-phy-v71.1",
583 		.compatible = "brcm,brcmstb-ddr-phy-v72.0",
587 		.compatible = "brcm,brcmstb-ddr-phy-v225.1",
591 		.compatible = "brcm,brcmstb-ddr-phy-v240.1",
596 		.compatible = "brcm,brcmstb-ddr-phy-v240.2",
617 	{ .compatible = "brcm,brcmstb-ddr-shimphy-v1.0" },
623 		.compatible = "brcm,brcmstb-memc-ddr-rev-b.2.1",
627 		.compatible = "brcm,brcmstb-memc-ddr-rev-b.2.2",
631 		.compatible = "brcm,brcmstb-memc-ddr-rev-b.2.3",
635 		.compatible = "brcm,brcmstb-memc-ddr-rev-b.3.0",
639 		.compatible = "brcm,brcmstb-memc-ddr-rev-b.3.1",
643 		.compatible = "brcm,brcmstb-memc-ddr",
706 	/* DDR PHY registers */  in brcmstb_pm_probe()
710 		pr_err("error mapping DDR PHY\n");  in brcmstb_pm_probe()
715 	/* Only need DDR PHY 0 for now? */  in brcmstb_pm_probe()
727 	/* DDR SHIM-PHY registers */  in brcmstb_pm_probe()
740 			pr_err("error mapping DDR SHIMPHY %d\n", i);  in brcmstb_pm_probe()
752 			pr_err("error mapping DDR Sequencer %d\n", i);  in brcmstb_pm_probe()
764 		/* Adjust warm boot offset based on the DDR sequencer */  in brcmstb_pm_probe()