Lines Matching +full:0 +full:x1100000
18 #define MN_WIN(addr) (((addr & 0x1fc0000) >> 1) | ((addr >> 25) & 0x3ff))
19 #define OCM_WIN(addr) (((addr & 0x1ff0000) >> 1) | ((addr >> 25) & 0x3ff))
20 #define MS_WIN(addr) (addr & 0x0ffc0000)
21 #define QLA82XX_PCI_MN_2M (0)
22 #define QLA82XX_PCI_MS_2M (0x80000)
23 #define QLA82XX_PCI_OCM0_2M (0xc0000)
24 #define VALID_OCM_ADDR(addr) (((addr) & 0x3f800) != 0x3f800)
28 #define CRB_BLK(off) ((off >> 20) & 0x3f)
29 #define CRB_SUBBLK(off) ((off >> 16) & 0xf)
30 #define CRB_WINDOW_2M (0x130060)
32 ((off) & 0xf0000))
33 #define QLA82XX_PCI_CAMQM_2M_END (0x04800800UL)
34 #define QLA82XX_PCI_CAMQM_2M_BASE (0x000ff800UL)
35 #define CRB_INDIRECT_2M (0x1e0000UL)
47 static const int MD_MIU_TEST_AGT_RDDATA[] = { 0x410000A8,
48 0x410000AC, 0x410000B8, 0x410000BC };
115 {{{0, 0, 0, 0} } }, /* 0: PCI */
116 {{{1, 0x0100000, 0x0102000, 0x120000}, /* 1: PCIE */
117 {1, 0x0110000, 0x0120000, 0x130000},
118 {1, 0x0120000, 0x0122000, 0x124000},
119 {1, 0x0130000, 0x0132000, 0x126000},
120 {1, 0x0140000, 0x0142000, 0x128000},
121 {1, 0x0150000, 0x0152000, 0x12a000},
122 {1, 0x0160000, 0x0170000, 0x110000},
123 {1, 0x0170000, 0x0172000, 0x12e000},
124 {0, 0x0000000, 0x0000000, 0x000000},
125 {0, 0x0000000, 0x0000000, 0x000000},
126 {0, 0x0000000, 0x0000000, 0x000000},
127 {0, 0x0000000, 0x0000000, 0x000000},
128 {0, 0x0000000, 0x0000000, 0x000000},
129 {0, 0x0000000, 0x0000000, 0x000000},
130 {1, 0x01e0000, 0x01e0800, 0x122000},
131 {0, 0x0000000, 0x0000000, 0x000000} } },
132 {{{1, 0x0200000, 0x0210000, 0x180000} } },/* 2: MN */
133 {{{0, 0, 0, 0} } }, /* 3: */
134 {{{1, 0x0400000, 0x0401000, 0x169000} } },/* 4: P2NR1 */
135 {{{1, 0x0500000, 0x0510000, 0x140000} } },/* 5: SRE */
136 {{{1, 0x0600000, 0x0610000, 0x1c0000} } },/* 6: NIU */
137 {{{1, 0x0700000, 0x0704000, 0x1b8000} } },/* 7: QM */
138 {{{1, 0x0800000, 0x0802000, 0x170000}, /* 8: SQM0 */
139 {0, 0x0000000, 0x0000000, 0x000000},
140 {0, 0x0000000, 0x0000000, 0x000000},
141 {0, 0x0000000, 0x0000000, 0x000000},
142 {0, 0x0000000, 0x0000000, 0x000000},
143 {0, 0x0000000, 0x0000000, 0x000000},
144 {0, 0x0000000, 0x0000000, 0x000000},
145 {0, 0x0000000, 0x0000000, 0x000000},
146 {0, 0x0000000, 0x0000000, 0x000000},
147 {0, 0x0000000, 0x0000000, 0x000000},
148 {0, 0x0000000, 0x0000000, 0x000000},
149 {0, 0x0000000, 0x0000000, 0x000000},
150 {0, 0x0000000, 0x0000000, 0x000000},
151 {0, 0x0000000, 0x0000000, 0x000000},
152 {0, 0x0000000, 0x0000000, 0x000000},
153 {1, 0x08f0000, 0x08f2000, 0x172000} } },
154 {{{1, 0x0900000, 0x0902000, 0x174000}, /* 9: SQM1*/
155 {0, 0x0000000, 0x0000000, 0x000000},
156 {0, 0x0000000, 0x0000000, 0x000000},
157 {0, 0x0000000, 0x0000000, 0x000000},
158 {0, 0x0000000, 0x0000000, 0x000000},
159 {0, 0x0000000, 0x0000000, 0x000000},
160 {0, 0x0000000, 0x0000000, 0x000000},
161 {0, 0x0000000, 0x0000000, 0x000000},
162 {0, 0x0000000, 0x0000000, 0x000000},
163 {0, 0x0000000, 0x0000000, 0x000000},
164 {0, 0x0000000, 0x0000000, 0x000000},
165 {0, 0x0000000, 0x0000000, 0x000000},
166 {0, 0x0000000, 0x0000000, 0x000000},
167 {0, 0x0000000, 0x0000000, 0x000000},
168 {0, 0x0000000, 0x0000000, 0x000000},
169 {1, 0x09f0000, 0x09f2000, 0x176000} } },
170 {{{0, 0x0a00000, 0x0a02000, 0x178000}, /* 10: SQM2*/
171 {0, 0x0000000, 0x0000000, 0x000000},
172 {0, 0x0000000, 0x0000000, 0x000000},
173 {0, 0x0000000, 0x0000000, 0x000000},
174 {0, 0x0000000, 0x0000000, 0x000000},
175 {0, 0x0000000, 0x0000000, 0x000000},
176 {0, 0x0000000, 0x0000000, 0x000000},
177 {0, 0x0000000, 0x0000000, 0x000000},
178 {0, 0x0000000, 0x0000000, 0x000000},
179 {0, 0x0000000, 0x0000000, 0x000000},
180 {0, 0x0000000, 0x0000000, 0x000000},
181 {0, 0x0000000, 0x0000000, 0x000000},
182 {0, 0x0000000, 0x0000000, 0x000000},
183 {0, 0x0000000, 0x0000000, 0x000000},
184 {0, 0x0000000, 0x0000000, 0x000000},
185 {1, 0x0af0000, 0x0af2000, 0x17a000} } },
186 {{{0, 0x0b00000, 0x0b02000, 0x17c000}, /* 11: SQM3*/
187 {0, 0x0000000, 0x0000000, 0x000000},
188 {0, 0x0000000, 0x0000000, 0x000000},
189 {0, 0x0000000, 0x0000000, 0x000000},
190 {0, 0x0000000, 0x0000000, 0x000000},
191 {0, 0x0000000, 0x0000000, 0x000000},
192 {0, 0x0000000, 0x0000000, 0x000000},
193 {0, 0x0000000, 0x0000000, 0x000000},
194 {0, 0x0000000, 0x0000000, 0x000000},
195 {0, 0x0000000, 0x0000000, 0x000000},
196 {0, 0x0000000, 0x0000000, 0x000000},
197 {0, 0x0000000, 0x0000000, 0x000000},
198 {0, 0x0000000, 0x0000000, 0x000000},
199 {0, 0x0000000, 0x0000000, 0x000000},
200 {0, 0x0000000, 0x0000000, 0x000000},
201 {1, 0x0bf0000, 0x0bf2000, 0x17e000} } },
202 {{{1, 0x0c00000, 0x0c04000, 0x1d4000} } },/* 12: I2Q */
203 {{{1, 0x0d00000, 0x0d04000, 0x1a4000} } },/* 13: TMR */
204 {{{1, 0x0e00000, 0x0e04000, 0x1a0000} } },/* 14: ROMUSB */
205 {{{1, 0x0f00000, 0x0f01000, 0x164000} } },/* 15: PEG4 */
206 {{{0, 0x1000000, 0x1004000, 0x1a8000} } },/* 16: XDMA */
207 {{{1, 0x1100000, 0x1101000, 0x160000} } },/* 17: PEG0 */
208 {{{1, 0x1200000, 0x1201000, 0x161000} } },/* 18: PEG1 */
209 {{{1, 0x1300000, 0x1301000, 0x162000} } },/* 19: PEG2 */
210 {{{1, 0x1400000, 0x1401000, 0x163000} } },/* 20: PEG3 */
211 {{{1, 0x1500000, 0x1501000, 0x165000} } },/* 21: P2ND */
212 {{{1, 0x1600000, 0x1601000, 0x166000} } },/* 22: P2NI */
213 {{{0, 0, 0, 0} } }, /* 23: */
214 {{{0, 0, 0, 0} } }, /* 24: */
215 {{{0, 0, 0, 0} } }, /* 25: */
216 {{{0, 0, 0, 0} } }, /* 26: */
217 {{{0, 0, 0, 0} } }, /* 27: */
218 {{{0, 0, 0, 0} } }, /* 28: */
219 {{{1, 0x1d00000, 0x1d10000, 0x190000} } },/* 29: MS */
220 {{{1, 0x1e00000, 0x1e01000, 0x16a000} } },/* 30: P2NR2 */
221 {{{1, 0x1f00000, 0x1f10000, 0x150000} } },/* 31: EPG */
222 {{{0} } }, /* 32: PCI */
223 {{{1, 0x2100000, 0x2102000, 0x120000}, /* 33: PCIE */
224 {1, 0x2110000, 0x2120000, 0x130000},
225 {1, 0x2120000, 0x2122000, 0x124000},
226 {1, 0x2130000, 0x2132000, 0x126000},
227 {1, 0x2140000, 0x2142000, 0x128000},
228 {1, 0x2150000, 0x2152000, 0x12a000},
229 {1, 0x2160000, 0x2170000, 0x110000},
230 {1, 0x2170000, 0x2172000, 0x12e000},
231 {0, 0x0000000, 0x0000000, 0x000000},
232 {0, 0x0000000, 0x0000000, 0x000000},
233 {0, 0x0000000, 0x0000000, 0x000000},
234 {0, 0x0000000, 0x0000000, 0x000000},
235 {0, 0x0000000, 0x0000000, 0x000000},
236 {0, 0x0000000, 0x0000000, 0x000000},
237 {0, 0x0000000, 0x0000000, 0x000000},
238 {0, 0x0000000, 0x0000000, 0x000000} } },
239 {{{1, 0x2200000, 0x2204000, 0x1b0000} } },/* 34: CAM */
240 {{{0} } }, /* 35: */
241 {{{0} } }, /* 36: */
242 {{{0} } }, /* 37: */
243 {{{0} } }, /* 38: */
244 {{{0} } }, /* 39: */
245 {{{1, 0x2800000, 0x2804000, 0x1a4000} } },/* 40: TMR */
246 {{{1, 0x2900000, 0x2901000, 0x16b000} } },/* 41: P2NR3 */
247 {{{1, 0x2a00000, 0x2a00400, 0x1ac400} } },/* 42: RPMX1 */
248 {{{1, 0x2b00000, 0x2b00400, 0x1ac800} } },/* 43: RPMX2 */
249 {{{1, 0x2c00000, 0x2c00400, 0x1acc00} } },/* 44: RPMX3 */
250 {{{1, 0x2d00000, 0x2d00400, 0x1ad000} } },/* 45: RPMX4 */
251 {{{1, 0x2e00000, 0x2e00400, 0x1ad400} } },/* 46: RPMX5 */
252 {{{1, 0x2f00000, 0x2f00400, 0x1ad800} } },/* 47: RPMX6 */
253 {{{1, 0x3000000, 0x3000400, 0x1adc00} } },/* 48: RPMX7 */
254 {{{0, 0x3100000, 0x3104000, 0x1a8000} } },/* 49: XDMA */
255 {{{1, 0x3200000, 0x3204000, 0x1d4000} } },/* 50: I2Q */
256 {{{1, 0x3300000, 0x3304000, 0x1a0000} } },/* 51: ROMUSB */
257 {{{0} } }, /* 52: */
258 {{{1, 0x3500000, 0x3500400, 0x1ac000} } },/* 53: RPMX0 */
259 {{{1, 0x3600000, 0x3600400, 0x1ae000} } },/* 54: RPMX8 */
260 {{{1, 0x3700000, 0x3700400, 0x1ae400} } },/* 55: RPMX9 */
261 {{{1, 0x3800000, 0x3804000, 0x1d0000} } },/* 56: OCM0 */
262 {{{1, 0x3900000, 0x3904000, 0x1b4000} } },/* 57: CRYPTO */
263 {{{1, 0x3a00000, 0x3a04000, 0x1d8000} } },/* 58: SMB */
264 {{{0} } }, /* 59: I2C0 */
265 {{{0} } }, /* 60: I2C1 */
266 {{{1, 0x3d00000, 0x3d04000, 0x1dc000} } },/* 61: LPC */
267 {{{1, 0x3e00000, 0x3e01000, 0x167000} } },/* 62: P2NC */
268 {{{1, 0x3f00000, 0x3f01000, 0x168000} } } /* 63: P2NR0 */
275 0,
279 0,
302 0,
305 0,
307 0,
310 0,
311 0,
312 0,
313 0,
314 0,
316 0,
327 0,
332 0,
336 0,
338 0,
372 "%s: Written crbwin (0x%x) != Read crbwin (0x%x)," in qla4_82xx_pci_set_crbwindow_2M()
373 " off=0x%lx\n", __func__, ha->crb_win, win_read, *off)); in qla4_82xx_pci_set_crbwindow_2M()
381 unsigned long flags = 0; in qla4_82xx_wr_32()
404 unsigned long flags = 0; in qla4_82xx_rd_32()
432 off_value = off & 0xFFFF0000; in qla4_82xx_md_rd_32()
442 "%s: Written (0x%x) != Read (0x%x), off=0x%x\n", in qla4_82xx_md_rd_32()
446 off_value = off & 0x0000FFFF; in qla4_82xx_md_rd_32()
458 off_value = off & 0xFFFF0000; in qla4_82xx_md_wr_32()
467 "%s: Written (0x%x) != Read (0x%x), off=0x%x\n", in qla4_82xx_md_wr_32()
471 off_value = off & 0x0000FFFF; in qla4_82xx_md_wr_32()
483 int done = 0, timeout = 0; in qla4_82xx_crb_win_lock()
499 for (i = 0; i < 20; i++) in qla4_82xx_crb_win_lock()
504 return 0; in qla4_82xx_crb_win_lock()
524 int done = 0, timeout = 0; in qla4_82xx_idc_lock()
540 for (i = 0; i < 20; i++) in qla4_82xx_idc_lock()
544 return 0; in qla4_82xx_idc_lock()
563 return 0; in qla4_82xx_pci_get_crb_addr_2M()
578 return 0; in qla4_82xx_pci_get_crb_addr_2M()
600 return 0; in qla4_82xx_pci_mem_bound_check()
624 "%s: Written MNwin (0x%x) != Read MNwin (0x%x)\n", in qla4_82xx_pci_set_window()
632 if ((addr & 0x00ff800) == 0xff800) { in qla4_82xx_pci_set_window()
643 temp1 = ((window & 0x1FF) << 7) | in qla4_82xx_pci_set_window()
644 ((window & 0x0FFFE0000) >> 17); in qla4_82xx_pci_set_window()
646 printk("%s: Written OCMwin (0x%x) != Read" in qla4_82xx_pci_set_window()
647 " OCMwin (0x%x)\n", __func__, temp1, win_read); in qla4_82xx_pci_set_window()
661 printk("%s: Written MSwin (0x%x) != Read " in qla4_82xx_pci_set_window()
662 "MSwin (0x%x)\n", __func__, window, win_read); in qla4_82xx_pci_set_window()
672 (qla4_82xx_pci_set_window_warning_count%64 == 0)) { in qla4_82xx_pci_set_window()
703 window = ((addr - QLA8XXX_ADDR_QDR_NET) >> 22) & 0x3f; in qla4_82xx_pci_is_same_window()
708 return 0; in qla4_82xx_pci_is_same_window()
716 int ret = 0; in qla4_82xx_pci_mem_read_direct()
730 (qla4_82xx_pci_is_same_window(ha, off + size - 1) == 0)) { in qla4_82xx_pci_mem_read_direct()
733 "offset is 0x%llx\n", DRIVER_NAME, off); in qla4_82xx_pci_mem_read_direct()
740 mem_base = pci_resource_start(ha->pdev, 0); in qla4_82xx_pci_mem_read_direct()
751 *(u8 *)data = 0; in qla4_82xx_pci_mem_read_direct()
789 int ret = 0; in qla4_82xx_pci_mem_write_direct()
803 (qla4_82xx_pci_is_same_window(ha, off + size - 1) == 0)) { in qla4_82xx_pci_mem_write_direct()
806 "offset is 0x%llx\n", DRIVER_NAME, off); in qla4_82xx_pci_mem_write_direct()
813 mem_base = pci_resource_start(ha->pdev, 0); in qla4_82xx_pci_mem_write_direct()
865 base_addr = addr & 0xfff00000; in qla4_82xx_decode_crb_addr()
866 offset = addr & 0x000fffff; in qla4_82xx_decode_crb_addr()
868 for (i = 0; i < MAX_CRB_XFORM; i++) { in qla4_82xx_decode_crb_addr()
887 int done = 0, timeout = 0; in qla4_82xx_rom_lock()
904 for (i = 0; i < 20; i++) in qla4_82xx_rom_lock()
909 return 0; in qla4_82xx_rom_lock()
921 long timeout = 0; in qla4_82xx_wait_rom_done()
922 long done = 0 ; in qla4_82xx_wait_rom_done()
924 while (done == 0) { in qla4_82xx_wait_rom_done()
934 return 0; in qla4_82xx_wait_rom_done()
941 qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_DUMMY_BYTE_CNT, 0); in qla4_82xx_do_rom_fast_read()
943 qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, 0xb); in qla4_82xx_do_rom_fast_read()
949 qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_DUMMY_BYTE_CNT, 0); in qla4_82xx_do_rom_fast_read()
951 qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 0); in qla4_82xx_do_rom_fast_read()
954 return 0; in qla4_82xx_do_rom_fast_read()
960 int ret, loops = 0; in qla4_82xx_rom_fast_read()
962 while ((qla4_82xx_rom_lock(ha) != 0) && (loops < 50000)) { in qla4_82xx_rom_fast_read()
998 qla4_82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x10, 0x0); in qla4_82xx_pinit_from_rom()
999 qla4_82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x14, 0x0); in qla4_82xx_pinit_from_rom()
1000 qla4_82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x18, 0x0); in qla4_82xx_pinit_from_rom()
1001 qla4_82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x1c, 0x0); in qla4_82xx_pinit_from_rom()
1002 qla4_82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x20, 0x0); in qla4_82xx_pinit_from_rom()
1003 qla4_82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x24, 0x0); in qla4_82xx_pinit_from_rom()
1006 qla4_82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x40, 0xff); in qla4_82xx_pinit_from_rom()
1008 qla4_82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x70000, 0x00); in qla4_82xx_pinit_from_rom()
1010 qla4_82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x80000, 0x00); in qla4_82xx_pinit_from_rom()
1012 qla4_82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x90000, 0x00); in qla4_82xx_pinit_from_rom()
1014 qla4_82xx_wr_32(ha, QLA82XX_CRB_NIU + 0xa0000, 0x00); in qla4_82xx_pinit_from_rom()
1016 qla4_82xx_wr_32(ha, QLA82XX_CRB_NIU + 0xb0000, 0x00); in qla4_82xx_pinit_from_rom()
1019 val = qla4_82xx_rd_32(ha, QLA82XX_CRB_SRE + 0x1000); in qla4_82xx_pinit_from_rom()
1020 qla4_82xx_wr_32(ha, QLA82XX_CRB_SRE + 0x1000, val & (~(0x1))); in qla4_82xx_pinit_from_rom()
1023 qla4_82xx_wr_32(ha, QLA82XX_CRB_EPG + 0x1300, 0x1); in qla4_82xx_pinit_from_rom()
1026 qla4_82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x0, 0x0); in qla4_82xx_pinit_from_rom()
1027 qla4_82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x8, 0x0); in qla4_82xx_pinit_from_rom()
1028 qla4_82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x10, 0x0); in qla4_82xx_pinit_from_rom()
1029 qla4_82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x18, 0x0); in qla4_82xx_pinit_from_rom()
1030 qla4_82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x100, 0x0); in qla4_82xx_pinit_from_rom()
1031 qla4_82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x200, 0x0); in qla4_82xx_pinit_from_rom()
1034 qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x3c, 1); in qla4_82xx_pinit_from_rom()
1035 qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1 + 0x3c, 1); in qla4_82xx_pinit_from_rom()
1036 qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2 + 0x3c, 1); in qla4_82xx_pinit_from_rom()
1037 qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3 + 0x3c, 1); in qla4_82xx_pinit_from_rom()
1038 qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_4 + 0x3c, 1); in qla4_82xx_pinit_from_rom()
1044 qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0xfeffffff); in qla4_82xx_pinit_from_rom()
1046 qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0xffffffff); in qla4_82xx_pinit_from_rom()
1051 * Offset 0: Contain signature (0xcafecafe) in qla4_82xx_pinit_from_rom()
1055 if (qla4_82xx_rom_fast_read(ha, 0, &n) != 0 || n != 0xcafecafeUL || in qla4_82xx_pinit_from_rom()
1056 qla4_82xx_rom_fast_read(ha, 4, &n) != 0) { in qla4_82xx_pinit_from_rom()
1065 offset = n & 0xffffU; in qla4_82xx_pinit_from_rom()
1066 n = (n >> 16) & 0xffffU; in qla4_82xx_pinit_from_rom()
1071 "%s: %s:n=0x%x [ERROR] Card flash not initialized.\n", in qla4_82xx_pinit_from_rom()
1086 for (i = 0; i < n; i++) { in qla4_82xx_pinit_from_rom()
1087 if (qla4_82xx_rom_fast_read(ha, 8*i + 4*offset, &val) != 0 || in qla4_82xx_pinit_from_rom()
1089 0) { in qla4_82xx_pinit_from_rom()
1098 for (i = 0; i < n; i++) { in qla4_82xx_pinit_from_rom()
1109 if (off & 0x1) { in qla4_82xx_pinit_from_rom()
1111 "Skip CRB init replay for offset = 0x%lx\n", off)); in qla4_82xx_pinit_from_rom()
1116 if (off == QLA82XX_CAM_RAM(0x1fc)) in qla4_82xx_pinit_from_rom()
1120 if (off == (ROMUSB_GLB + 0xbc)) in qla4_82xx_pinit_from_rom()
1124 if (off == (ROMUSB_GLB + 0xc8)) in qla4_82xx_pinit_from_rom()
1134 if ((off & 0x0ff00000) == QLA82XX_CRB_SMB) in qla4_82xx_pinit_from_rom()
1137 if ((off & 0x0ff00000) == QLA82XX_CRB_DDR_NET) in qla4_82xx_pinit_from_rom()
1142 "%s: [ERROR] Unknown addr: 0x%08lx\n", in qla4_82xx_pinit_from_rom()
1150 * else crb_window returns 0xffffffff in qla4_82xx_pinit_from_rom()
1164 qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_D+0xec, 0x1e); in qla4_82xx_pinit_from_rom()
1165 qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_D+0x4c, 8); in qla4_82xx_pinit_from_rom()
1166 qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_I+0x4c, 8); in qla4_82xx_pinit_from_rom()
1169 qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0+0x8, 0); in qla4_82xx_pinit_from_rom()
1170 qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0+0xc, 0); in qla4_82xx_pinit_from_rom()
1171 qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1+0x8, 0); in qla4_82xx_pinit_from_rom()
1172 qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1+0xc, 0); in qla4_82xx_pinit_from_rom()
1173 qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2+0x8, 0); in qla4_82xx_pinit_from_rom()
1174 qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2+0xc, 0); in qla4_82xx_pinit_from_rom()
1175 qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3+0x8, 0); in qla4_82xx_pinit_from_rom()
1176 qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3+0xc, 0); in qla4_82xx_pinit_from_rom()
1178 return 0; in qla4_82xx_pinit_from_rom()
1200 if (addr & 0xF) { in qla4_8xxx_ms_mem_write_128b()
1208 ret_val = ha->isp_ops->wr_reg_indirect(ha, MD_MIU_TEST_AGT_ADDR_HI, 0); in qla4_8xxx_ms_mem_write_128b()
1215 for (i = 0; i < count; i++, addr += 16) { in qla4_8xxx_ms_mem_write_128b()
1258 for (j = 0; j < MAX_CTL_CHECK; j++) { in qla4_8xxx_ms_mem_write_128b()
1267 if ((agt_ctrl & MIU_TA_CTL_BUSY) == 0) in qla4_8xxx_ms_mem_write_128b()
1290 int i, rval = 0; in qla4_82xx_load_from_flash()
1291 long size = 0; in qla4_82xx_load_from_flash()
1299 DEBUG2(printk("scsi%ld: %s: bootldr=0x%lx, fw_image=0x%x\n", in qla4_82xx_load_from_flash()
1302 for (i = 0; i < size; i++) { in qla4_82xx_load_from_flash()
1317 if (i % 0x1000 == 0) in qla4_82xx_load_from_flash()
1325 qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x18, 0x1020); in qla4_82xx_load_from_flash()
1326 qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0x80001e); in qla4_82xx_load_from_flash()
1337 qla4_82xx_wr_32(ha, CRB_CMDPEG_STATE, 0); in qla4_82xx_load_fw()
1338 if (qla4_82xx_pinit_from_rom(ha, 0) != QLA_SUCCESS) { in qla4_82xx_load_fw()
1368 int i, j = 0, k, start, end, loop, sz[2], off0[2]; in qla4_82xx_pci_mem_read_2M()
1371 uint64_t off8, val, mem_crb, word[2] = {0, 0}; in qla4_82xx_pci_mem_read_2M()
1381 if (qla4_82xx_pci_mem_bound_check(ha, off, size) == 0) in qla4_82xx_pci_mem_read_2M()
1387 off8 = off & 0xfffffff0; in qla4_82xx_pci_mem_read_2M()
1388 off0[0] = off & 0xf; in qla4_82xx_pci_mem_read_2M()
1389 sz[0] = (size < (16 - off0[0])) ? size : (16 - off0[0]); in qla4_82xx_pci_mem_read_2M()
1392 loop = ((off0[0] + size - 1) >> shift_amount) + 1; in qla4_82xx_pci_mem_read_2M()
1393 off0[1] = 0; in qla4_82xx_pci_mem_read_2M()
1394 sz[1] = size - sz[0]; in qla4_82xx_pci_mem_read_2M()
1396 for (i = 0; i < loop; i++) { in qla4_82xx_pci_mem_read_2M()
1399 temp = 0; in qla4_82xx_pci_mem_read_2M()
1406 for (j = 0; j < MAX_CTL_CHECK; j++) { in qla4_82xx_pci_mem_read_2M()
1408 if ((temp & MIU_TA_CTL_BUSY) == 0) in qla4_82xx_pci_mem_read_2M()
1431 if ((off0[0] & 7) == 0) { in qla4_82xx_pci_mem_read_2M()
1432 val = word[0]; in qla4_82xx_pci_mem_read_2M()
1434 val = ((word[0] >> (off0[0] * 8)) & (~(~0ULL << (sz[0] * 8)))) | in qla4_82xx_pci_mem_read_2M()
1435 ((word[1] & (~(~0ULL << (sz[1] * 8)))) << (sz[0] * 8)); in qla4_82xx_pci_mem_read_2M()
1452 return 0; in qla4_82xx_pci_mem_read_2M()
1459 int i, j, ret = 0, loop, sz[2], off0; in qla4_82xx_pci_mem_write_2M()
1462 uint64_t off8, mem_crb, tmpw, word[2] = {0, 0}; in qla4_82xx_pci_mem_write_2M()
1471 if (qla4_82xx_pci_mem_bound_check(ha, off, size) == 0) in qla4_82xx_pci_mem_write_2M()
1476 off0 = off & 0x7; in qla4_82xx_pci_mem_write_2M()
1477 sz[0] = (size < (8 - off0)) ? size : (8 - off0); in qla4_82xx_pci_mem_write_2M()
1478 sz[1] = size - sz[0]; in qla4_82xx_pci_mem_write_2M()
1480 off8 = off & 0xfffffff0; in qla4_82xx_pci_mem_write_2M()
1481 loop = (((off & 0xf) + size - 1) >> 4) + 1; in qla4_82xx_pci_mem_write_2M()
1484 startword = (off & 0xf)/8; in qla4_82xx_pci_mem_write_2M()
1486 for (i = 0; i < loop; i++) { in qla4_82xx_pci_mem_write_2M()
1508 if (sz[0] == 8) in qla4_82xx_pci_mem_write_2M()
1512 ~((~(~0ULL << (sz[0] * 8))) << (off0 * 8)); in qla4_82xx_pci_mem_write_2M()
1516 if (sz[1] != 0) { in qla4_82xx_pci_mem_write_2M()
1517 word[startword+1] &= ~(~0ULL << (sz[1] * 8)); in qla4_82xx_pci_mem_write_2M()
1518 word[startword+1] |= tmpw >> (sz[0] * 8); in qla4_82xx_pci_mem_write_2M()
1521 for (i = 0; i < loop; i++) { in qla4_82xx_pci_mem_write_2M()
1524 temp = 0; in qla4_82xx_pci_mem_write_2M()
1526 temp = word[i * scale] & 0xffffffff; in qla4_82xx_pci_mem_write_2M()
1528 temp = (word[i * scale] >> 32) & 0xffffffff; in qla4_82xx_pci_mem_write_2M()
1530 temp = word[i*scale + 1] & 0xffffffff; in qla4_82xx_pci_mem_write_2M()
1533 temp = (word[i*scale + 1] >> 32) & 0xffffffff; in qla4_82xx_pci_mem_write_2M()
1542 for (j = 0; j < MAX_CTL_CHECK; j++) { in qla4_82xx_pci_mem_write_2M()
1544 if ((temp & MIU_TA_CTL_BUSY) == 0) in qla4_82xx_pci_mem_write_2M()
1563 u32 val = 0; in qla4_82xx_cmdpeg_ready()
1571 return 0; in qla4_82xx_cmdpeg_ready()
1585 return 0; in qla4_82xx_cmdpeg_ready()
1590 uint32_t state = 0; in qla4_82xx_rcvpeg_ready()
1591 int loops = 0; in qla4_82xx_rcvpeg_ready()
1610 "Receive Peg initialization not complete: 0x%x.\n", state)); in qla4_82xx_rcvpeg_ready()
1634 ql4_printk(KERN_INFO, ha, "%s(%ld): drv_active: 0x%08x\n", in qla4_8xxx_set_drv_active()
1656 ql4_printk(KERN_INFO, ha, "%s(%ld): drv_active: 0x%08x\n", in qla4_8xxx_clear_drv_active()
1701 ql4_printk(KERN_INFO, ha, "%s(%ld): drv_state: 0x%08x\n", in qla4_8xxx_set_rst_ready()
1722 ql4_printk(KERN_INFO, ha, "%s(%ld): drv_state: 0x%08x\n", in qla4_8xxx_clear_rst_ready()
1754 qla4_82xx_wr_32(ha, CRB_DMA_SHIFT, 0x55555555); in qla4_82xx_start_firmware()
1757 qla4_82xx_wr_32(ha, CRB_CMDPEG_STATE, 0); in qla4_82xx_start_firmware()
1758 qla4_82xx_wr_32(ha, CRB_RCVPEG_STATE, 0); in qla4_82xx_start_firmware()
1759 qla4_82xx_wr_32(ha, QLA82XX_PEG_HALT_STATUS1, 0); in qla4_82xx_start_firmware()
1760 qla4_82xx_wr_32(ha, QLA82XX_PEG_HALT_STATUS2, 0); in qla4_82xx_start_firmware()
1768 if (qla4_82xx_cmdpeg_ready(ha, 0) != QLA_SUCCESS) { in qla4_82xx_start_firmware()
1775 ha->link_width = (lnk >> 4) & 0x3f; in qla4_82xx_start_firmware()
1835 if ((temp & mask) != 0) in ql4_84xx_poll_wait_for_ready()
1859 temp = (0x40000000 | addr); in ql4_84xx_ipmdio_rd_reg()
1887 if ((temp & 0x1) != 1) in ql4_84xx_poll_wait_ipmdio_bus_idle()
1934 for (i = 0; i < loop_cnt; i++) { in qla4_8xxx_minidump_process_rdcrb()
1946 uint32_t dma_eng_num = 0, cmd_sts_and_cntrl = 0; in qla4_83xx_check_dma_engine_state()
1947 uint64_t dma_base_addr = 0; in qla4_83xx_check_dma_engine_state()
1975 int rval = QLA_SUCCESS, wait = 0; in qla4_83xx_start_pex_dma()
1976 uint32_t dma_eng_num = 0, cmd_sts_and_cntrl = 0; in qla4_83xx_start_pex_dma()
1977 uint64_t dma_base_addr = 0; in qla4_83xx_start_pex_dma()
1994 dma_base_addr + QLA83XX_PEX_DMA_CMD_ADDR_HIGH, 0); in qla4_83xx_start_pex_dma()
2005 for (wait = 0; wait < QLA83XX_PEX_DMA_MAX_WAIT; wait++) { in qla4_83xx_start_pex_dma()
2012 if ((cmd_sts_and_cntrl & BIT_1) == 0) in qla4_83xx_start_pex_dma()
2063 * 0-3: dma-desc-cmd 0-3 in qla4_8xxx_minidump_pex_dma_read()
2067 dma_desc.cmd.dma_desc_cmd = (m_hdr->dma_desc_cmd & 0xff0f); in qla4_8xxx_minidump_pex_dma_read()
2068 dma_desc.cmd.dma_desc_cmd |= ((PCI_FUNC(ha->pdev->devfn) & 0xf) << 0x4); in qla4_8xxx_minidump_pex_dma_read()
2071 size = 0; in qla4_8xxx_minidump_pex_dma_read()
2072 read_size = 0; in qla4_8xxx_minidump_pex_dma_read()
2117 "%s: Dma-desc: Instruct for rdmem dma (size 0x%x).\n", in qla4_8xxx_minidump_pex_dma_read()
2123 "scsi(%ld): start-pex-dma failed rval=0x%x\n", in qla4_8xxx_minidump_pex_dma_read()
2171 for (i = 0; i < loop_count; i++) { in qla4_8xxx_minidump_process_l2tag()
2182 if ((c_value_r & p_mask) == 0) { in qla4_8xxx_minidump_process_l2tag()
2192 for (k = 0; k < r_cnt; k++) { in qla4_8xxx_minidump_process_l2tag()
2220 for (i = 0; i < crb_entry->op_count; i++) { in qla4_8xxx_minidump_process_control()
2336 "[%s]: r_addr: 0x%x, r_stride: 0x%x, loop_cnt: 0x%x\n", in qla4_8xxx_minidump_process_rdocm()
2339 for (i = 0; i < loop_cnt; i++) { in qla4_8xxx_minidump_process_rdocm()
2344 DEBUG2(ql4_printk(KERN_INFO, ha, "Leaving fn: %s datacount: 0x%lx\n", in qla4_8xxx_minidump_process_rdocm()
2365 for (i = 0; i < loop_cnt; i++) { in qla4_8xxx_minidump_process_rdmux()
2395 for (i = 0; i < loop_count; i++) { in qla4_8xxx_minidump_process_l1cache()
2399 for (k = 0; k < r_cnt; k++) { in qla4_8xxx_minidump_process_l1cache()
2414 uint32_t r_stride, r_value, r_cnt, qid = 0; in qla4_8xxx_minidump_process_queue()
2426 for (i = 0; i < loop_cnt; i++) { in qla4_8xxx_minidump_process_queue()
2429 for (k = 0; k < r_cnt; k++) { in qla4_8xxx_minidump_process_queue()
2439 #define MD_DIRECT_ROM_WINDOW 0x42110030
2440 #define MD_DIRECT_ROM_READ_BASE 0x42150000
2457 "[%s]: flash_addr: 0x%x, read_data_size: 0x%x\n", in qla4_82xx_minidump_process_rdrom()
2460 for (i = 0; i < loop_cnt; i++) { in qla4_82xx_minidump_process_rdrom()
2462 (r_addr & 0xFFFF0000)); in qla4_82xx_minidump_process_rdrom()
2464 MD_DIRECT_ROM_READ_BASE + (r_addr & 0x0000FFFF), in qla4_82xx_minidump_process_rdrom()
2472 #define MD_MIU_TEST_AGT_CTRL 0x41000090
2473 #define MD_MIU_TEST_AGT_ADDR_LO 0x41000094
2474 #define MD_MIU_TEST_AGT_ADDR_HI 0x41000098
2492 "[%s]: Read addr: 0x%x, read_data_size: 0x%x\n", in __qla4_8xxx_minidump_process_rdmem()
2495 if (r_addr & 0xf) { in __qla4_8xxx_minidump_process_rdmem()
2497 "[%s]: Read addr 0x%x not 16 bytes aligned\n", in __qla4_8xxx_minidump_process_rdmem()
2504 "[%s]: Read data[0x%x] not multiple of 16 bytes\n", in __qla4_8xxx_minidump_process_rdmem()
2510 "[%s]: rdmem_addr: 0x%x, read_data_size: 0x%x, loop_cnt: 0x%x\n", in __qla4_8xxx_minidump_process_rdmem()
2514 for (i = 0; i < loop_cnt; i++) { in __qla4_8xxx_minidump_process_rdmem()
2517 r_value = 0; in __qla4_8xxx_minidump_process_rdmem()
2525 for (j = 0; j < MAX_CTL_CHECK; j++) { in __qla4_8xxx_minidump_process_rdmem()
2528 if ((r_value & MIU_TA_CTL_BUSY) == 0) in __qla4_8xxx_minidump_process_rdmem()
2540 for (j = 0; j < 4; j++) { in __qla4_8xxx_minidump_process_rdmem()
2551 DEBUG2(ql4_printk(KERN_INFO, ha, "Leaving fn: %s datacount: 0x%x\n", in __qla4_8xxx_minidump_process_rdmem()
2579 "scsi(%ld): Skipping entry[%d]: ETYPE[0x%x]-ELEVEL[0x%x]\n", in qla4_8xxx_mark_entry_skipped()
2609 for (i = 0; i < le32_to_cpu(pollrd_hdr->op_count); i++) { in qla83xx_minidump_process_pollrd()
2615 if ((r_value & poll_mask) != 0) { in qla83xx_minidump_process_pollrd()
2619 if (--poll_wait == 0) { in qla83xx_minidump_process_pollrd()
2648 uint32_t wait_count = 0; in qla4_84xx_minidump_process_rddfe()
2666 for (loop_cnt = 0x0; loop_cnt < count; loop_cnt++) { in qla4_84xx_minidump_process_rddfe()
2667 ha->isp_ops->wr_reg_indirect(ha, addr1, (0x40000000 | value)); in qla4_84xx_minidump_process_rddfe()
2669 wait_count = 0; in qla4_84xx_minidump_process_rddfe()
2672 if ((temp & mask) != 0) in qla4_84xx_minidump_process_rddfe()
2690 wait_count = 0; in qla4_84xx_minidump_process_rddfe()
2693 if ((temp & mask) != 0) in qla4_84xx_minidump_process_rddfe()
2705 ((0x40000000 | value) + in qla4_84xx_minidump_process_rddfe()
2707 wait_count = 0; in qla4_84xx_minidump_process_rddfe()
2710 if ((temp & mask) != 0) in qla4_84xx_minidump_process_rddfe()
2760 for (loop_cnt = 0; loop_cnt < count; loop_cnt++) { in qla4_84xx_minidump_process_rdmdio()
2780 addr6, 0x2); in qla4_84xx_minidump_process_rdmdio()
2815 uint32_t wait_count = 0; in qla4_84xx_minidump_process_pollwr()
2829 if ((r_value & poll) != 0) in qla4_84xx_minidump_process_pollwr()
2844 wait_count = 0; in qla4_84xx_minidump_process_pollwr()
2848 if ((r_value & poll) != 0) in qla4_84xx_minidump_process_pollwr()
2874 for (i = 0; i < rdmux2_hdr->op_count; i++) { in qla83xx_minidump_process_rdmux2()
2923 if ((r_value & poll_mask) != 0) { in qla83xx_minidump_process_pollrdmwr()
2927 if (--poll_wait == 0) { in qla83xx_minidump_process_pollrdmwr()
2945 if ((r_value & poll_mask) != 0) { in qla83xx_minidump_process_pollrdmwr()
2949 if (--poll_wait == 0) { in qla83xx_minidump_process_pollrdmwr()
2978 DEBUG2(ql4_printk(KERN_INFO, ha, "[%s]: fl_addr: 0x%x, count: 0x%x\n", in qla4_83xx_minidump_process_rdrom()
3003 int num_entry_hdr = 0; in qla4_8xxx_collect_md_data()
3007 uint32_t data_collected = 0; in qla4_8xxx_collect_md_data()
3012 ha->fw_dump_skip_size = 0; in qla4_8xxx_collect_md_data()
3029 "[%s]: no of entry headers in Template: 0x%x\n", in qla4_8xxx_collect_md_data()
3031 ql4_printk(KERN_INFO, ha, "[%s]: Capture Mask obtained: 0x%x\n", in qla4_8xxx_collect_md_data()
3033 ql4_printk(KERN_INFO, ha, "[%s]: Total_data_size 0x%x, %d obtained\n", in qla4_8xxx_collect_md_data()
3050 for (i = 0; i < num_entry_hdr; i++) { in qla4_8xxx_collect_md_data()
3053 "Data collected: [0x%x], Total Dump size: [0x%x]\n", in qla4_8xxx_collect_md_data()
3066 "Data collected: [0x%x], Dump size left:[0x%x]\n", in qla4_8xxx_collect_md_data()
3204 "Dump data mismatch: Data collected: [0x%x], total_data_size:[0x%x]\n", in qla4_8xxx_collect_md_data()
3210 DEBUG2(ql4_printk(KERN_INFO, ha, "Leaving fn: %s Last entry: 0x%x\n", in qla4_8xxx_collect_md_data()
3264 int need_reset = 0; in qla4_8xxx_device_bootstrap()
3274 for (i = 0; i < 10; i++) { in qla4_8xxx_device_bootstrap()
3324 uint32_t active_mask = 0xFFFFFFFF; in qla4_82xx_need_reset_handler()
3352 "%s(%ld): drv_state = 0x%x, drv_active = 0x%x\n", in qla4_82xx_need_reset_handler()
3358 "%s: RESET TIMEOUT! drv_state: 0x%08x, drv_active: 0x%08x\n", in qla4_82xx_need_reset_handler()
3369 "%s(%ld): drv_state = 0x%x, drv_active = 0x%x\n", in qla4_82xx_need_reset_handler()
3385 ql4_printk(KERN_INFO, ha, "Device state is 0x%x = %s\n", dev_state, in qla4_82xx_need_reset_handler()
3439 idc_ver &= (~0xFF); in qla4_83xx_set_idc_ver()
3447 idc_ver &= 0xFF; in qla4_83xx_set_idc_ver()
3460 idc_ver &= ~(0x03 << (ha->func_num * 2)); in qla4_83xx_set_idc_ver()
3520 DEBUG2(ql4_printk(KERN_INFO, ha, "Device state is 0x%x = %s\n", in qla4_8xxx_device_state_handler()
3532 "%s: Device Init Failed 0x%x = %s\n", in qla4_8xxx_device_state_handler()
3541 ql4_printk(KERN_INFO, ha, "Device state is 0x%x = %s\n", in qla4_8xxx_device_state_handler()
3614 writel(0, &ha->qla4_83xx_reg->risc_intr); in qla4_8xxx_load_risc()
3617 writel(0, &ha->qla4_82xx_reg->host_int); in qla4_8xxx_load_risc()
3637 #define OPTROM_BURST_SIZE 0x1000
3641 #define FARX_ACCESS_FLASH_CONF 0x7FFD0000
3642 #define FARX_ACCESS_FLASH_DATA 0x7FF00000
3662 int loops = 0; in qla4_82xx_read_flash_data()
3663 while ((qla4_82xx_rom_lock(ha) != 0) && (loops < 50000)) { in qla4_82xx_read_flash_data()
3674 for (i = 0; i < length/4; i++, faddr += 4) { in qla4_82xx_read_flash_data()
3709 loc = locations[0]; in qla4_8xxx_find_flt_start()
3712 DEBUG2(ql4_printk(KERN_INFO, ha, "FLTL[%s] = 0x%x.\n", loc, *start)); in qla4_8xxx_find_flt_start()
3738 0x400); in qla4_8xxx_get_flt_info()
3743 if (*wptr == __constant_cpu_to_le16(0xffff)) in qla4_8xxx_get_flt_info()
3747 "version=0x%x length=0x%x checksum=0x%x.\n", in qla4_8xxx_get_flt_info()
3754 for (chksum = 0; cnt; cnt--) in qla4_8xxx_get_flt_info()
3758 "version=0x%x length=0x%x checksum=0x%x.\n", in qla4_8xxx_get_flt_info()
3770 DEBUG3(ql4_printk(KERN_DEBUG, ha, "FLT[%02x]: start=0x%x " in qla4_8xxx_get_flt_info()
3771 "end=0x%x size=0x%x.\n", le32_to_cpu(region->code), start, in qla4_8xxx_get_flt_info()
3774 switch (le32_to_cpu(region->code) & 0xff) { in qla4_8xxx_get_flt_info()
3805 loc = locations[0]; in qla4_8xxx_get_flt_info()
3818 …"FLT[%s]: flt=0x%x fdt=0x%x boot=0x%x bootload=0x%x fw=0x%x chap=0x%x chap_size=0x%x ddb=0x%x ddb… in qla4_8xxx_get_flt_info()
3829 #define FLASH_BLK_SIZE_4K 0x1000 in qla4_82xx_get_fdt_info()
3830 #define FLASH_BLK_SIZE_32K 0x8000 in qla4_82xx_get_fdt_info()
3831 #define FLASH_BLK_SIZE_64K 0x10000 in qla4_82xx_get_fdt_info()
3836 uint16_t mid = 0; in qla4_82xx_get_fdt_info()
3837 uint16_t fid = 0; in qla4_82xx_get_fdt_info()
3848 if (*wptr == __constant_cpu_to_le16(0xffff)) in qla4_82xx_get_fdt_info()
3851 if (fdt->sig[0] != 'Q' || fdt->sig[1] != 'L' || fdt->sig[2] != 'I' || in qla4_82xx_get_fdt_info()
3855 for (cnt = 0, chksum = 0; cnt < sizeof(struct qla_fdt_layout) >> 1; in qla4_82xx_get_fdt_info()
3861 "checksum=0x%x id=%c version=0x%x.\n", chksum, fdt->sig[0], in qla4_82xx_get_fdt_info()
3870 hw->fdt_erase_cmd = flash_conf_addr(hw, 0x0300 | fdt->erase_cmd); in qla4_82xx_get_fdt_info()
3874 hw->fdt_unprotect_sec_cmd = flash_conf_addr(hw, 0x0300 | in qla4_82xx_get_fdt_info()
3877 flash_conf_addr(hw, 0x0300 | fdt->protect_sec_cmd) : in qla4_82xx_get_fdt_info()
3878 flash_conf_addr(hw, 0x0336); in qla4_82xx_get_fdt_info()
3883 loc = locations[0]; in qla4_82xx_get_fdt_info()
3886 DEBUG2(ql4_printk(KERN_INFO, ha, "FDT[%s]: (0x%x/0x%x) erase=0x%x " in qla4_82xx_get_fdt_info()
3887 "pro=%x upro=%x wrtd=0x%x blk=0x%x.\n", loc, mid, fid, in qla4_82xx_get_fdt_info()
3896 #define QLA82XX_IDC_PARAM_ADDR 0x003e885c in qla4_82xx_get_idc_param()
3905 if (*wptr == __constant_cpu_to_le32(0xffffffff)) { in qla4_82xx_get_idc_param()
3925 /* Load all mailbox registers, except mailbox 0. */ in qla4_82xx_queue_mbox_cmd()
3930 writel(mbx_cmd[0], &ha->qla4_82xx_reg->mailbox_in[0]); in qla4_82xx_queue_mbox_cmd()
3931 readl(&ha->qla4_82xx_reg->mailbox_in[0]); in qla4_82xx_queue_mbox_cmd()
3949 0xfbff); in qla4_82xx_process_mbox_intr()
3990 memset(&mbox_cmd, 0, sizeof(mbox_cmd)); in qla4_8xxx_stop_firmware()
3991 memset(&mbox_sts, 0, sizeof(mbox_sts)); in qla4_8xxx_stop_firmware()
3993 mbox_cmd[0] = MBOX_CMD_STOP_FW; in qla4_8xxx_stop_firmware()
3995 &mbox_cmd[0], &mbox_sts[0]); in qla4_8xxx_stop_firmware()
4060 memset(&mbox_cmd, 0, sizeof(mbox_cmd)); in qla4_8xxx_get_sys_info()
4061 memset(&mbox_sts, 0, sizeof(mbox_sts)); in qla4_8xxx_get_sys_info()
4063 mbox_cmd[0] = MBOX_CMD_GET_SYS_INFO; in qla4_8xxx_get_sys_info()
4068 if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 6, &mbox_cmd[0], in qla4_8xxx_get_sys_info()
4069 &mbox_sts[0]) != QLA_SUCCESS) { in qla4_8xxx_get_sys_info()
4085 memcpy(ha->my_mac, &sys_info->mac_addr[0], in qla4_8xxx_get_sys_info()
4115 memset(&mbox_cmd, 0, sizeof(mbox_cmd)); in qla4_8xxx_intr_enable()
4116 memset(&mbox_sts, 0, sizeof(mbox_sts)); in qla4_8xxx_intr_enable()
4117 mbox_cmd[0] = MBOX_CMD_ENABLE_INTRS; in qla4_8xxx_intr_enable()
4119 if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, &mbox_cmd[0], in qla4_8xxx_intr_enable()
4120 &mbox_sts[0]) != QLA_SUCCESS) { in qla4_8xxx_intr_enable()
4122 "%s: MBOX_CMD_ENABLE_INTRS failed (0x%04x)\n", in qla4_8xxx_intr_enable()
4123 __func__, mbox_sts[0])); in qla4_8xxx_intr_enable()
4136 memset(&mbox_cmd, 0, sizeof(mbox_cmd)); in qla4_8xxx_intr_disable()
4137 memset(&mbox_sts, 0, sizeof(mbox_sts)); in qla4_8xxx_intr_disable()
4138 mbox_cmd[0] = MBOX_CMD_ENABLE_INTRS; in qla4_8xxx_intr_disable()
4140 if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, &mbox_cmd[0], in qla4_8xxx_intr_disable()
4141 &mbox_sts[0]) != QLA_SUCCESS) { in qla4_8xxx_intr_disable()
4143 "%s: MBOX_CMD_ENABLE_INTRS failed (0x%04x)\n", in qla4_8xxx_intr_disable()
4144 __func__, mbox_sts[0])); in qla4_8xxx_intr_disable()
4158 qla4_82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0xfbff); in qla4_82xx_enable_intrs()
4171 qla4_82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0x0400); in qla4_82xx_disable_intrs()
4182 if (ret < 0) { in qla4_8xxx_enable_msix()
4189 ret = request_irq(pci_irq_vector(ha->pdev, 0), in qla4_8xxx_enable_msix()
4190 qla4_8xxx_default_intr_handler, 0, "qla4xxx (default)", in qla4_8xxx_enable_msix()
4196 qla4_8xxx_msix_rsp_q, 0, "qla4xxx (rsp_q)", ha); in qla4_8xxx_enable_msix()
4200 return 0; in qla4_8xxx_enable_msix()
4203 free_irq(pci_irq_vector(ha->pdev, 0), ha); in qla4_8xxx_enable_msix()