Lines Matching +full:0 +full:x00000001
35 * #define example_bit_field_MASK 0x03
46 * bf_set(example_bit_field, &t1, 0);
70 #define lpfc_sli_intf_valid_MASK 0x00000007
74 #define lpfc_sli_intf_sli_hint2_MASK 0x0000001F
76 #define LPFC_SLI_INTF_SLI_HINT2_NONE 0
78 #define lpfc_sli_intf_sli_hint1_MASK 0x000000FF
80 #define LPFC_SLI_INTF_SLI_HINT1_NONE 0
84 #define lpfc_sli_intf_if_type_MASK 0x0000000F
86 #define LPFC_SLI_INTF_IF_TYPE_0 0
91 #define lpfc_sli_intf_sli_family_MASK 0x0000000F
93 #define LPFC_SLI_INTF_FAMILY_BE2 0x0
94 #define LPFC_SLI_INTF_FAMILY_BE3 0x1
95 #define LPFC_SLI_INTF_FAMILY_LNCR_A0 0xa
96 #define LPFC_SLI_INTF_FAMILY_LNCR_B0 0xb
98 #define lpfc_sli_intf_slirev_MASK 0x0000000F
102 #define lpfc_sli_intf_func_type_SHIFT 0
103 #define lpfc_sli_intf_func_type_MASK 0x00000001
105 #define LPFC_SLI_INTF_IF_TYPE_PHYS 0
122 #define LPFC_VFR_PAGE_SIZE 0x1000 /* 4KB BAR2 per-VF register page size */
131 #define LPFC_MBX_ERROR_RANGE 0x4000
132 #define LPFC_BMBX_BIT1_ADDR_HI 0x2
133 #define LPFC_BMBX_BIT1_ADDR_LO 0
136 #define LPFC_RPI_ALLOC_ERROR 0xFFFF
138 #define LPFC_ENTIRE_FCF_DATABASE 0
139 #define LPFC_DFLT_FCF_INDEX 0
142 #define LPFC_VF0 0
176 #define LPFC_PCI_FUNC0 0
183 #define LPFC_CTL_PDEV_CTL_OFFSET 0x414
184 #define LPFC_CTL_PDEV_CTL_DRST 0x00000001
185 #define LPFC_CTL_PDEV_CTL_FRST 0x00000002
186 #define LPFC_CTL_PDEV_CTL_DD 0x00000004
187 #define LPFC_CTL_PDEV_CTL_LC 0x00000008
188 #define LPFC_CTL_PDEV_CTL_FRL_ALL 0x00
189 #define LPFC_CTL_PDEV_CTL_FRL_FC_FCOE 0x10
190 #define LPFC_CTL_PDEV_CTL_FRL_NIC 0x20
191 #define LPFC_CTL_PDEV_CTL_DDL_RAS 0x1000000
199 #define LPFC_FCP_SCHED_BY_HDWQ 0
203 #define LPFC_NS_QUERY_GID_FT 0
213 #define LPFC_DEF_IMAX 0
221 #define LPFC_MIN_CPU_MAP 0
233 uint32_t bdeFlags:8; /* BDE Flags 0 IS A SUPPORTED
238 uint32_t bdeFlags:8; /* BDE Flags 0 IS A SUPPORTED
241 #define BUFF_TYPE_BDE_64 0x00 /* BDE (Host_resident) */
242 #define BUFF_TYPE_BDE_IMMED 0x01 /* Immediate Data BDE */
243 #define BUFF_TYPE_BDE_64P 0x02 /* BDE (Port-resident) */
244 #define BUFF_TYPE_BDE_64I 0x08 /* Input BDE (Host-resident) */
245 #define BUFF_TYPE_BDE_64IP 0x0A /* Input BDE (Port-resident) */
246 #define BUFF_TYPE_BLP_64 0x40 /* BLP (Host-resident) */
247 #define BUFF_TYPE_BLP_64P 0x42 /* BLP (Port-resident) */
259 #define lpfc_idx_rsrc_rdy_SHIFT 0
260 #define lpfc_idx_rsrc_rdy_MASK 0x00000001
264 #define lpfc_rpi_rsrc_rdy_MASK 0x00000001
268 #define lpfc_vpi_rsrc_rdy_MASK 0x00000001
272 #define lpfc_vfi_rsrc_rdy_MASK 0x00000001
280 #define lpfc_abts_orig_SHIFT 0
281 #define lpfc_abts_orig_MASK 0x00000001
284 #define LPFC_ABTS_UNSOL_INT 0
286 #define lpfc_abts_rxid_SHIFT 0
287 #define lpfc_abts_rxid_MASK 0x0000FFFF
290 #define lpfc_abts_oxid_MASK 0x0000FFFF
293 #define lpfc_vndr_code_SHIFT 0
294 #define lpfc_vndr_code_MASK 0x000000FF
297 #define lpfc_rsn_expln_MASK 0x000000FF
300 #define lpfc_rsn_code_MASK 0x000000FF
311 #define lpfc_eqe_resource_id_MASK 0x0000FFFF
314 #define lpfc_eqe_minor_code_MASK 0x00000FFF
317 #define lpfc_eqe_major_code_MASK 0x00000007
319 #define lpfc_eqe_valid_SHIFT 0
320 #define lpfc_eqe_valid_MASK 0x00000001
331 #define lpfc_cqe_valid_MASK 0x00000001
334 #define lpfc_cqe_code_MASK 0x000000FF
339 #define CQE_STATUS_SUCCESS 0x0
340 #define CQE_STATUS_FCP_RSP_FAILURE 0x1
341 #define CQE_STATUS_REMOTE_STOP 0x2
342 #define CQE_STATUS_LOCAL_REJECT 0x3
343 #define CQE_STATUS_NPORT_RJT 0x4
344 #define CQE_STATUS_FABRIC_RJT 0x5
345 #define CQE_STATUS_NPORT_BSY 0x6
346 #define CQE_STATUS_FABRIC_BSY 0x7
347 #define CQE_STATUS_INTERMED_RSP 0x8
348 #define CQE_STATUS_LS_RJT 0x9
349 #define CQE_STATUS_CMD_REJECT 0xb
350 #define CQE_STATUS_FCP_TGT_LENCHECK 0xc
351 #define CQE_STATUS_NEED_BUFF_ENTRY 0xf
352 #define CQE_STATUS_DI_ERROR 0x16
355 #define LPFC_IOCB_STATUS_MASK 0xf
358 #define CQE_HW_STATUS_NO_ERR 0x0
359 #define CQE_HW_STATUS_UNDERRUN 0x1
360 #define CQE_HW_STATUS_OVERRUN 0x2
363 #define CQE_CODE_COMPL_WQE 0x1
364 #define CQE_CODE_RELEASE_WQE 0x2
365 #define CQE_CODE_RECEIVE 0x4
366 #define CQE_CODE_XRI_ABORTED 0x5
367 #define CQE_CODE_RECEIVE_V1 0x9
368 #define CQE_CODE_NVME_ERSP 0xd
372 * Currently, extended status is limited to 9 bits (0x0 -> 0x103) .
374 #define WCQE_PARAM_MASK 0x1FF
380 #define lpfc_wcqe_c_request_tag_MASK 0x0000FFFF
383 #define lpfc_wcqe_c_status_MASK 0x000000FF
385 #define lpfc_wcqe_c_hw_status_SHIFT 0
386 #define lpfc_wcqe_c_hw_status_MASK 0x000000FF
388 #define lpfc_wcqe_c_ersp0_SHIFT 0
389 #define lpfc_wcqe_c_ersp0_MASK 0x0000FFFF
394 #define lpfc_wcqe_c_bg_edir_MASK 0x00000001
397 #define lpfc_wcqe_c_bg_tdpv_MASK 0x00000001
400 #define lpfc_wcqe_c_bg_re_MASK 0x00000001
403 #define lpfc_wcqe_c_bg_ae_MASK 0x00000001
405 #define lpfc_wcqe_c_bg_ge_SHIFT 0
406 #define lpfc_wcqe_c_bg_ge_MASK 0x00000001
413 #define lpfc_wcqe_c_xb_MASK 0x00000001
416 #define lpfc_wcqe_c_pv_MASK 0x00000001
419 #define lpfc_wcqe_c_priority_MASK 0x00000007
424 #define lpfc_wcqe_c_sqhead_SHIFT 0
425 #define lpfc_wcqe_c_sqhead_MASK 0x0000FFFF
435 #define lpfc_wcqe_r_wq_id_MASK 0x0000FFFF
437 #define lpfc_wcqe_r_wqe_index_SHIFT 0
438 #define lpfc_wcqe_r_wqe_index_MASK 0x0000FFFF
452 #define lpfc_wcqe_xa_status_MASK 0x000000FF
457 #define lpfc_wcqe_xa_remote_xid_MASK 0x0000FFFF
459 #define lpfc_wcqe_xa_xri_SHIFT 0
460 #define lpfc_wcqe_xa_xri_MASK 0x0000FFFF
467 #define lpfc_wcqe_xa_ia_MASK 0x00000001
469 #define CQE_XRI_ABORTED_IA_REMOTE 0
472 #define lpfc_wcqe_xa_br_MASK 0x00000001
474 #define CQE_XRI_ABORTED_BR_BA_ACC 0
477 #define lpfc_wcqe_xa_eo_MASK 0x00000001
479 #define CQE_XRI_ABORTED_EO_REMOTE 0
490 #define lpfc_rcqe_bindex_MASK 0x0000FFF
493 #define lpfc_rcqe_status_MASK 0x000000FF
495 #define FC_STATUS_RQ_SUCCESS 0x10 /* Async receive successful */
496 #define FC_STATUS_RQ_BUF_LEN_EXCEEDED 0x11 /* payload truncated */
497 #define FC_STATUS_INSUFF_BUF_NEED_BUF 0x12 /* Insufficient buffers */
498 #define FC_STATUS_INSUFF_BUF_FRM_DISC 0x13 /* Frame Discard */
500 #define lpfc_rcqe_fcf_id_v1_SHIFT 0
501 #define lpfc_rcqe_fcf_id_v1_MASK 0x0000003F
505 #define lpfc_rcqe_length_MASK 0x0000FFFF
508 #define lpfc_rcqe_rq_id_MASK 0x000003FF
510 #define lpfc_rcqe_fcf_id_SHIFT 0
511 #define lpfc_rcqe_fcf_id_MASK 0x0000003F
513 #define lpfc_rcqe_rq_id_v1_SHIFT 0
514 #define lpfc_rcqe_rq_id_v1_MASK 0x0000FFFF
521 #define lpfc_rcqe_port_MASK 0x00000001
524 #define lpfc_rcqe_hdr_length_MASK 0x0000001F
530 #define lpfc_rcqe_eof_MASK 0x000000FF
532 #define FCOE_EOFn 0x41
533 #define FCOE_EOFt 0x42
534 #define FCOE_EOFni 0x49
535 #define FCOE_EOFa 0x50
536 #define lpfc_rcqe_sof_SHIFT 0
537 #define lpfc_rcqe_sof_MASK 0x000000FF
539 #define FCOE_SOFi2 0x2d
540 #define FCOE_SOFi3 0x2e
541 #define FCOE_SOFn2 0x35
542 #define FCOE_SOFn3 0x36
556 #define lpfc_bde4_last_MASK 0x00000001
558 #define lpfc_bde4_sge_offset_SHIFT 0
559 #define lpfc_bde4_sge_offset_MASK 0x000003FF
562 #define lpfc_bde4_length_SHIFT 0
563 #define lpfc_bde4_length_MASK 0x000000FF
571 #define LPFC_PORT_SEM_UE_RECOVERABLE 0xE000
572 #define LPFC_PORT_SEM_MASK 0xF000
573 /* The following BAR0 Registers apply to SLI4 if_type 0 UCNAs. */
574 #define LPFC_UERR_STATUS_HI 0x00A4
575 #define LPFC_UERR_STATUS_LO 0x00A0
576 #define LPFC_UE_MASK_HI 0x00AC
577 #define LPFC_UE_MASK_LO 0x00A8
579 /* The following BAR0 register sets are defined for if_type 0 and 2 UCNAs. */
580 #define LPFC_SLI_INTF 0x0058
581 #define LPFC_SLI_ASIC_VER 0x009C
583 #define LPFC_CTL_PORT_SEM_OFFSET 0x400
585 #define lpfc_port_smphr_perr_MASK 0x1
588 #define lpfc_port_smphr_sfi_MASK 0x1
591 #define lpfc_port_smphr_nip_MASK 0x1
594 #define lpfc_port_smphr_ipc_MASK 0x1
597 #define lpfc_port_smphr_scr1_MASK 0x1
600 #define lpfc_port_smphr_scr2_MASK 0x1
603 #define lpfc_port_smphr_host_scratch_MASK 0xFF
605 #define lpfc_port_smphr_port_status_SHIFT 0
606 #define lpfc_port_smphr_port_status_MASK 0xFFFF
609 #define LPFC_POST_STAGE_POWER_ON_RESET 0x0000
610 #define LPFC_POST_STAGE_AWAITING_HOST_RDY 0x0001
611 #define LPFC_POST_STAGE_HOST_RDY 0x0002
612 #define LPFC_POST_STAGE_BE_RESET 0x0003
613 #define LPFC_POST_STAGE_SEEPROM_CS_START 0x0100
614 #define LPFC_POST_STAGE_SEEPROM_CS_DONE 0x0101
615 #define LPFC_POST_STAGE_DDR_CONFIG_START 0x0200
616 #define LPFC_POST_STAGE_DDR_CONFIG_DONE 0x0201
617 #define LPFC_POST_STAGE_DDR_CALIBRATE_START 0x0300
618 #define LPFC_POST_STAGE_DDR_CALIBRATE_DONE 0x0301
619 #define LPFC_POST_STAGE_DDR_TEST_START 0x0400
620 #define LPFC_POST_STAGE_DDR_TEST_DONE 0x0401
621 #define LPFC_POST_STAGE_REDBOOT_INIT_START 0x0600
622 #define LPFC_POST_STAGE_REDBOOT_INIT_DONE 0x0601
623 #define LPFC_POST_STAGE_FW_IMAGE_LOAD_START 0x0700
624 #define LPFC_POST_STAGE_FW_IMAGE_LOAD_DONE 0x0701
625 #define LPFC_POST_STAGE_ARMFW_START 0x0800
626 #define LPFC_POST_STAGE_DHCP_QUERY_START 0x0900
627 #define LPFC_POST_STAGE_DHCP_QUERY_DONE 0x0901
628 #define LPFC_POST_STAGE_BOOT_TARGET_DISCOVERY_START 0x0A00
629 #define LPFC_POST_STAGE_BOOT_TARGET_DISCOVERY_DONE 0x0A01
630 #define LPFC_POST_STAGE_RC_OPTION_SET 0x0B00
631 #define LPFC_POST_STAGE_SWITCH_LINK 0x0B01
632 #define LPFC_POST_STAGE_SEND_ICDS_MESSAGE 0x0B02
633 #define LPFC_POST_STAGE_PERFROM_TFTP 0x0B03
634 #define LPFC_POST_STAGE_PARSE_XML 0x0B04
635 #define LPFC_POST_STAGE_DOWNLOAD_IMAGE 0x0B05
636 #define LPFC_POST_STAGE_FLASH_IMAGE 0x0B06
637 #define LPFC_POST_STAGE_RC_DONE 0x0B07
638 #define LPFC_POST_STAGE_REBOOT_SYSTEM 0x0B08
639 #define LPFC_POST_STAGE_MAC_ADDRESS 0x0C00
640 #define LPFC_POST_STAGE_PORT_READY 0xC000
641 #define LPFC_POST_STAGE_PORT_UE 0xF000
643 #define LPFC_CTL_PORT_STA_OFFSET 0x404
645 #define lpfc_sliport_status_err_MASK 0x1
648 #define lpfc_sliport_status_end_MASK 0x1
651 #define lpfc_sliport_status_oti_MASK 0x1
654 #define lpfc_sliport_status_dip_MASK 0x1
657 #define lpfc_sliport_status_rn_MASK 0x1
660 #define lpfc_sliport_status_rdy_MASK 0x1
664 #define LPFC_CTL_PORT_CTL_OFFSET 0x408
666 #define lpfc_sliport_ctrl_end_MASK 0x1
668 #define LPFC_SLIPORT_LITTLE_ENDIAN 0
671 #define lpfc_sliport_ctrl_ip_MASK 0x1
675 #define LPFC_CTL_PORT_ER1_OFFSET 0x40C
676 #define LPFC_CTL_PORT_ER2_OFFSET 0x410
678 #define LPFC_CTL_PORT_EQ_DELAY_OFFSET 0x418
680 #define lpfc_sliport_eqdelay_delay_MASK 0xffff
682 #define lpfc_sliport_eqdelay_id_SHIFT 0
683 #define lpfc_sliport_eqdelay_id_MASK 0xfff
687 /* The following Registers apply to SLI4 if_type 0 UCNAs. They typically
690 #define LPFC_SLIPORT_IF0_SMPHR 0x00AC
692 #define LPFC_IMR_MASK_ALL 0xFFFFFFFF
693 #define LPFC_ISCR_CLEAR_ALL 0xFFFFFFFF
695 #define LPFC_HST_ISR0 0x0C18
696 #define LPFC_HST_ISR1 0x0C1C
697 #define LPFC_HST_ISR2 0x0C20
698 #define LPFC_HST_ISR3 0x0C24
699 #define LPFC_HST_ISR4 0x0C28
701 #define LPFC_HST_IMR0 0x0C48
702 #define LPFC_HST_IMR1 0x0C4C
703 #define LPFC_HST_IMR2 0x0C50
704 #define LPFC_HST_IMR3 0x0C54
705 #define LPFC_HST_IMR4 0x0C58
707 #define LPFC_HST_ISCR0 0x0C78
708 #define LPFC_HST_ISCR1 0x0C7C
709 #define LPFC_HST_ISCR2 0x0C80
710 #define LPFC_HST_ISCR3 0x0C84
711 #define LPFC_HST_ISCR4 0x0C88
749 * value. For UCNA ports running SLI4 and if_type 0, they reside in
755 #define LPFC_ULP0_RQ_DOORBELL 0x00A0
756 #define LPFC_ULP1_RQ_DOORBELL 0x00C0
757 #define LPFC_IF6_RQ_DOORBELL 0x0080
759 #define lpfc_rq_db_list_fm_num_posted_MASK 0x00FF
762 #define lpfc_rq_db_list_fm_index_MASK 0x00FF
764 #define lpfc_rq_db_list_fm_id_SHIFT 0
765 #define lpfc_rq_db_list_fm_id_MASK 0xFFFF
768 #define lpfc_rq_db_ring_fm_num_posted_MASK 0x3FFF
770 #define lpfc_rq_db_ring_fm_id_SHIFT 0
771 #define lpfc_rq_db_ring_fm_id_MASK 0xFFFF
774 #define LPFC_ULP0_WQ_DOORBELL 0x0040
775 #define LPFC_ULP1_WQ_DOORBELL 0x0060
777 #define lpfc_wq_db_list_fm_num_posted_MASK 0x00FF
780 #define lpfc_wq_db_list_fm_index_MASK 0x00FF
782 #define lpfc_wq_db_list_fm_id_SHIFT 0
783 #define lpfc_wq_db_list_fm_id_MASK 0xFFFF
786 #define lpfc_wq_db_ring_fm_num_posted_MASK 0x3FFF
788 #define lpfc_wq_db_ring_fm_id_SHIFT 0
789 #define lpfc_wq_db_ring_fm_id_MASK 0xFFFF
792 #define LPFC_IF6_WQ_DOORBELL 0x0040
794 #define lpfc_if6_wq_db_list_fm_num_posted_MASK 0x00FF
797 #define lpfc_if6_wq_db_list_fm_dpp_MASK 0x0001
800 #define lpfc_if6_wq_db_list_fm_dpp_id_MASK 0x001F
802 #define lpfc_if6_wq_db_list_fm_id_SHIFT 0
803 #define lpfc_if6_wq_db_list_fm_id_MASK 0xFFFF
806 #define LPFC_EQCQ_DOORBELL 0x0120
808 #define lpfc_eqcq_doorbell_se_MASK 0x0001
810 #define LPFC_EQCQ_SOLICIT_ENABLE_OFF 0
813 #define lpfc_eqcq_doorbell_arm_MASK 0x0001
816 #define lpfc_eqcq_doorbell_num_released_MASK 0x1FFF
819 #define lpfc_eqcq_doorbell_qt_MASK 0x0001
821 #define LPFC_QUEUE_TYPE_COMPLETION 0
824 #define lpfc_eqcq_doorbell_eqci_MASK 0x0001
826 #define lpfc_eqcq_doorbell_cqid_lo_SHIFT 0
827 #define lpfc_eqcq_doorbell_cqid_lo_MASK 0x03FF
830 #define lpfc_eqcq_doorbell_cqid_hi_MASK 0x001F
832 #define lpfc_eqcq_doorbell_eqid_lo_SHIFT 0
833 #define lpfc_eqcq_doorbell_eqid_lo_MASK 0x01FF
836 #define lpfc_eqcq_doorbell_eqid_hi_MASK 0x001F
841 #define LPFC_IF6_CQ_DOORBELL 0x00C0
843 #define lpfc_if6_cq_doorbell_se_MASK 0x0001
845 #define LPFC_IF6_CQ_SOLICIT_ENABLE_OFF 0
848 #define lpfc_if6_cq_doorbell_arm_MASK 0x0001
851 #define lpfc_if6_cq_doorbell_num_released_MASK 0x1FFF
853 #define lpfc_if6_cq_doorbell_cqid_SHIFT 0
854 #define lpfc_if6_cq_doorbell_cqid_MASK 0xFFFF
857 #define LPFC_IF6_EQ_DOORBELL 0x0120
859 #define lpfc_if6_eq_doorbell_io_MASK 0x0001
861 #define LPFC_IF6_EQ_INTR_OVERRIDE_OFF 0
864 #define lpfc_if6_eq_doorbell_arm_MASK 0x0001
867 #define lpfc_if6_eq_doorbell_num_released_MASK 0x1FFF
869 #define lpfc_if6_eq_doorbell_eqid_SHIFT 0
870 #define lpfc_if6_eq_doorbell_eqid_MASK 0x0FFF
873 #define LPFC_BMBX 0x0160
875 #define lpfc_bmbx_addr_MASK 0x3FFFFFFF
878 #define lpfc_bmbx_hi_MASK 0x0001
880 #define lpfc_bmbx_rdy_SHIFT 0
881 #define lpfc_bmbx_rdy_MASK 0x0001
884 #define LPFC_MQ_DOORBELL 0x0140
885 #define LPFC_IF6_MQ_DOORBELL 0x0160
887 #define lpfc_mq_doorbell_num_posted_MASK 0x3FFF
889 #define lpfc_mq_doorbell_id_SHIFT 0
890 #define lpfc_mq_doorbell_id_MASK 0xFFFF
895 #define lpfc_mbox_hdr_emb_SHIFT 0
896 #define lpfc_mbox_hdr_emb_MASK 0x00000001
899 #define lpfc_mbox_hdr_sge_cnt_MASK 0x0000001F
910 #define lpfc_mbox_hdr_opcode_SHIFT 0
911 #define lpfc_mbox_hdr_opcode_MASK 0x000000FF
914 #define lpfc_mbox_hdr_subsystem_MASK 0x000000FF
917 #define lpfc_mbox_hdr_port_number_MASK 0x000000FF
920 #define lpfc_mbox_hdr_domain_MASK 0x000000FF
925 #define lpfc_mbox_hdr_version_SHIFT 0
926 #define lpfc_mbox_hdr_version_MASK 0x000000FF
929 #define lpfc_mbox_hdr_pf_num_MASK 0x000000FF
932 #define lpfc_mbox_hdr_vh_num_MASK 0x000000FF
936 #define LPFC_Q_CREATE_VERSION_0 0
937 #define LPFC_OPCODE_VERSION_0 0
942 #define lpfc_mbox_hdr_opcode_SHIFT 0
943 #define lpfc_mbox_hdr_opcode_MASK 0x000000FF
946 #define lpfc_mbox_hdr_subsystem_MASK 0x000000FF
949 #define lpfc_mbox_hdr_domain_MASK 0x000000FF
952 #define lpfc_mbox_hdr_status_SHIFT 0
953 #define lpfc_mbox_hdr_status_MASK 0x000000FF
956 #define lpfc_mbox_hdr_add_status_MASK 0x000000FF
975 #define LPFC_EXTENT_LOCAL 0
976 #define LPFC_TIMEOUT_DEFAULT 0
977 #define LPFC_EXTENT_VERSION_DEFAULT 0
980 #define LPFC_MBOX_SUBSYSTEM_NA 0x0
981 #define LPFC_MBOX_SUBSYSTEM_COMMON 0x1
982 #define LPFC_MBOX_SUBSYSTEM_LOWLEVEL 0xB
983 #define LPFC_MBOX_SUBSYSTEM_FCOE 0xC
988 #define HOST_ENDIAN_LOW_WORD0 0xFF3412FF
989 #define HOST_ENDIAN_HIGH_WORD1 0xFF7856FF
992 #define LPFC_MBOX_OPCODE_NA 0x00
993 #define LPFC_MBOX_OPCODE_CQ_CREATE 0x0C
994 #define LPFC_MBOX_OPCODE_EQ_CREATE 0x0D
995 #define LPFC_MBOX_OPCODE_MQ_CREATE 0x15
996 #define LPFC_MBOX_OPCODE_GET_CNTL_ATTRIBUTES 0x20
997 #define LPFC_MBOX_OPCODE_NOP 0x21
998 #define LPFC_MBOX_OPCODE_MODIFY_EQ_DELAY 0x29
999 #define LPFC_MBOX_OPCODE_MQ_DESTROY 0x35
1000 #define LPFC_MBOX_OPCODE_CQ_DESTROY 0x36
1001 #define LPFC_MBOX_OPCODE_EQ_DESTROY 0x37
1002 #define LPFC_MBOX_OPCODE_QUERY_FW_CFG 0x3A
1003 #define LPFC_MBOX_OPCODE_FUNCTION_RESET 0x3D
1004 #define LPFC_MBOX_OPCODE_SET_PHYSICAL_LINK_CONFIG 0x3E
1005 #define LPFC_MBOX_OPCODE_SET_BOOT_CONFIG 0x43
1006 #define LPFC_MBOX_OPCODE_SET_BEACON_CONFIG 0x45
1007 #define LPFC_MBOX_OPCODE_GET_BEACON_CONFIG 0x46
1008 #define LPFC_MBOX_OPCODE_GET_PORT_NAME 0x4D
1009 #define LPFC_MBOX_OPCODE_MQ_CREATE_EXT 0x5A
1010 #define LPFC_MBOX_OPCODE_GET_VPD_DATA 0x5B
1011 #define LPFC_MBOX_OPCODE_SET_HOST_DATA 0x5D
1012 #define LPFC_MBOX_OPCODE_SEND_ACTIVATION 0x73
1013 #define LPFC_MBOX_OPCODE_RESET_LICENSES 0x74
1014 #define LPFC_MBOX_OPCODE_GET_RSRC_EXTENT_INFO 0x9A
1015 #define LPFC_MBOX_OPCODE_GET_ALLOC_RSRC_EXTENT 0x9B
1016 #define LPFC_MBOX_OPCODE_ALLOC_RSRC_EXTENT 0x9C
1017 #define LPFC_MBOX_OPCODE_DEALLOC_RSRC_EXTENT 0x9D
1018 #define LPFC_MBOX_OPCODE_GET_FUNCTION_CONFIG 0xA0
1019 #define LPFC_MBOX_OPCODE_GET_PROFILE_CAPACITIES 0xA1
1020 #define LPFC_MBOX_OPCODE_GET_PROFILE_CONFIG 0xA4
1021 #define LPFC_MBOX_OPCODE_SET_PROFILE_CONFIG 0xA5
1022 #define LPFC_MBOX_OPCODE_GET_PROFILE_LIST 0xA6
1023 #define LPFC_MBOX_OPCODE_SET_ACT_PROFILE 0xA8
1024 #define LPFC_MBOX_OPCODE_GET_FACTORY_PROFILE_CONFIG 0xA9
1025 #define LPFC_MBOX_OPCODE_READ_OBJECT 0xAB
1026 #define LPFC_MBOX_OPCODE_WRITE_OBJECT 0xAC
1027 #define LPFC_MBOX_OPCODE_READ_OBJECT_LIST 0xAD
1028 #define LPFC_MBOX_OPCODE_DELETE_OBJECT 0xAE
1029 #define LPFC_MBOX_OPCODE_GET_SLI4_PARAMETERS 0xB5
1030 #define LPFC_MBOX_OPCODE_SET_FEATURES 0xBF
1033 #define LPFC_MBOX_OPCODE_FCOE_WQ_CREATE 0x01
1034 #define LPFC_MBOX_OPCODE_FCOE_WQ_DESTROY 0x02
1035 #define LPFC_MBOX_OPCODE_FCOE_POST_SGL_PAGES 0x03
1036 #define LPFC_MBOX_OPCODE_FCOE_REMOVE_SGL_PAGES 0x04
1037 #define LPFC_MBOX_OPCODE_FCOE_RQ_CREATE 0x05
1038 #define LPFC_MBOX_OPCODE_FCOE_RQ_DESTROY 0x06
1039 #define LPFC_MBOX_OPCODE_FCOE_READ_FCF_TABLE 0x08
1040 #define LPFC_MBOX_OPCODE_FCOE_ADD_FCF 0x09
1041 #define LPFC_MBOX_OPCODE_FCOE_DELETE_FCF 0x0A
1042 #define LPFC_MBOX_OPCODE_FCOE_POST_HDR_TEMPLATE 0x0B
1043 #define LPFC_MBOX_OPCODE_FCOE_REDISCOVER_FCF 0x10
1044 #define LPFC_MBOX_OPCODE_FCOE_CQ_CREATE_SET 0x1D
1045 #define LPFC_MBOX_OPCODE_FCOE_SET_FCLINK_SETTINGS 0x21
1046 #define LPFC_MBOX_OPCODE_FCOE_LINK_DIAG_STATE 0x22
1047 #define LPFC_MBOX_OPCODE_FCOE_LINK_DIAG_LOOPBACK 0x23
1048 #define LPFC_MBOX_OPCODE_FCOE_FC_SET_TRUNK_MODE 0x42
1051 #define LPFC_MBOX_OPCODE_SET_DIAG_LOG_OPTION 0x37
1057 #define lpfc_eq_context_size_MASK 0x00000001
1059 #define LPFC_EQE_SIZE_4 0x0
1060 #define LPFC_EQE_SIZE_16 0x1
1062 #define lpfc_eq_context_valid_MASK 0x00000001
1065 #define lpfc_eq_context_autovalid_MASK 0x00000001
1069 #define lpfc_eq_context_count_MASK 0x00000003
1071 #define LPFC_EQ_CNT_256 0x0
1072 #define LPFC_EQ_CNT_512 0x1
1073 #define LPFC_EQ_CNT_1024 0x2
1074 #define LPFC_EQ_CNT_2048 0x3
1075 #define LPFC_EQ_CNT_4096 0x4
1078 #define lpfc_eq_context_delay_multi_MASK 0x000003FF
1100 #define lpfc_post_sgl_pages_xri_SHIFT 0
1101 #define lpfc_post_sgl_pages_xri_MASK 0x0000FFFF
1104 #define lpfc_post_sgl_pages_xricnt_MASK 0x0000FFFF
1137 #define lpfc_mbx_eq_create_num_pages_SHIFT 0
1138 #define lpfc_mbx_eq_create_num_pages_MASK 0x0000FFFF
1145 #define lpfc_mbx_eq_create_q_id_SHIFT 0
1146 #define lpfc_mbx_eq_create_q_id_MASK 0x0000FFFF
1170 #define lpfc_mbx_eq_destroy_q_id_SHIFT 0
1171 #define lpfc_mbx_eq_destroy_q_id_MASK 0x0000FFFF
1192 #define lpfc_fwlog_enable_SHIFT 0
1193 #define lpfc_fwlog_enable_MASK 0x00000001
1196 #define lpfc_fwlog_loglvl_MASK 0x0000000F
1199 #define lpfc_fwlog_ra_WORD 0x00000008
1201 #define lpfc_fwlog_buffcnt_MASK 0x000000FF
1204 #define lpfc_fwlog_buffsz_MASK 0x000000FF
1207 #define lpfc_fwlog_acqe_SHIFT 0
1208 #define lpfc_fwlog_acqe_MASK 0x0000FFFF
1211 #define lpfc_fwlog_cqid_MASK 0x0000FFFF
1227 #define lpfc_cq_context_event_MASK 0x00000001
1230 #define lpfc_cq_context_valid_MASK 0x00000001
1233 #define lpfc_cq_context_count_MASK 0x00000003
1235 #define LPFC_CQ_CNT_256 0x0
1236 #define LPFC_CQ_CNT_512 0x1
1237 #define LPFC_CQ_CNT_1024 0x2
1238 #define LPFC_CQ_CNT_WORD7 0x3
1240 #define lpfc_cq_context_autovalid_MASK 0x00000001
1243 #define lpfc_cq_eq_id_SHIFT 22 /* Version 0 Only */
1244 #define lpfc_cq_eq_id_MASK 0x000000FF
1246 #define lpfc_cq_eq_id_2_SHIFT 0 /* Version 2 Only */
1247 #define lpfc_cq_eq_id_2_MASK 0x0000FFFF
1259 #define lpfc_mbx_cq_create_page_size_MASK 0x000000FF
1261 #define lpfc_mbx_cq_create_num_pages_SHIFT 0
1262 #define lpfc_mbx_cq_create_num_pages_MASK 0x0000FFFF
1269 #define lpfc_mbx_cq_create_q_id_SHIFT 0
1270 #define lpfc_mbx_cq_create_q_id_MASK 0x0000FFFF
1282 #define lpfc_mbx_cq_create_set_page_size_MASK 0x000000FF
1284 #define lpfc_mbx_cq_create_set_num_pages_SHIFT 0
1285 #define lpfc_mbx_cq_create_set_num_pages_MASK 0x0000FFFF
1289 #define lpfc_mbx_cq_create_set_evt_MASK 0x00000001
1292 #define lpfc_mbx_cq_create_set_valid_MASK 0x00000001
1295 #define lpfc_mbx_cq_create_set_cqe_cnt_MASK 0x00000003
1298 #define lpfc_mbx_cq_create_set_cqe_size_MASK 0x00000003
1301 #define lpfc_mbx_cq_create_set_autovalid_MASK 0x0000001
1304 #define lpfc_mbx_cq_create_set_nodelay_MASK 0x00000001
1307 #define lpfc_mbx_cq_create_set_clswm_MASK 0x00000003
1311 #define lpfc_mbx_cq_create_set_arm_MASK 0x00000001
1314 #define lpfc_mbx_cq_create_set_cq_cnt_MASK 0x00007FFF
1316 #define lpfc_mbx_cq_create_set_num_cq_SHIFT 0
1317 #define lpfc_mbx_cq_create_set_num_cq_MASK 0x0000FFFF
1321 #define lpfc_mbx_cq_create_set_eq_id1_MASK 0x0000FFFF
1323 #define lpfc_mbx_cq_create_set_eq_id0_SHIFT 0
1324 #define lpfc_mbx_cq_create_set_eq_id0_MASK 0x0000FFFF
1328 #define lpfc_mbx_cq_create_set_eq_id3_MASK 0x0000FFFF
1330 #define lpfc_mbx_cq_create_set_eq_id2_SHIFT 0
1331 #define lpfc_mbx_cq_create_set_eq_id2_MASK 0x0000FFFF
1335 #define lpfc_mbx_cq_create_set_eq_id5_MASK 0x0000FFFF
1337 #define lpfc_mbx_cq_create_set_eq_id4_SHIFT 0
1338 #define lpfc_mbx_cq_create_set_eq_id4_MASK 0x0000FFFF
1342 #define lpfc_mbx_cq_create_set_eq_id7_MASK 0x0000FFFF
1344 #define lpfc_mbx_cq_create_set_eq_id6_SHIFT 0
1345 #define lpfc_mbx_cq_create_set_eq_id6_MASK 0x0000FFFF
1349 #define lpfc_mbx_cq_create_set_eq_id9_MASK 0x0000FFFF
1351 #define lpfc_mbx_cq_create_set_eq_id8_SHIFT 0
1352 #define lpfc_mbx_cq_create_set_eq_id8_MASK 0x0000FFFF
1356 #define lpfc_mbx_cq_create_set_eq_id11_MASK 0x0000FFFF
1358 #define lpfc_mbx_cq_create_set_eq_id10_SHIFT 0
1359 #define lpfc_mbx_cq_create_set_eq_id10_MASK 0x0000FFFF
1363 #define lpfc_mbx_cq_create_set_eq_id13_MASK 0x0000FFFF
1365 #define lpfc_mbx_cq_create_set_eq_id12_SHIFT 0
1366 #define lpfc_mbx_cq_create_set_eq_id12_MASK 0x0000FFFF
1370 #define lpfc_mbx_cq_create_set_eq_id15_MASK 0x0000FFFF
1372 #define lpfc_mbx_cq_create_set_eq_id14_SHIFT 0
1373 #define lpfc_mbx_cq_create_set_eq_id14_MASK 0x0000FFFF
1380 #define lpfc_mbx_cq_create_set_num_alloc_MASK 0x0000FFFF
1382 #define lpfc_mbx_cq_create_set_base_id_SHIFT 0
1383 #define lpfc_mbx_cq_create_set_base_id_MASK 0x0000FFFF
1394 #define lpfc_mbx_cq_destroy_q_id_SHIFT 0
1395 #define lpfc_mbx_cq_destroy_q_id_MASK 0x0000FFFF
1414 struct { /* Version 0 Request */
1416 #define lpfc_mbx_wq_create_num_pages_SHIFT 0
1417 #define lpfc_mbx_wq_create_num_pages_MASK 0x000000FF
1420 #define lpfc_mbx_wq_create_dua_MASK 0x00000001
1423 #define lpfc_mbx_wq_create_cq_id_MASK 0x0000FFFF
1427 #define lpfc_mbx_wq_create_bua_SHIFT 0
1428 #define lpfc_mbx_wq_create_bua_MASK 0x00000001
1431 #define lpfc_mbx_wq_create_ulp_num_MASK 0x000000FF
1435 uint32_t word0; /* Word 0 is the same as in v0 */
1437 #define lpfc_mbx_wq_create_page_size_SHIFT 0
1438 #define lpfc_mbx_wq_create_page_size_MASK 0x000000FF
1440 #define LPFC_WQ_PAGE_SIZE_4096 0x1
1442 #define lpfc_mbx_wq_create_dpp_req_MASK 0x00000001
1445 #define lpfc_mbx_wq_create_doe_MASK 0x00000001
1448 #define lpfc_mbx_wq_create_toe_MASK 0x00000001
1451 #define lpfc_mbx_wq_create_wqe_size_MASK 0x0000000F
1453 #define LPFC_WQ_WQE_SIZE_64 0x5
1454 #define LPFC_WQ_WQE_SIZE_128 0x6
1456 #define lpfc_mbx_wq_create_wqe_count_MASK 0x0000FFFF
1463 #define lpfc_mbx_wq_create_q_id_SHIFT 0
1464 #define lpfc_mbx_wq_create_q_id_MASK 0x0000FFFF
1468 #define lpfc_mbx_wq_create_bar_set_SHIFT 0
1469 #define lpfc_mbx_wq_create_bar_set_MASK 0x0000FFFF
1471 #define WQ_PCI_BAR_0_AND_1 0x00
1472 #define WQ_PCI_BAR_2_AND_3 0x01
1473 #define WQ_PCI_BAR_4_AND_5 0x02
1475 #define lpfc_mbx_wq_create_db_format_MASK 0x0000FFFF
1481 #define lpfc_mbx_wq_create_dpp_rsp_MASK 0x00000001
1483 #define lpfc_mbx_wq_create_v1_q_id_SHIFT 0
1484 #define lpfc_mbx_wq_create_v1_q_id_MASK 0x0000FFFF
1487 #define lpfc_mbx_wq_create_v1_bar_set_SHIFT 0
1488 #define lpfc_mbx_wq_create_v1_bar_set_MASK 0x0000000F
1493 #define lpfc_mbx_wq_create_dpp_id_MASK 0x0000001F
1495 #define lpfc_mbx_wq_create_dpp_bar_SHIFT 0
1496 #define lpfc_mbx_wq_create_dpp_bar_MASK 0x0000000F
1508 #define lpfc_mbx_wq_destroy_q_id_SHIFT 0
1509 #define lpfc_mbx_wq_destroy_q_id_MASK 0x0000FFFF
1523 #define lpfc_rq_context_rqe_count_SHIFT 16 /* Version 0 Only */
1524 #define lpfc_rq_context_rqe_count_MASK 0x0000000F
1531 #define lpfc_rq_context_rqe_count_1_MASK 0x0000FFFF
1534 #define lpfc_rq_context_rqe_size_MASK 0x0000000F
1541 #define lpfc_rq_context_page_size_SHIFT 0 /* Version 1 Only */
1542 #define lpfc_rq_context_page_size_MASK 0x000000FF
1544 #define LPFC_RQ_PAGE_SIZE_4096 0x1
1547 #define lpfc_rq_context_data_size_MASK 0x0000FFFF
1549 #define lpfc_rq_context_hdr_size_SHIFT 0 /* Version 2 Only */
1550 #define lpfc_rq_context_hdr_size_MASK 0x0000FFFF
1554 #define lpfc_rq_context_cq_id_MASK 0x000003FF
1556 #define lpfc_rq_context_buf_size_SHIFT 0
1557 #define lpfc_rq_context_buf_size_MASK 0x0000FFFF
1559 #define lpfc_rq_context_base_cq_SHIFT 0 /* Version 2 Only */
1560 #define lpfc_rq_context_base_cq_MASK 0x0000FFFF
1570 #define lpfc_mbx_rq_create_num_pages_SHIFT 0
1571 #define lpfc_mbx_rq_create_num_pages_MASK 0x0000FFFF
1574 #define lpfc_mbx_rq_create_dua_MASK 0x00000001
1577 #define lpfc_mbx_rq_create_bqu_MASK 0x00000001
1580 #define lpfc_mbx_rq_create_ulp_num_MASK 0x000000FF
1588 #define lpfc_mbx_rq_create_q_cnt_v2_MASK 0x0000FFFF
1590 #define lpfc_mbx_rq_create_q_id_SHIFT 0
1591 #define lpfc_mbx_rq_create_q_id_MASK 0x0000FFFF
1595 #define lpfc_mbx_rq_create_bar_set_SHIFT 0
1596 #define lpfc_mbx_rq_create_bar_set_MASK 0x0000FFFF
1599 #define lpfc_mbx_rq_create_db_format_MASK 0x0000FFFF
1610 #define lpfc_mbx_rq_create_num_pages_SHIFT 0
1611 #define lpfc_mbx_rq_create_num_pages_MASK 0x0000FFFF
1614 #define lpfc_mbx_rq_create_rq_cnt_MASK 0x000000FF
1617 #define lpfc_mbx_rq_create_dua_MASK 0x00000001
1620 #define lpfc_mbx_rq_create_bqu_MASK 0x00000001
1623 #define lpfc_mbx_rq_create_ulp_num_MASK 0x000000FF
1626 #define lpfc_mbx_rq_create_dim_MASK 0x00000001
1629 #define lpfc_mbx_rq_create_dfd_MASK 0x00000001
1632 #define lpfc_mbx_rq_create_dnb_MASK 0x00000001
1640 #define lpfc_mbx_rq_create_q_cnt_v2_MASK 0x0000FFFF
1642 #define lpfc_mbx_rq_create_q_id_SHIFT 0
1643 #define lpfc_mbx_rq_create_q_id_MASK 0x0000FFFF
1647 #define lpfc_mbx_rq_create_bar_set_SHIFT 0
1648 #define lpfc_mbx_rq_create_bar_set_MASK 0x0000FFFF
1651 #define lpfc_mbx_rq_create_db_format_MASK 0x0000FFFF
1662 #define lpfc_mbx_rq_destroy_q_id_SHIFT 0
1663 #define lpfc_mbx_rq_destroy_q_id_MASK 0x0000FFFF
1674 #define lpfc_mq_context_cq_id_SHIFT 22 /* Version 0 Only */
1675 #define lpfc_mq_context_cq_id_MASK 0x000003FF
1678 #define lpfc_mq_context_ring_size_MASK 0x0000000F
1680 #define LPFC_MQ_RING_SIZE_16 0x5
1681 #define LPFC_MQ_RING_SIZE_32 0x6
1682 #define LPFC_MQ_RING_SIZE_64 0x7
1683 #define LPFC_MQ_RING_SIZE_128 0x8
1686 #define lpfc_mq_context_valid_MASK 0x00000001
1697 #define lpfc_mbx_mq_create_num_pages_SHIFT 0
1698 #define lpfc_mbx_mq_create_num_pages_MASK 0x0000FFFF
1705 #define lpfc_mbx_mq_create_q_id_SHIFT 0
1706 #define lpfc_mbx_mq_create_q_id_MASK 0x0000FFFF
1717 #define lpfc_mbx_mq_create_ext_num_pages_SHIFT 0
1718 #define lpfc_mbx_mq_create_ext_num_pages_MASK 0x0000FFFF
1721 #define lpfc_mbx_mq_create_ext_cq_id_MASK 0x0000FFFF
1725 #define lpfc_mbx_mq_create_ext_async_evt_link_MASK 0x00000001
1727 #define LPFC_EVT_CODE_LINK_NO_LINK 0x0
1728 #define LPFC_EVT_CODE_LINK_10_MBIT 0x1
1729 #define LPFC_EVT_CODE_LINK_100_MBIT 0x2
1730 #define LPFC_EVT_CODE_LINK_1_GBIT 0x3
1731 #define LPFC_EVT_CODE_LINK_10_GBIT 0x4
1733 #define lpfc_mbx_mq_create_ext_async_evt_fip_MASK 0x00000001
1736 #define lpfc_mbx_mq_create_ext_async_evt_group5_MASK 0x00000001
1739 #define lpfc_mbx_mq_create_ext_async_evt_fc_MASK 0x00000001
1741 #define LPFC_EVT_CODE_FC_NO_LINK 0x0
1742 #define LPFC_EVT_CODE_FC_1_GBAUD 0x1
1743 #define LPFC_EVT_CODE_FC_2_GBAUD 0x2
1744 #define LPFC_EVT_CODE_FC_4_GBAUD 0x4
1745 #define LPFC_EVT_CODE_FC_8_GBAUD 0x8
1746 #define LPFC_EVT_CODE_FC_10_GBAUD 0xA
1747 #define LPFC_EVT_CODE_FC_16_GBAUD 0x10
1749 #define lpfc_mbx_mq_create_ext_async_evt_sli_MASK 0x00000001
1756 #define lpfc_mbx_mq_create_q_id_SHIFT 0
1757 #define lpfc_mbx_mq_create_q_id_MASK 0x0000FFFF
1761 #define LPFC_ASYNC_EVENT_LINK_STATE 0x2
1762 #define LPFC_ASYNC_EVENT_FCF_STATE 0x4
1763 #define LPFC_ASYNC_EVENT_GROUP5 0x20
1771 #define lpfc_mbx_mq_destroy_q_id_SHIFT 0
1772 #define lpfc_mbx_mq_destroy_q_id_MASK 0x0000FFFF
1784 #define LPFC_RSC_TYPE_FCOE_VFI 0x20
1785 #define LPFC_RSC_TYPE_FCOE_VPI 0x21
1786 #define LPFC_RSC_TYPE_FCOE_RPI 0x22
1787 #define LPFC_RSC_TYPE_FCOE_XRI 0x23
1794 #define lpfc_mbx_get_rsrc_extent_info_type_SHIFT 0
1795 #define lpfc_mbx_get_rsrc_extent_info_type_MASK 0x0000FFFF
1800 #define lpfc_mbx_get_rsrc_extent_info_cnt_SHIFT 0
1801 #define lpfc_mbx_get_rsrc_extent_info_cnt_MASK 0x0000FFFF
1804 #define lpfc_mbx_get_rsrc_extent_info_size_MASK 0x0000FFFF
1814 #define LPFC_FC_FCOE 0x00000007
1818 #define LPFC_FCOE_INI_MODE 0x00000040
1819 #define LPFC_FCOE_TGT_MODE 0x00000080
1820 #define LPFC_DUA_MODE 0x00000800
1822 #define LPFC_ULP_FCOE_INIT_MODE 0x00000040
1823 #define LPFC_ULP_FCOE_TGT_MODE 0x00000080
1840 #define lpfc_mbx_set_beacon_port_num_SHIFT 0
1841 #define lpfc_mbx_set_beacon_port_num_MASK 0x0000003F
1844 #define lpfc_mbx_set_beacon_port_type_MASK 0x00000003
1847 #define lpfc_mbx_set_beacon_state_MASK 0x000000FF
1850 #define lpfc_mbx_set_beacon_duration_MASK 0x000000FF
1855 #define lpfc_mbx_set_beacon_duration_v1_MASK 0x0000FFFF
1862 #define lpfc_mbx_rsrc_id_word4_0_SHIFT 0
1863 #define lpfc_mbx_rsrc_id_word4_0_MASK 0x0000FFFF
1866 #define lpfc_mbx_rsrc_id_word4_1_MASK 0x0000FFFF
1875 #define lpfc_mbx_set_diag_state_diag_SHIFT 0
1876 #define lpfc_mbx_set_diag_state_diag_MASK 0x00000001
1879 #define lpfc_mbx_set_diag_state_diag_bit_valid_MASK 0x00000001
1881 #define LPFC_DIAG_STATE_DIAG_BIT_VALID_NO_CHANGE 0
1884 #define lpfc_mbx_set_diag_state_link_num_MASK 0x0000003F
1887 #define lpfc_mbx_set_diag_state_link_type_MASK 0x00000003
1901 #define lpfc_mbx_set_diag_lpbk_type_SHIFT 0
1902 #define lpfc_mbx_set_diag_lpbk_type_MASK 0x00000003
1904 #define LPFC_DIAG_LOOPBACK_TYPE_DISABLE 0x0
1905 #define LPFC_DIAG_LOOPBACK_TYPE_INTERNAL 0x1
1906 #define LPFC_DIAG_LOOPBACK_TYPE_SERDES 0x2
1907 #define LPFC_DIAG_LOOPBACK_TYPE_EXTERNAL_TRUNKED 0x3
1909 #define lpfc_mbx_set_diag_lpbk_link_num_MASK 0x0000003F
1912 #define lpfc_mbx_set_diag_lpbk_link_type_MASK 0x00000003
1927 #define lpfc_mbx_run_diag_test_link_num_MASK 0x0000003F
1930 #define lpfc_mbx_run_diag_test_link_type_MASK 0x00000003
1933 #define lpfc_mbx_run_diag_test_test_id_SHIFT 0
1934 #define lpfc_mbx_run_diag_test_test_id_MASK 0x0000FFFF
1937 #define lpfc_mbx_run_diag_test_loops_MASK 0x0000FFFF
1940 #define lpfc_mbx_run_diag_test_test_ver_SHIFT 0
1941 #define lpfc_mbx_run_diag_test_test_ver_MASK 0x0000FFFF
1944 #define lpfc_mbx_run_diag_test_err_act_MASK 0x000000FF
1975 #define lpfc_mbx_alloc_rsrc_extents_type_SHIFT 0
1976 #define lpfc_mbx_alloc_rsrc_extents_type_MASK 0x0000FFFF
1979 #define lpfc_mbx_alloc_rsrc_extents_cnt_MASK 0x0000FFFF
1984 #define lpfc_mbx_rsrc_cnt_SHIFT 0
1985 #define lpfc_mbx_rsrc_cnt_MASK 0x0000FFFF
2009 #define lpfc_mbx_dealloc_rsrc_extents_type_SHIFT 0
2010 #define lpfc_mbx_dealloc_rsrc_extents_type_MASK 0x0000FFFF
2021 #define lpfc_mbx_post_hdr_tmpl_rpi_offset_SHIFT 0
2022 #define lpfc_mbx_post_hdr_tmpl_rpi_offset_MASK 0x0000FFFF
2025 #define lpfc_mbx_post_hdr_tmpl_page_cnt_MASK 0x0000FFFF
2036 #define lpfc_sli4_sge_offset_SHIFT 0
2037 #define lpfc_sli4_sge_offset_MASK 0x07FFFFFF
2040 #define lpfc_sli4_sge_type_MASK 0x0000000F
2042 #define LPFC_SGE_TYPE_DATA 0x0
2043 #define LPFC_SGE_TYPE_DIF 0x4
2044 #define LPFC_SGE_TYPE_LSP 0x5
2045 #define LPFC_SGE_TYPE_PEDIF 0x6
2046 #define LPFC_SGE_TYPE_PESEED 0x7
2047 #define LPFC_SGE_TYPE_DISEED 0x8
2048 #define LPFC_SGE_TYPE_ENC 0x9
2049 #define LPFC_SGE_TYPE_ATM 0xA
2050 #define LPFC_SGE_TYPE_SKIP 0xC
2052 #define lpfc_sli4_sge_last_MASK 0x00000001
2079 #define lpfc_sli4_sge_dif_apptran_SHIFT 0
2080 #define lpfc_sli4_sge_dif_apptran_MASK 0x0000FFFF
2083 #define lpfc_sli4_sge_dif_af_MASK 0x00000001
2086 #define lpfc_sli4_sge_dif_na_MASK 0x00000001
2089 #define lpfc_sli4_sge_dif_hi_MASK 0x00000001
2092 #define lpfc_sli4_sge_dif_type_MASK 0x0000000F
2095 #define lpfc_sli4_sge_dif_last_MASK 0x00000001
2098 #define lpfc_sli4_sge_dif_apptag_SHIFT 0
2099 #define lpfc_sli4_sge_dif_apptag_MASK 0x0000FFFF
2102 #define lpfc_sli4_sge_dif_bs_MASK 0x00000007
2105 #define lpfc_sli4_sge_dif_ai_MASK 0x00000001
2108 #define lpfc_sli4_sge_dif_me_MASK 0x00000001
2111 #define lpfc_sli4_sge_dif_re_MASK 0x00000001
2114 #define lpfc_sli4_sge_dif_ce_MASK 0x00000001
2117 #define lpfc_sli4_sge_dif_nr_MASK 0x00000001
2120 #define lpfc_sli4_sge_dif_oprx_MASK 0x0000000F
2123 #define lpfc_sli4_sge_dif_optx_MASK 0x0000000F
2133 #define lpfc_fcf_record_mac_0_SHIFT 0
2134 #define lpfc_fcf_record_mac_0_MASK 0x000000FF
2137 #define lpfc_fcf_record_mac_1_MASK 0x000000FF
2140 #define lpfc_fcf_record_mac_2_MASK 0x000000FF
2143 #define lpfc_fcf_record_mac_3_MASK 0x000000FF
2146 #define lpfc_fcf_record_mac_4_SHIFT 0
2147 #define lpfc_fcf_record_mac_4_MASK 0x000000FF
2150 #define lpfc_fcf_record_mac_5_MASK 0x000000FF
2153 #define lpfc_fcf_record_fcf_avail_MASK 0x000000FF
2156 #define lpfc_fcf_record_mac_addr_prov_MASK 0x000000FF
2161 #define lpfc_fcf_record_fab_name_0_SHIFT 0
2162 #define lpfc_fcf_record_fab_name_0_MASK 0x000000FF
2165 #define lpfc_fcf_record_fab_name_1_MASK 0x000000FF
2168 #define lpfc_fcf_record_fab_name_2_MASK 0x000000FF
2171 #define lpfc_fcf_record_fab_name_3_MASK 0x000000FF
2174 #define lpfc_fcf_record_fab_name_4_SHIFT 0
2175 #define lpfc_fcf_record_fab_name_4_MASK 0x000000FF
2178 #define lpfc_fcf_record_fab_name_5_MASK 0x000000FF
2181 #define lpfc_fcf_record_fab_name_6_MASK 0x000000FF
2184 #define lpfc_fcf_record_fab_name_7_MASK 0x000000FF
2187 #define lpfc_fcf_record_fc_map_0_SHIFT 0
2188 #define lpfc_fcf_record_fc_map_0_MASK 0x000000FF
2191 #define lpfc_fcf_record_fc_map_1_MASK 0x000000FF
2194 #define lpfc_fcf_record_fc_map_2_MASK 0x000000FF
2197 #define lpfc_fcf_record_fcf_valid_MASK 0x00000001
2200 #define lpfc_fcf_record_fcf_fc_MASK 0x00000001
2203 #define lpfc_fcf_record_fcf_sol_MASK 0x00000001
2206 #define lpfc_fcf_record_fcf_index_SHIFT 0
2207 #define lpfc_fcf_record_fcf_index_MASK 0x0000FFFF
2210 #define lpfc_fcf_record_fcf_state_MASK 0x0000FFFF
2214 #define lpfc_fcf_record_switch_name_0_SHIFT 0
2215 #define lpfc_fcf_record_switch_name_0_MASK 0x000000FF
2218 #define lpfc_fcf_record_switch_name_1_MASK 0x000000FF
2221 #define lpfc_fcf_record_switch_name_2_MASK 0x000000FF
2224 #define lpfc_fcf_record_switch_name_3_MASK 0x000000FF
2227 #define lpfc_fcf_record_switch_name_4_SHIFT 0
2228 #define lpfc_fcf_record_switch_name_4_MASK 0x000000FF
2231 #define lpfc_fcf_record_switch_name_5_MASK 0x000000FF
2234 #define lpfc_fcf_record_switch_name_6_MASK 0x000000FF
2237 #define lpfc_fcf_record_switch_name_7_MASK 0x000000FF
2246 #define lpfc_mbx_read_fcf_tbl_indx_SHIFT 0
2247 #define lpfc_mbx_read_fcf_tbl_indx_MASK 0x0000FFFF
2255 #define lpfc_mbx_read_fcf_tbl_nxt_vindx_SHIFT 0
2256 #define lpfc_mbx_read_fcf_tbl_nxt_vindx_MASK 0x0000FFFF
2263 #define lpfc_mbx_add_fcf_tbl_fcfi_SHIFT 0
2264 #define lpfc_mbx_add_fcf_tbl_fcfi_MASK 0x0000FFFF
2272 #define lpfc_mbx_del_fcf_tbl_count_SHIFT 0
2273 #define lpfc_mbx_del_fcf_tbl_count_MASK 0x0000FFFF
2276 #define lpfc_mbx_del_fcf_tbl_index_MASK 0x0000FFFF
2283 #define lpfc_mbx_redisc_fcf_count_SHIFT 0
2284 #define lpfc_mbx_redisc_fcf_count_MASK 0x0000FFFF
2288 #define lpfc_mbx_redisc_fcf_index_SHIFT 0
2289 #define lpfc_mbx_redisc_fcf_index_MASK 0x0000FFFF
2294 #define STATUS_SUCCESS 0x0
2295 #define STATUS_FAILED 0x1
2296 #define STATUS_ILLEGAL_REQUEST 0x2
2297 #define STATUS_ILLEGAL_FIELD 0x3
2298 #define STATUS_INSUFFICIENT_BUFFER 0x4
2299 #define STATUS_UNAUTHORIZED_REQUEST 0x5
2300 #define STATUS_FLASHROM_SAVE_FAILED 0x17
2301 #define STATUS_FLASHROM_RESTORE_FAILED 0x18
2302 #define STATUS_ICCBINDEX_ALLOC_FAILED 0x1a
2303 #define STATUS_IOCTLHANDLE_ALLOC_FAILED 0x1b
2304 #define STATUS_INVALID_PHY_ADDR_FROM_OSM 0x1c
2305 #define STATUS_INVALID_PHY_ADDR_LEN_FROM_OSM 0x1d
2306 #define STATUS_ASSERT_FAILED 0x1e
2307 #define STATUS_INVALID_SESSION 0x1f
2308 #define STATUS_INVALID_CONNECTION 0x20
2309 #define STATUS_BTL_PATH_EXCEEDS_OSM_LIMIT 0x21
2310 #define STATUS_BTL_NO_FREE_SLOT_PATH 0x24
2311 #define STATUS_BTL_NO_FREE_SLOT_TGTID 0x25
2312 #define STATUS_OSM_DEVSLOT_NOT_FOUND 0x26
2313 #define STATUS_FLASHROM_READ_FAILED 0x27
2314 #define STATUS_POLL_IOCTL_TIMEOUT 0x28
2315 #define STATUS_ERROR_ACITMAIN 0x2a
2316 #define STATUS_REBOOT_REQUIRED 0x2c
2317 #define STATUS_FCF_IN_USE 0x3a
2318 #define STATUS_FCF_TABLE_EMPTY 0x43
2324 #define ADD_STATUS_OPERATION_ALREADY_ACTIVE 0x67
2325 #define ADD_STATUS_FW_NOT_SUPPORTED 0xEB
2326 #define ADD_STATUS_INVALID_REQUEST 0x4B
2327 #define ADD_STATUS_FW_DOWNLOAD_HW_DISABLED 0x58
2336 #define lpfc_init_vfi_vr_MASK 0x00000001
2339 #define lpfc_init_vfi_vt_MASK 0x00000001
2342 #define lpfc_init_vfi_vf_MASK 0x00000001
2345 #define lpfc_init_vfi_vp_MASK 0x00000001
2347 #define lpfc_init_vfi_vfi_SHIFT 0
2348 #define lpfc_init_vfi_vfi_MASK 0x0000FFFF
2352 #define lpfc_init_vfi_vpi_MASK 0x0000FFFF
2354 #define lpfc_init_vfi_fcfi_SHIFT 0
2355 #define lpfc_init_vfi_fcfi_MASK 0x0000FFFF
2359 #define lpfc_init_vfi_pri_MASK 0x00000007
2362 #define lpfc_init_vfi_vf_id_MASK 0x00000FFF
2366 #define lpfc_init_vfi_hop_count_MASK 0x000000FF
2369 #define MBX_VFI_IN_USE 0x9F02
2375 #define lpfc_reg_vfi_upd_MASK 0x00000001
2378 #define lpfc_reg_vfi_vp_MASK 0x00000001
2380 #define lpfc_reg_vfi_vfi_SHIFT 0
2381 #define lpfc_reg_vfi_vfi_MASK 0x0000FFFF
2385 #define lpfc_reg_vfi_vpi_MASK 0x0000FFFF
2387 #define lpfc_reg_vfi_fcfi_SHIFT 0
2388 #define lpfc_reg_vfi_fcfi_MASK 0x0000FFFF
2395 #define lpfc_reg_vfi_nport_id_SHIFT 0
2396 #define lpfc_reg_vfi_nport_id_MASK 0x00FFFFFF
2399 #define lpfc_reg_vfi_bbcr_MASK 0x00000001
2402 #define lpfc_reg_vfi_bbscn_MASK 0x0000000F
2409 #define lpfc_init_vpi_vfi_MASK 0x0000FFFF
2411 #define lpfc_init_vpi_vpi_SHIFT 0
2412 #define lpfc_init_vpi_vpi_MASK 0x0000FFFF
2419 #define lpfc_mbx_read_vpi_vnportid_SHIFT 0
2420 #define lpfc_mbx_read_vpi_vnportid_MASK 0x00FFFFFF
2424 #define lpfc_mbx_read_vpi_acq_alpa_SHIFT 0
2425 #define lpfc_mbx_read_vpi_acq_alpa_MASK 0x000000FF
2428 #define lpfc_mbx_read_vpi_pb_MASK 0x00000001
2431 #define lpfc_mbx_read_vpi_spec_alpa_MASK 0x000000FF
2434 #define lpfc_mbx_read_vpi_ns_MASK 0x00000001
2437 #define lpfc_mbx_read_vpi_hl_MASK 0x00000001
2441 #define lpfc_mbx_read_vpi_vpi_SHIFT 0
2442 #define lpfc_mbx_read_vpi_vpi_MASK 0x0000FFFF
2445 #define lpfc_mbx_read_vpi_mac_0_SHIFT 0
2446 #define lpfc_mbx_read_vpi_mac_0_MASK 0x000000FF
2449 #define lpfc_mbx_read_vpi_mac_1_MASK 0x000000FF
2452 #define lpfc_mbx_read_vpi_mac_2_MASK 0x000000FF
2455 #define lpfc_mbx_read_vpi_mac_3_MASK 0x000000FF
2458 #define lpfc_mbx_read_vpi_mac_4_SHIFT 0
2459 #define lpfc_mbx_read_vpi_mac_4_MASK 0x000000FF
2462 #define lpfc_mbx_read_vpi_mac_5_MASK 0x000000FF
2465 #define lpfc_mbx_read_vpi_vlan_tag_MASK 0x00000FFF
2468 #define lpfc_mbx_read_vpi_vv_MASK 0x0000001
2475 #define lpfc_unreg_vfi_vfi_SHIFT 0
2476 #define lpfc_unreg_vfi_vfi_MASK 0x0000FFFF
2482 #define lpfc_resume_rpi_index_SHIFT 0
2483 #define lpfc_resume_rpi_index_MASK 0x0000FFFF
2486 #define lpfc_resume_rpi_ii_MASK 0x00000003
2488 #define RESUME_INDEX_RPI 0
2495 #define REG_FCF_INVALID_QID 0xFFFF
2498 #define lpfc_reg_fcfi_info_index_SHIFT 0
2499 #define lpfc_reg_fcfi_info_index_MASK 0x0000FFFF
2502 #define lpfc_reg_fcfi_fcfi_MASK 0x0000FFFF
2505 #define lpfc_reg_fcfi_rq_id1_SHIFT 0
2506 #define lpfc_reg_fcfi_rq_id1_MASK 0x0000FFFF
2509 #define lpfc_reg_fcfi_rq_id0_MASK 0x0000FFFF
2512 #define lpfc_reg_fcfi_rq_id3_SHIFT 0
2513 #define lpfc_reg_fcfi_rq_id3_MASK 0x0000FFFF
2516 #define lpfc_reg_fcfi_rq_id2_MASK 0x0000FFFF
2520 #define lpfc_reg_fcfi_type_match0_MASK 0x000000FF
2523 #define lpfc_reg_fcfi_type_mask0_MASK 0x000000FF
2526 #define lpfc_reg_fcfi_rctl_match0_MASK 0x000000FF
2528 #define lpfc_reg_fcfi_rctl_mask0_SHIFT 0
2529 #define lpfc_reg_fcfi_rctl_mask0_MASK 0x000000FF
2533 #define lpfc_reg_fcfi_type_match1_MASK 0x000000FF
2536 #define lpfc_reg_fcfi_type_mask1_MASK 0x000000FF
2539 #define lpfc_reg_fcfi_rctl_match1_MASK 0x000000FF
2541 #define lpfc_reg_fcfi_rctl_mask1_SHIFT 0
2542 #define lpfc_reg_fcfi_rctl_mask1_MASK 0x000000FF
2546 #define lpfc_reg_fcfi_type_match2_MASK 0x000000FF
2549 #define lpfc_reg_fcfi_type_mask2_MASK 0x000000FF
2552 #define lpfc_reg_fcfi_rctl_match2_MASK 0x000000FF
2554 #define lpfc_reg_fcfi_rctl_mask2_SHIFT 0
2555 #define lpfc_reg_fcfi_rctl_mask2_MASK 0x000000FF
2559 #define lpfc_reg_fcfi_type_match3_MASK 0x000000FF
2562 #define lpfc_reg_fcfi_type_mask3_MASK 0x000000FF
2565 #define lpfc_reg_fcfi_rctl_match3_MASK 0x000000FF
2567 #define lpfc_reg_fcfi_rctl_mask3_SHIFT 0
2568 #define lpfc_reg_fcfi_rctl_mask3_MASK 0x000000FF
2572 #define lpfc_reg_fcfi_mam_MASK 0x00000003
2574 #define LPFC_MAM_BOTH 0 /* Both SPMA and FPMA */
2578 #define lpfc_reg_fcfi_vv_MASK 0x00000001
2580 #define lpfc_reg_fcfi_vlan_tag_SHIFT 0
2581 #define lpfc_reg_fcfi_vlan_tag_MASK 0x00000FFF
2587 #define lpfc_reg_fcfi_mrq_info_index_SHIFT 0
2588 #define lpfc_reg_fcfi_mrq_info_index_MASK 0x0000FFFF
2591 #define lpfc_reg_fcfi_mrq_fcfi_MASK 0x0000FFFF
2594 #define lpfc_reg_fcfi_mrq_rq_id1_SHIFT 0
2595 #define lpfc_reg_fcfi_mrq_rq_id1_MASK 0x0000FFFF
2598 #define lpfc_reg_fcfi_mrq_rq_id0_MASK 0x0000FFFF
2601 #define lpfc_reg_fcfi_mrq_rq_id3_SHIFT 0
2602 #define lpfc_reg_fcfi_mrq_rq_id3_MASK 0x0000FFFF
2605 #define lpfc_reg_fcfi_mrq_rq_id2_MASK 0x0000FFFF
2609 #define lpfc_reg_fcfi_mrq_type_match0_MASK 0x000000FF
2612 #define lpfc_reg_fcfi_mrq_type_mask0_MASK 0x000000FF
2615 #define lpfc_reg_fcfi_mrq_rctl_match0_MASK 0x000000FF
2617 #define lpfc_reg_fcfi_mrq_rctl_mask0_SHIFT 0
2618 #define lpfc_reg_fcfi_mrq_rctl_mask0_MASK 0x000000FF
2622 #define lpfc_reg_fcfi_mrq_type_match1_MASK 0x000000FF
2625 #define lpfc_reg_fcfi_mrq_type_mask1_MASK 0x000000FF
2628 #define lpfc_reg_fcfi_mrq_rctl_match1_MASK 0x000000FF
2630 #define lpfc_reg_fcfi_mrq_rctl_mask1_SHIFT 0
2631 #define lpfc_reg_fcfi_mrq_rctl_mask1_MASK 0x000000FF
2635 #define lpfc_reg_fcfi_mrq_type_match2_MASK 0x000000FF
2638 #define lpfc_reg_fcfi_mrq_type_mask2_MASK 0x000000FF
2641 #define lpfc_reg_fcfi_mrq_rctl_match2_MASK 0x000000FF
2643 #define lpfc_reg_fcfi_mrq_rctl_mask2_SHIFT 0
2644 #define lpfc_reg_fcfi_mrq_rctl_mask2_MASK 0x000000FF
2648 #define lpfc_reg_fcfi_mrq_type_match3_MASK 0x000000FF
2651 #define lpfc_reg_fcfi_mrq_type_mask3_MASK 0x000000FF
2654 #define lpfc_reg_fcfi_mrq_rctl_match3_MASK 0x000000FF
2656 #define lpfc_reg_fcfi_mrq_rctl_mask3_SHIFT 0
2657 #define lpfc_reg_fcfi_mrq_rctl_mask3_MASK 0x000000FF
2661 #define lpfc_reg_fcfi_mrq_ptc7_MASK 0x00000001
2664 #define lpfc_reg_fcfi_mrq_ptc6_MASK 0x00000001
2667 #define lpfc_reg_fcfi_mrq_ptc5_MASK 0x00000001
2670 #define lpfc_reg_fcfi_mrq_ptc4_MASK 0x00000001
2673 #define lpfc_reg_fcfi_mrq_ptc3_MASK 0x00000001
2676 #define lpfc_reg_fcfi_mrq_ptc2_MASK 0x00000001
2679 #define lpfc_reg_fcfi_mrq_ptc1_MASK 0x00000001
2682 #define lpfc_reg_fcfi_mrq_ptc0_MASK 0x00000001
2685 #define lpfc_reg_fcfi_mrq_pt7_MASK 0x00000001
2688 #define lpfc_reg_fcfi_mrq_pt6_MASK 0x00000001
2691 #define lpfc_reg_fcfi_mrq_pt5_MASK 0x00000001
2694 #define lpfc_reg_fcfi_mrq_pt4_MASK 0x00000001
2697 #define lpfc_reg_fcfi_mrq_pt3_MASK 0x00000001
2700 #define lpfc_reg_fcfi_mrq_pt2_MASK 0x00000001
2703 #define lpfc_reg_fcfi_mrq_pt1_MASK 0x00000001
2706 #define lpfc_reg_fcfi_mrq_pt0_MASK 0x00000001
2709 #define lpfc_reg_fcfi_mrq_xmv_MASK 0x00000001
2712 #define lpfc_reg_fcfi_mrq_mode_MASK 0x00000001
2715 #define lpfc_reg_fcfi_mrq_vv_MASK 0x00000001
2717 #define lpfc_reg_fcfi_mrq_vlan_tag_SHIFT 0
2718 #define lpfc_reg_fcfi_mrq_vlan_tag_MASK 0x00000FFF
2722 #define lpfc_reg_fcfi_mrq_policy_MASK 0x0000000F
2725 #define lpfc_reg_fcfi_mrq_filter_MASK 0x0000000F
2727 #define lpfc_reg_fcfi_mrq_npairs_SHIFT 0
2728 #define lpfc_reg_fcfi_mrq_npairs_MASK 0x000000FF
2742 #define lpfc_unreg_fcfi_SHIFT 0
2743 #define lpfc_unreg_fcfi_MASK 0x0000FFFF
2750 #define lpfc_mbx_rd_rev_sli_lvl_MASK 0x0000000F
2753 #define lpfc_mbx_rd_rev_fcoe_MASK 0x00000001
2756 #define lpfc_mbx_rd_rev_cee_ver_MASK 0x00000003
2758 #define LPFC_PREDCBX_CEE_MODE 0
2761 #define lpfc_mbx_rd_rev_vpd_MASK 0x00000001
2764 #define LPFC_G7_ASIC_1 0xd
2769 #define lpfc_mbx_rd_rev_fcph_low_SHIFT 0
2770 #define lpfc_mbx_rd_rev_fcph_low_MASK 0x000000FF
2773 #define lpfc_mbx_rd_rev_fcph_high_MASK 0x000000FF
2776 #define lpfc_mbx_rd_rev_ftr_lvl_low_MASK 0x000000FF
2779 #define lpfc_mbx_rd_rev_ftr_lvl_high_MASK 0x000000FF
2788 #define lpfc_mbx_rd_rev_avail_len_SHIFT 0
2789 #define lpfc_mbx_rd_rev_avail_len_MASK 0x00FFFFFF
2800 #define lpfc_mbx_rd_conf_extnts_inuse_MASK 0x00000001
2803 #define lpfc_mbx_rd_conf_lnk_numb_SHIFT 0
2804 #define lpfc_mbx_rd_conf_lnk_numb_MASK 0x0000003F
2807 #define lpfc_mbx_rd_conf_lnk_type_MASK 0x00000003
2809 #define LPFC_LNK_TYPE_GE 0
2812 #define lpfc_mbx_rd_conf_lnk_ldv_MASK 0x00000001
2815 #define lpfc_mbx_rd_conf_trunk_MASK 0x0000000F
2818 #define lpfc_mbx_rd_conf_pt_MASK 0x00000003
2821 #define lpfc_mbx_rd_conf_tf_MASK 0x00000001
2824 #define lpfc_mbx_rd_conf_ptv_MASK 0x00000001
2827 #define lpfc_mbx_rd_conf_topology_MASK 0x000000FF
2831 #define lpfc_mbx_rd_conf_e_d_tov_SHIFT 0
2832 #define lpfc_mbx_rd_conf_e_d_tov_MASK 0x0000FFFF
2836 #define lpfc_mbx_rd_conf_r_a_tov_SHIFT 0
2837 #define lpfc_mbx_rd_conf_r_a_tov_MASK 0x0000FFFF
2840 #define lpfc_mbx_rd_conf_link_speed_MASK 0x0000FFFF
2844 #define lpfc_mbx_rd_conf_bbscn_min_SHIFT 0
2845 #define lpfc_mbx_rd_conf_bbscn_min_MASK 0x0000000F
2848 #define lpfc_mbx_rd_conf_bbscn_max_MASK 0x0000000F
2851 #define lpfc_mbx_rd_conf_bbscn_def_MASK 0x0000000F
2854 #define lpfc_mbx_rd_conf_lmt_SHIFT 0
2855 #define lpfc_mbx_rd_conf_lmt_MASK 0x0000FFFF
2860 #define lpfc_mbx_rd_conf_xri_base_SHIFT 0
2861 #define lpfc_mbx_rd_conf_xri_base_MASK 0x0000FFFF
2864 #define lpfc_mbx_rd_conf_xri_count_MASK 0x0000FFFF
2867 #define lpfc_mbx_rd_conf_rpi_base_SHIFT 0
2868 #define lpfc_mbx_rd_conf_rpi_base_MASK 0x0000FFFF
2871 #define lpfc_mbx_rd_conf_rpi_count_MASK 0x0000FFFF
2874 #define lpfc_mbx_rd_conf_vpi_base_SHIFT 0
2875 #define lpfc_mbx_rd_conf_vpi_base_MASK 0x0000FFFF
2878 #define lpfc_mbx_rd_conf_vpi_count_MASK 0x0000FFFF
2881 #define lpfc_mbx_rd_conf_vfi_base_SHIFT 0
2882 #define lpfc_mbx_rd_conf_vfi_base_MASK 0x0000FFFF
2885 #define lpfc_mbx_rd_conf_vfi_count_MASK 0x0000FFFF
2889 #define lpfc_mbx_rd_conf_fcfi_count_MASK 0x0000FFFF
2892 #define lpfc_mbx_rd_conf_rq_count_SHIFT 0
2893 #define lpfc_mbx_rd_conf_rq_count_MASK 0x0000FFFF
2896 #define lpfc_mbx_rd_conf_eq_count_MASK 0x0000FFFF
2899 #define lpfc_mbx_rd_conf_wq_count_SHIFT 0
2900 #define lpfc_mbx_rd_conf_wq_count_MASK 0x0000FFFF
2903 #define lpfc_mbx_rd_conf_cq_count_MASK 0x0000FFFF
2909 #define lpfc_mbx_rq_ftr_qry_SHIFT 0
2910 #define lpfc_mbx_rq_ftr_qry_MASK 0x00000001
2913 #define lpfc_mbx_rq_ftr_rq_iaab_SHIFT 0
2914 #define lpfc_mbx_rq_ftr_rq_iaab_MASK 0x00000001
2917 #define lpfc_mbx_rq_ftr_rq_npiv_MASK 0x00000001
2920 #define lpfc_mbx_rq_ftr_rq_dif_MASK 0x00000001
2923 #define lpfc_mbx_rq_ftr_rq_vf_MASK 0x00000001
2926 #define lpfc_mbx_rq_ftr_rq_fcpi_MASK 0x00000001
2929 #define lpfc_mbx_rq_ftr_rq_fcpt_MASK 0x00000001
2932 #define lpfc_mbx_rq_ftr_rq_fcpc_MASK 0x00000001
2935 #define lpfc_mbx_rq_ftr_rq_ifip_MASK 0x00000001
2938 #define lpfc_mbx_rq_ftr_rq_iaar_MASK 0x00000001
2941 #define lpfc_mbx_rq_ftr_rq_perfh_MASK 0x00000001
2944 #define lpfc_mbx_rq_ftr_rq_mrqp_MASK 0x00000001
2947 #define lpfc_mbx_rq_ftr_rsp_iaab_SHIFT 0
2948 #define lpfc_mbx_rq_ftr_rsp_iaab_MASK 0x00000001
2951 #define lpfc_mbx_rq_ftr_rsp_npiv_MASK 0x00000001
2954 #define lpfc_mbx_rq_ftr_rsp_dif_MASK 0x00000001
2957 #define lpfc_mbx_rq_ftr_rsp_vf__MASK 0x00000001
2960 #define lpfc_mbx_rq_ftr_rsp_fcpi_MASK 0x00000001
2963 #define lpfc_mbx_rq_ftr_rsp_fcpt_MASK 0x00000001
2966 #define lpfc_mbx_rq_ftr_rsp_fcpc_MASK 0x00000001
2969 #define lpfc_mbx_rq_ftr_rsp_ifip_MASK 0x00000001
2972 #define lpfc_mbx_rq_ftr_rsp_perfh_MASK 0x00000001
2975 #define lpfc_mbx_rq_ftr_rsp_mrqp_MASK 0x00000001
2981 #define qs_SHIFT 0
2982 #define qs_MASK 0x00000001
2985 #define wr_MASK 0x00000001
2988 #define pf_MASK 0x000000ff
2991 #define cpn_MASK 0x000000ff
2994 #define list_offset_SHIFT 0
2995 #define list_offset_MASK 0x000000ff
2998 #define next_offset_MASK 0x000000ff
3001 #define elem_cnt_MASK 0x000000ff
3005 #define pn_0_MASK 0x000000ff
3008 #define pn_1_MASK 0x000000ff
3011 #define pn_2_MASK 0x000000ff
3013 #define pn_3_SHIFT 0
3014 #define pn_3_MASK 0x000000ff
3018 #define pn_4_MASK 0x000000ff
3021 #define pn_5_MASK 0x000000ff
3024 #define pn_6_MASK 0x000000ff
3026 #define pn_7_SHIFT 0
3027 #define pn_7_MASK 0x000000ff
3030 #define LPFC_SUPP_PAGES 0
3037 #define lpfc_mbx_memory_dump_type3_type_SHIFT 0
3038 #define lpfc_mbx_memory_dump_type3_type_MASK 0x0000000f
3041 #define lpfc_mbx_memory_dump_type3_link_MASK 0x000000ff
3044 #define lpfc_mbx_memory_dump_type3_page_no_SHIFT 0
3045 #define lpfc_mbx_memory_dump_type3_page_no_MASK 0x0000ffff
3048 #define lpfc_mbx_memory_dump_type3_offset_MASK 0x0000ffff
3051 #define lpfc_mbx_memory_dump_type3_length_SHIFT 0
3052 #define lpfc_mbx_memory_dump_type3_length_MASK 0x00ffffff
3059 #define DMP_PAGE_A0 0xa0
3060 #define DMP_PAGE_A2 0xa2
3071 #define SFF_PG0_CONNECTOR_UNKNOWN 0x00 /* Unknown */
3072 #define SFF_PG0_CONNECTOR_SC 0x01 /* SC */
3073 #define SFF_PG0_CONNECTOR_FC_COPPER1 0x02 /* FC style 1 copper connector */
3074 #define SFF_PG0_CONNECTOR_FC_COPPER2 0x03 /* FC style 2 copper connector */
3075 #define SFF_PG0_CONNECTOR_BNC 0x04 /* BNC / TNC */
3076 #define SFF_PG0_CONNECTOR__FC_COAX 0x05 /* FC coaxial headers */
3077 #define SFF_PG0_CONNECTOR_FIBERJACK 0x06 /* FiberJack */
3078 #define SFF_PG0_CONNECTOR_LC 0x07 /* LC */
3079 #define SFF_PG0_CONNECTOR_MT 0x08 /* MT - RJ */
3080 #define SFF_PG0_CONNECTOR_MU 0x09 /* MU */
3081 #define SFF_PG0_CONNECTOR_SF 0x0A /* SG */
3082 #define SFF_PG0_CONNECTOR_OPTICAL_PIGTAIL 0x0B /* Optical pigtail */
3083 #define SFF_PG0_CONNECTOR_OPTICAL_PARALLEL 0x0C /* MPO Parallel Optic */
3084 #define SFF_PG0_CONNECTOR_HSSDC_II 0x20 /* HSSDC II */
3085 #define SFF_PG0_CONNECTOR_COPPER_PIGTAIL 0x21 /* Copper pigtail */
3086 #define SFF_PG0_CONNECTOR_RJ45 0x22 /* RJ45 */
3090 #define SSF_IDENTIFIER 0
3131 #define SSF_TEMP_HIGH_ALARM 0
3253 #define qs_SHIFT 0
3254 #define qs_MASK 0x00000001
3257 #define wr_MASK 0x00000001
3260 #define pf_MASK 0x000000ff
3263 #define cpn_MASK 0x000000ff
3266 #define if_type_SHIFT 0
3267 #define if_type_MASK 0x00000007
3270 #define sli_rev_MASK 0x0000000f
3273 #define sli_family_MASK 0x000000ff
3276 #define featurelevel_1_MASK 0x000000ff
3279 #define featurelevel_2_MASK 0x0000001f
3282 #define fcoe_SHIFT 0
3283 #define fcoe_MASK 0x00000001
3286 #define fc_MASK 0x00000001
3289 #define nic_MASK 0x00000001
3292 #define iscsi_MASK 0x00000001
3295 #define rdma_MASK 0x00000001
3300 #define if_page_sz_SHIFT 0
3301 #define if_page_sz_MASK 0x0000ffff
3304 #define loopbk_scope_MASK 0x0000000f
3307 #define rq_db_window_MASK 0x0000000f
3310 #define eq_pages_SHIFT 0
3311 #define eq_pages_MASK 0x0000000f
3314 #define eqe_size_MASK 0x000000ff
3317 #define cq_pages_SHIFT 0
3318 #define cq_pages_MASK 0x0000000f
3321 #define cqe_size_MASK 0x000000ff
3324 #define mq_pages_SHIFT 0
3325 #define mq_pages_MASK 0x0000000f
3328 #define mqe_size_MASK 0x000000ff
3331 #define mq_elem_cnt_MASK 0x000000ff
3334 #define wq_pages_SHIFT 0
3335 #define wq_pages_MASK 0x0000ffff
3338 #define wqe_size_MASK 0x000000ff
3341 #define rq_pages_SHIFT 0
3342 #define rq_pages_MASK 0x0000ffff
3345 #define rqe_size_MASK 0x000000ff
3348 #define hdr_pages_SHIFT 0
3349 #define hdr_pages_MASK 0x0000000f
3352 #define hdr_size_MASK 0x0000000f
3355 #define hdr_pp_align_MASK 0x0000ffff
3358 #define sgl_pages_SHIFT 0
3359 #define sgl_pages_MASK 0x0000000f
3362 #define sgl_pp_align_MASK 0x0000ffff
3371 #define cfg_prot_type_SHIFT 0
3372 #define cfg_prot_type_MASK 0x000000FF
3375 #define cfg_ft_SHIFT 0
3376 #define cfg_ft_MASK 0x00000001
3379 #define cfg_sli_rev_MASK 0x0000000f
3382 #define cfg_sli_family_MASK 0x0000000f
3385 #define cfg_if_type_MASK 0x0000000f
3388 #define cfg_sli_hint_1_MASK 0x000000ff
3391 #define cfg_sli_hint_2_MASK 0x0000001f
3395 #define cfg_eqav_MASK 0x00000001
3400 #define cfg_cqv_MASK 0x00000003
3403 #define cfg_cqpsize_MASK 0x000000ff
3406 #define cfg_cqav_MASK 0x00000001
3411 #define cfg_mqv_MASK 0x00000003
3415 #define cfg_wqpcnt_SHIFT 0
3416 #define cfg_wqpcnt_MASK 0x0000000f
3419 #define cfg_wqsize_MASK 0x0000000f
3422 #define cfg_wqv_MASK 0x00000003
3425 #define cfg_wqpsize_MASK 0x000000ff
3430 #define cfg_rqv_MASK 0x00000003
3434 #define cfg_rq_db_window_MASK 0x0000000f
3437 #define cfg_fcoe_SHIFT 0
3438 #define cfg_fcoe_MASK 0x00000001
3441 #define cfg_ext_MASK 0x00000001
3444 #define cfg_hdrr_MASK 0x00000001
3447 #define cfg_phwq_MASK 0x00000001
3450 #define cfg_oas_MASK 0x00000001
3453 #define cfg_loopbk_scope_MASK 0x0000000f
3457 #define cfg_sgl_page_cnt_SHIFT 0
3458 #define cfg_sgl_page_cnt_MASK 0x0000000f
3461 #define cfg_sgl_page_size_MASK 0x000000ff
3464 #define cfg_sgl_pp_align_MASK 0x000000ff
3471 #define cfg_ext_embed_cb_SHIFT 0
3472 #define cfg_ext_embed_cb_MASK 0x00000001
3475 #define cfg_mds_diags_MASK 0x00000001
3478 #define cfg_nvme_MASK 0x00000001
3481 #define cfg_xib_MASK 0x00000001
3484 #define cfg_xpsgl_MASK 0x00000001
3487 #define cfg_eqdr_MASK 0x00000001
3490 #define cfg_nosr_MASK 0x00000001
3494 #define cfg_bv1s_MASK 0x00000001
3497 #define cfg_pvl_MASK 0x00000001
3501 #define cfg_nsler_MASK 0x00000001
3505 #define cfg_max_tow_xri_SHIFT 0
3506 #define cfg_max_tow_xri_MASK 0x0000ffff
3514 #define cfg_frag_field_offset_SHIFT 0
3515 #define cfg_frag_field_offset_MASK 0x0000ffff
3519 #define cfg_frag_field_size_MASK 0x0000ffff
3523 #define cfg_sgl_field_offset_SHIFT 0
3524 #define cfg_sgl_field_offset_MASK 0x0000ffff
3528 #define cfg_sgl_field_size_MASK 0x0000ffff
3536 #define LPFC_SET_UE_RECOVERY 0x10
3537 #define LPFC_SET_MDS_DIAGS 0x12
3538 #define LPFC_SET_DUAL_DUMP 0x1e
3544 #define lpfc_mbx_set_feature_UER_SHIFT 0
3545 #define lpfc_mbx_set_feature_UER_MASK 0x00000001
3548 #define lpfc_mbx_set_feature_mds_MASK 0x00000001
3551 #define lpfc_mbx_set_feature_mds_deep_loopbk_MASK 0x00000001
3553 #define lpfc_mbx_set_feature_dd_SHIFT 0
3554 #define lpfc_mbx_set_feature_dd_MASK 0x00000001
3557 #define lpfc_mbx_set_feature_ddquery_MASK 0x00000001
3559 #define LPFC_DISABLE_DUAL_DUMP 0
3563 #define lpfc_mbx_set_feature_UERP_SHIFT 0
3564 #define lpfc_mbx_set_feature_UERP_MASK 0x0000ffff
3567 #define lpfc_mbx_set_feature_UESR_MASK 0x0000ffff
3572 #define LPFC_SET_HOST_OS_DRIVER_VERSION 0x2
3585 #define lpfc_mbx_set_trunk_mode_SHIFT 0
3586 #define lpfc_mbx_set_trunk_mode_MASK 0xFF
3603 #define lpfc_rsrc_desc_pcie_type_SHIFT 0
3604 #define lpfc_rsrc_desc_pcie_type_MASK 0x000000ff
3606 #define LPFC_RSRC_DESC_TYPE_PCIE 0x40
3608 #define lpfc_rsrc_desc_pcie_length_MASK 0x000000ff
3611 #define lpfc_rsrc_desc_pcie_pfnum_SHIFT 0
3612 #define lpfc_rsrc_desc_pcie_pfnum_MASK 0x000000ff
3616 #define lpfc_rsrc_desc_pcie_sriov_sta_SHIFT 0
3617 #define lpfc_rsrc_desc_pcie_sriov_sta_MASK 0x000000ff
3620 #define lpfc_rsrc_desc_pcie_pf_sta_MASK 0x000000ff
3623 #define lpfc_rsrc_desc_pcie_pf_type_MASK 0x000000ff
3626 #define lpfc_rsrc_desc_pcie_nr_virtfn_SHIFT 0
3627 #define lpfc_rsrc_desc_pcie_nr_virtfn_MASK 0x0000ffff
3633 #define lpfc_rsrc_desc_fcfcoe_type_SHIFT 0
3634 #define lpfc_rsrc_desc_fcfcoe_type_MASK 0x000000ff
3636 #define LPFC_RSRC_DESC_TYPE_FCFCOE 0x43
3638 #define lpfc_rsrc_desc_fcfcoe_length_MASK 0x000000ff
3640 #define LPFC_RSRC_DESC_TYPE_FCFCOE_V0_RSVD 0
3644 #define lpfc_rsrc_desc_fcfcoe_vfnum_SHIFT 0
3645 #define lpfc_rsrc_desc_fcfcoe_vfnum_MASK 0x000000ff
3648 #define lpfc_rsrc_desc_fcfcoe_pfnum_MASK 0x000007ff
3651 #define lpfc_rsrc_desc_fcfcoe_rpi_cnt_SHIFT 0
3652 #define lpfc_rsrc_desc_fcfcoe_rpi_cnt_MASK 0x0000ffff
3655 #define lpfc_rsrc_desc_fcfcoe_xri_cnt_MASK 0x0000ffff
3658 #define lpfc_rsrc_desc_fcfcoe_wq_cnt_SHIFT 0
3659 #define lpfc_rsrc_desc_fcfcoe_wq_cnt_MASK 0x0000ffff
3662 #define lpfc_rsrc_desc_fcfcoe_rq_cnt_MASK 0x0000ffff
3665 #define lpfc_rsrc_desc_fcfcoe_cq_cnt_SHIFT 0
3666 #define lpfc_rsrc_desc_fcfcoe_cq_cnt_MASK 0x0000ffff
3669 #define lpfc_rsrc_desc_fcfcoe_vpi_cnt_MASK 0x0000ffff
3672 #define lpfc_rsrc_desc_fcfcoe_fcfi_cnt_SHIFT 0
3673 #define lpfc_rsrc_desc_fcfcoe_fcfi_cnt_MASK 0x0000ffff
3676 #define lpfc_rsrc_desc_fcfcoe_vfi_cnt_MASK 0x0000ffff
3686 #define lpfc_rsrc_desc_fcfcoe_lnk_nr_SHIFT 0
3687 #define lpfc_rsrc_desc_fcfcoe_lnk_nr_MASK 0x0000003f
3690 #define lpfc_rsrc_desc_fcfcoe_lnk_tp_MASK 0x00000003
3693 #define lpfc_rsrc_desc_fcfcoe_lmc_MASK 0x00000001
3696 #define lpfc_rsrc_desc_fcfcoe_lld_MASK 0x00000001
3699 #define lpfc_rsrc_desc_fcfcoe_eq_cnt_MASK 0x0000ffff
3717 #define LPFC_CFG_TYPE_PERSISTENT_OVERRIDE 0x0
3718 #define LPFC_CFG_TYPE_FACTURY_DEFAULT 0x1
3719 #define LPFC_CFG_TYPE_CURRENT_ACTIVE 0x2
3731 #define LPFC_CFG_TYPE_PERSISTENT_OVERRIDE 0x0
3732 #define LPFC_CFG_TYPE_FACTURY_DEFAULT 0x1
3733 #define LPFC_CFG_TYPE_CURRENT_ACTIVE 0x2
3737 #define lpfc_mbx_get_prof_cfg_prof_id_SHIFT 0
3738 #define lpfc_mbx_get_prof_cfg_prof_id_MASK 0x000000ff
3741 #define lpfc_mbx_get_prof_cfg_prof_tp_MASK 0x00000003
3755 #define lpfc_cntl_attr_eprom_ver_lo_SHIFT 0
3756 #define lpfc_cntl_attr_eprom_ver_lo_MASK 0x000000ff
3759 #define lpfc_cntl_attr_eprom_ver_hi_MASK 0x000000ff
3776 #define lpfc_cntl_attr_max_cbd_len_SHIFT 0
3777 #define lpfc_cntl_attr_max_cbd_len_MASK 0x0000ffff
3780 #define lpfc_cntl_attr_asic_rev_MASK 0x000000ff
3783 #define lpfc_cntl_attr_gen_guid0_MASK 0x000000ff
3787 #define lpfc_cntl_attr_gen_guid13_14_SHIFT 0
3788 #define lpfc_cntl_attr_gen_guid13_14_MASK 0x0000ffff
3791 #define lpfc_cntl_attr_gen_guid15_MASK 0x000000ff
3794 #define lpfc_cntl_attr_hba_port_cnt_MASK 0x000000ff
3797 #define lpfc_cntl_attr_dflt_lnk_tmo_SHIFT 0
3798 #define lpfc_cntl_attr_dflt_lnk_tmo_MASK 0x0000ffff
3801 #define lpfc_cntl_attr_multi_func_dev_MASK 0x000000ff
3804 #define lpfc_cntl_attr_cache_valid_SHIFT 0
3805 #define lpfc_cntl_attr_cache_valid_MASK 0x000000ff
3808 #define lpfc_cntl_attr_hba_status_MASK 0x000000ff
3811 #define lpfc_cntl_attr_max_domain_MASK 0x000000ff
3814 #define lpfc_cntl_attr_lnk_numb_MASK 0x0000003f
3817 #define lpfc_cntl_attr_lnk_type_MASK 0x00000003
3824 #define lpfc_cntl_attr_pci_vendor_id_SHIFT 0
3825 #define lpfc_cntl_attr_pci_vendor_id_MASK 0x0000ffff
3828 #define lpfc_cntl_attr_pci_device_id_MASK 0x0000ffff
3831 #define lpfc_cntl_attr_pci_subvdr_id_SHIFT 0
3832 #define lpfc_cntl_attr_pci_subvdr_id_MASK 0x0000ffff
3835 #define lpfc_cntl_attr_pci_subsys_id_MASK 0x0000ffff
3838 #define lpfc_cntl_attr_pci_bus_num_SHIFT 0
3839 #define lpfc_cntl_attr_pci_bus_num_MASK 0x000000ff
3842 #define lpfc_cntl_attr_pci_dev_num_MASK 0x000000ff
3845 #define lpfc_cntl_attr_pci_fnc_num_MASK 0x000000ff
3848 #define lpfc_cntl_attr_inf_type_MASK 0x000000ff
3852 #define lpfc_cntl_attr_num_netfil_SHIFT 0
3853 #define lpfc_cntl_attr_num_netfil_MASK 0x000000ff
3868 #define lpfc_mbx_get_port_name_lnk_type_SHIFT 0
3869 #define lpfc_mbx_get_port_name_lnk_type_MASK 0x00000003
3874 #define lpfc_mbx_get_port_name_name0_SHIFT 0
3875 #define lpfc_mbx_get_port_name_name0_MASK 0x000000FF
3878 #define lpfc_mbx_get_port_name_name1_MASK 0x000000FF
3881 #define lpfc_mbx_get_port_name_name2_MASK 0x000000FF
3884 #define lpfc_mbx_get_port_name_name3_MASK 0x000000FF
3886 #define LPFC_LINK_NUMBER_0 0
3895 #define MB_CQE_STATUS_SUCCESS 0x0
3896 #define MB_CQE_STATUS_INSUFFICIENT_PRIVILEGES 0x1
3897 #define MB_CQE_STATUS_INVALID_PARAMETER 0x2
3898 #define MB_CQE_STATUS_INSUFFICIENT_RESOURCES 0x3
3899 #define MB_CEQ_STATUS_QUEUE_FLUSHING 0x4
3900 #define MB_CQE_STATUS_DMA_FAILED 0x5
3909 #define lpfc_wr_object_eof_MASK 0x00000001
3912 #define lpfc_wr_object_eas_MASK 0x00000001
3914 #define lpfc_wr_object_write_length_SHIFT 0
3915 #define lpfc_wr_object_write_length_MASK 0x00FFFFFF
3925 #define lpfc_wr_object_change_status_SHIFT 0
3926 #define lpfc_wr_object_change_status_MASK 0x000000FF
3928 #define LPFC_CHANGE_STATUS_NO_RESET_NEEDED 0x00
3929 #define LPFC_CHANGE_STATUS_PHYS_DEV_RESET 0x01
3930 #define LPFC_CHANGE_STATUS_FW_RESET 0x02
3931 #define LPFC_CHANGE_STATUS_PORT_MIGRATION 0x04
3932 #define LPFC_CHANGE_STATUS_PCI_RESET 0x05
3934 #define lpfc_wr_object_csf_MASK 0x00000001
3944 #define lpfc_mqe_status_MASK 0x0000FFFF
3947 #define lpfc_mqe_command_MASK 0x000000FF
4012 #define lpfc_mcqe_status_SHIFT 0
4013 #define lpfc_mcqe_status_MASK 0x0000FFFF
4016 #define lpfc_mcqe_ext_status_MASK 0x0000FFFF
4022 #define lpfc_trailer_valid_MASK 0x00000001
4025 #define lpfc_trailer_async_MASK 0x00000001
4028 #define lpfc_trailer_hpi_MASK 0x00000001
4031 #define lpfc_trailer_completed_MASK 0x00000001
4034 #define lpfc_trailer_consumed_MASK 0x00000001
4037 #define lpfc_trailer_type_MASK 0x000000FF
4040 #define lpfc_trailer_code_MASK 0x000000FF
4042 #define LPFC_TRAILER_CODE_LINK 0x1
4043 #define LPFC_TRAILER_CODE_FCOE 0x2
4044 #define LPFC_TRAILER_CODE_DCBX 0x3
4045 #define LPFC_TRAILER_CODE_GRP5 0x5
4046 #define LPFC_TRAILER_CODE_FC 0x10
4047 #define LPFC_TRAILER_CODE_SLI 0x11
4053 #define lpfc_acqe_link_speed_MASK 0x000000FF
4055 #define LPFC_ASYNC_LINK_SPEED_ZERO 0x0
4056 #define LPFC_ASYNC_LINK_SPEED_10MBPS 0x1
4057 #define LPFC_ASYNC_LINK_SPEED_100MBPS 0x2
4058 #define LPFC_ASYNC_LINK_SPEED_1GBPS 0x3
4059 #define LPFC_ASYNC_LINK_SPEED_10GBPS 0x4
4060 #define LPFC_ASYNC_LINK_SPEED_20GBPS 0x5
4061 #define LPFC_ASYNC_LINK_SPEED_25GBPS 0x6
4062 #define LPFC_ASYNC_LINK_SPEED_40GBPS 0x7
4063 #define LPFC_ASYNC_LINK_SPEED_100GBPS 0x8
4065 #define lpfc_acqe_link_duplex_MASK 0x000000FF
4067 #define LPFC_ASYNC_LINK_DUPLEX_NONE 0x0
4068 #define LPFC_ASYNC_LINK_DUPLEX_HALF 0x1
4069 #define LPFC_ASYNC_LINK_DUPLEX_FULL 0x2
4071 #define lpfc_acqe_link_status_MASK 0x000000FF
4073 #define LPFC_ASYNC_LINK_STATUS_DOWN 0x0
4074 #define LPFC_ASYNC_LINK_STATUS_UP 0x1
4075 #define LPFC_ASYNC_LINK_STATUS_LOGICAL_DOWN 0x2
4076 #define LPFC_ASYNC_LINK_STATUS_LOGICAL_UP 0x3
4078 #define lpfc_acqe_link_type_MASK 0x00000003
4080 #define lpfc_acqe_link_number_SHIFT 0
4081 #define lpfc_acqe_link_number_MASK 0x0000003F
4084 #define lpfc_acqe_link_fault_SHIFT 0
4085 #define lpfc_acqe_link_fault_MASK 0x000000FF
4087 #define LPFC_ASYNC_LINK_FAULT_NONE 0x0
4088 #define LPFC_ASYNC_LINK_FAULT_LOCAL 0x1
4089 #define LPFC_ASYNC_LINK_FAULT_REMOTE 0x2
4090 #define LPFC_ASYNC_LINK_FAULT_LR_LRR 0x3
4092 #define lpfc_acqe_logical_link_speed_MASK 0x0000FFFF
4096 #define LPFC_LINK_EVENT_TYPE_PHYSICAL 0x0
4097 #define LPFC_LINK_EVENT_TYPE_VIRTUAL 0x1
4103 #define lpfc_acqe_fip_fcf_count_SHIFT 0
4104 #define lpfc_acqe_fip_fcf_count_MASK 0x0000FFFF
4107 #define lpfc_acqe_fip_event_type_MASK 0x0000FFFF
4111 #define LPFC_FIP_EVENT_TYPE_NEW_FCF 0x1
4112 #define LPFC_FIP_EVENT_TYPE_FCF_TABLE_FULL 0x2
4113 #define LPFC_FIP_EVENT_TYPE_FCF_DEAD 0x3
4114 #define LPFC_FIP_EVENT_TYPE_CVL 0x4
4115 #define LPFC_FIP_EVENT_TYPE_FCF_PARAM_MOD 0x5
4128 #define lpfc_acqe_grp5_type_MASK 0x00000003
4130 #define lpfc_acqe_grp5_number_SHIFT 0
4131 #define lpfc_acqe_grp5_number_MASK 0x0000003F
4135 #define lpfc_acqe_grp5_llink_spd_MASK 0x0000FFFF
4146 #define lpfc_acqe_fc_la_speed_MASK 0x000000FF
4148 #define LPFC_FC_LA_SPEED_UNKNOWN 0x0
4149 #define LPFC_FC_LA_SPEED_1G 0x1
4150 #define LPFC_FC_LA_SPEED_2G 0x2
4151 #define LPFC_FC_LA_SPEED_4G 0x4
4152 #define LPFC_FC_LA_SPEED_8G 0x8
4153 #define LPFC_FC_LA_SPEED_10G 0xA
4154 #define LPFC_FC_LA_SPEED_16G 0x10
4155 #define LPFC_FC_LA_SPEED_32G 0x20
4156 #define LPFC_FC_LA_SPEED_64G 0x21
4157 #define LPFC_FC_LA_SPEED_128G 0x22
4158 #define LPFC_FC_LA_SPEED_256G 0x23
4160 #define lpfc_acqe_fc_la_topology_MASK 0x000000FF
4162 #define LPFC_FC_LA_TOP_UNKOWN 0x0
4163 #define LPFC_FC_LA_TOP_P2P 0x1
4164 #define LPFC_FC_LA_TOP_FCAL 0x2
4165 #define LPFC_FC_LA_TOP_INTERNAL_LOOP 0x3
4166 #define LPFC_FC_LA_TOP_SERDES_LOOP 0x4
4168 #define lpfc_acqe_fc_la_att_type_MASK 0x000000FF
4170 #define LPFC_FC_LA_TYPE_LINK_UP 0x1
4171 #define LPFC_FC_LA_TYPE_LINK_DOWN 0x2
4172 #define LPFC_FC_LA_TYPE_NO_HARD_ALPA 0x3
4173 #define LPFC_FC_LA_TYPE_MDS_LINK_DOWN 0x4
4174 #define LPFC_FC_LA_TYPE_MDS_LOOPBACK 0x5
4175 #define LPFC_FC_LA_TYPE_UNEXP_WWPN 0x6
4176 #define LPFC_FC_LA_TYPE_TRUNKING_EVENT 0x7
4178 #define lpfc_acqe_fc_la_port_type_MASK 0x00000003
4180 #define LPFC_LINK_TYPE_ETHERNET 0x0
4181 #define LPFC_LINK_TYPE_FC 0x1
4182 #define lpfc_acqe_fc_la_port_number_SHIFT 0
4183 #define lpfc_acqe_fc_la_port_number_MASK 0x0000003F
4186 /* Attention Type is 0x07 (Trunking Event) word0 */
4188 #define lpfc_acqe_fc_la_trunk_link_status_port0_MASK 0x0000001
4191 #define lpfc_acqe_fc_la_trunk_link_status_port1_MASK 0x0000001
4194 #define lpfc_acqe_fc_la_trunk_link_status_port2_MASK 0x0000001
4197 #define lpfc_acqe_fc_la_trunk_link_status_port3_MASK 0x0000001
4200 #define lpfc_acqe_fc_la_trunk_config_port0_MASK 0x0000001
4203 #define lpfc_acqe_fc_la_trunk_config_port1_MASK 0x0000001
4206 #define lpfc_acqe_fc_la_trunk_config_port2_MASK 0x0000001
4209 #define lpfc_acqe_fc_la_trunk_config_port3_MASK 0x0000001
4213 #define lpfc_acqe_fc_la_llink_spd_MASK 0x0000FFFF
4215 #define lpfc_acqe_fc_la_fault_SHIFT 0
4216 #define lpfc_acqe_fc_la_fault_MASK 0x000000FF
4218 #define lpfc_acqe_fc_la_trunk_fault_SHIFT 0
4219 #define lpfc_acqe_fc_la_trunk_fault_MASK 0x0000000F
4222 #define lpfc_acqe_fc_la_trunk_linkmask_MASK 0x000000F
4224 #define LPFC_FC_LA_FAULT_NONE 0x0
4225 #define LPFC_FC_LA_FAULT_LOCAL 0x1
4226 #define LPFC_FC_LA_FAULT_REMOTE 0x2
4229 #define LPFC_FC_LA_EVENT_TYPE_FC_LINK 0x1
4230 #define LPFC_FC_LA_EVENT_TYPE_SHARED_LINK 0x2
4236 #define lpfc_sli_misconfigured_port0_state_SHIFT 0
4237 #define lpfc_sli_misconfigured_port0_state_MASK 0x000000FF
4240 #define lpfc_sli_misconfigured_port1_state_MASK 0x000000FF
4243 #define lpfc_sli_misconfigured_port2_state_MASK 0x000000FF
4246 #define lpfc_sli_misconfigured_port3_state_MASK 0x000000FF
4249 #define lpfc_sli_misconfigured_port0_op_SHIFT 0
4250 #define lpfc_sli_misconfigured_port0_op_MASK 0x00000001
4253 #define lpfc_sli_misconfigured_port0_severity_MASK 0x00000003
4256 #define lpfc_sli_misconfigured_port1_op_MASK 0x00000001
4259 #define lpfc_sli_misconfigured_port1_severity_MASK 0x00000003
4262 #define lpfc_sli_misconfigured_port2_op_MASK 0x00000001
4265 #define lpfc_sli_misconfigured_port2_severity_MASK 0x00000003
4268 #define lpfc_sli_misconfigured_port3_op_MASK 0x00000001
4271 #define lpfc_sli_misconfigured_port3_severity_MASK 0x00000003
4274 #define LPFC_SLI_EVENT_STATUS_VALID 0x00
4275 #define LPFC_SLI_EVENT_STATUS_NOT_PRESENT 0x01
4276 #define LPFC_SLI_EVENT_STATUS_WRONG_TYPE 0x02
4277 #define LPFC_SLI_EVENT_STATUS_UNSUPPORTED 0x03
4278 #define LPFC_SLI_EVENT_STATUS_UNQUALIFIED 0x04
4279 #define LPFC_SLI_EVENT_STATUS_UNCERTIFIED 0x05
4287 #define LPFC_SLI_EVENT_TYPE_PORT_ERROR 0x1
4288 #define LPFC_SLI_EVENT_TYPE_OVER_TEMP 0x2
4289 #define LPFC_SLI_EVENT_TYPE_NORM_TEMP 0x3
4290 #define LPFC_SLI_EVENT_TYPE_NVLOG_POST 0x4
4291 #define LPFC_SLI_EVENT_TYPE_DIAG_DUMP 0x5
4292 #define LPFC_SLI_EVENT_TYPE_MISCONFIGURED 0x9
4293 #define LPFC_SLI_EVENT_TYPE_REMOTE_DPORT 0xA
4294 #define LPFC_SLI_EVENT_TYPE_MISCONF_FAWWN 0xF
4295 #define LPFC_SLI_EVENT_TYPE_EEPROM_FAILURE 0x10
4312 #define NO_XRI 0xffff
4316 #define wqe_xri_tag_SHIFT 0
4317 #define wqe_xri_tag_MASK 0x0000FFFF
4320 #define wqe_ctxt_tag_MASK 0x0000FFFF
4323 #define wqe_dif_SHIFT 0
4324 #define wqe_dif_MASK 0x00000003
4330 #define wqe_ct_MASK 0x00000003
4333 #define wqe_status_MASK 0x0000000f
4336 #define wqe_cmnd_MASK 0x000000ff
4339 #define wqe_class_MASK 0x00000007
4342 #define wqe_ar_MASK 0x00000001
4348 #define wqe_pu_MASK 0x00000003
4351 #define wqe_erp_MASK 0x00000001
4357 #define wqe_lnk_MASK 0x00000001
4360 #define wqe_tmo_MASK 0x000000ff
4364 #define wqe_reqtag_SHIFT 0
4365 #define wqe_reqtag_MASK 0x0000FFFF
4368 #define wqe_temp_rpi_MASK 0x0000FFFF
4371 #define wqe_rcvoxid_MASK 0x0000FFFF
4374 #define wqe_sof_MASK 0x000000FF
4377 #define wqe_eof_MASK 0x000000FF
4380 #define wqe_ebde_cnt_SHIFT 0
4381 #define wqe_ebde_cnt_MASK 0x0000000f
4384 #define wqe_nvme_MASK 0x00000001
4387 #define wqe_oas_MASK 0x00000001
4390 #define wqe_lenloc_MASK 0x00000003
4392 #define LPFC_WQE_LENLOC_NONE 0
4397 #define wqe_qosd_MASK 0x00000001
4400 #define wqe_xbl_MASK 0x00000001
4403 #define wqe_iod_MASK 0x00000001
4405 #define LPFC_WQE_IOD_NONE 0
4406 #define LPFC_WQE_IOD_WRITE 0
4409 #define wqe_dbde_MASK 0x00000001
4412 #define wqe_wqes_MASK 0x00000001
4416 #define wqe_wqid_MASK 0x00007fff
4419 #define wqe_pri_MASK 0x00000007
4422 #define wqe_pv_MASK 0x00000001
4425 #define wqe_xc_MASK 0x00000001
4428 #define wqe_sr_MASK 0x00000001
4431 #define wqe_ccpe_MASK 0x00000001
4434 #define wqe_ccp_MASK 0x000000ff
4437 #define wqe_cmd_type_SHIFT 0
4438 #define wqe_cmd_type_MASK 0x0000000f
4441 #define wqe_els_id_MASK 0x00000003
4446 #define LPFC_ELS_ID_DEFAULT 0
4448 #define wqe_irsp_MASK 0x00000001
4451 #define wqe_pbde_MASK 0x00000001
4454 #define wqe_sup_MASK 0x00000001
4457 #define wqe_wqec_MASK 0x00000001
4460 #define wqe_irsplen_MASK 0x0000000f
4463 #define wqe_cqid_MASK 0x0000ffff
4465 #define LPFC_WQE_CQ_ID_DEFAULT 0xffff
4470 #define wqe_els_did_SHIFT 0
4471 #define wqe_els_did_MASK 0x00FFFFFF
4474 #define wqe_xmit_bls_pt_MASK 0x00000003
4477 #define wqe_xmit_bls_ar_MASK 0x00000001
4480 #define wqe_xmit_bls_xo_MASK 0x00000001
4497 #define els_req64_sid_SHIFT 0
4498 #define els_req64_sid_MASK 0x00FFFFFF
4501 #define els_req64_sp_MASK 0x00000001
4504 #define els_req64_vf_MASK 0x00000001
4510 #define els_req64_vfid_MASK 0x00000FFF
4513 #define els_req64_pri_MASK 0x00000007
4517 #define els_req64_hopcnt_MASK 0x000000ff
4527 #define els_rsp64_sid_SHIFT 0
4528 #define els_rsp64_sid_MASK 0x00FFFFFF
4531 #define els_rsp64_sp_MASK 0x00000001
4536 #define wqe_rsp_temp_rpi_SHIFT 0
4537 #define wqe_rsp_temp_rpi_MASK 0x0000FFFF
4546 #define xmit_bls_rsp64_acc_seq_id_MASK 0x000000ff
4549 #define xmit_bls_rsp64_acc_seq_id_vald_MASK 0x000000ff
4552 #define xmit_bls_rsp64_rjt_vspec_SHIFT 0
4553 #define xmit_bls_rsp64_rjt_vspec_MASK 0x000000ff
4556 #define xmit_bls_rsp64_rjt_expc_MASK 0x000000ff
4559 #define xmit_bls_rsp64_rjt_rsnc_MASK 0x000000ff
4562 #define xmit_bls_rsp64_rxid_SHIFT 0
4563 #define xmit_bls_rsp64_rxid_MASK 0x0000ffff
4566 #define xmit_bls_rsp64_oxid_MASK 0x0000ffff
4569 #define xmit_bls_rsp64_seqcnthi_SHIFT 0
4570 #define xmit_bls_rsp64_seqcnthi_MASK 0x0000ffff
4573 #define xmit_bls_rsp64_seqcntlo_MASK 0x0000ffff
4580 #define xmit_bls_rsp64_temprpi_SHIFT 0
4581 #define xmit_bls_rsp64_temprpi_MASK 0x0000ffff
4589 #define wqe_si_MASK 0x000000001
4592 #define wqe_la_MASK 0x000000001
4595 #define wqe_xo_MASK 0x000000001
4598 #define wqe_ls_MASK 0x000000001
4601 #define wqe_dfctl_MASK 0x0000000ff
4604 #define wqe_type_MASK 0x0000000ff
4607 #define wqe_rctl_MASK 0x0000000ff
4647 #define prli_acc_rsp_code_MASK 0x0000000f
4650 #define prli_estabImagePair_MASK 0x00000001
4653 #define prli_type_code_ext_MASK 0x000000ff
4656 #define prli_type_code_MASK 0x000000ff
4662 #define prli_fba_SHIFT 0
4663 #define prli_fba_MASK 0x00000001
4666 #define prli_disc_MASK 0x00000001
4669 #define prli_tgt_MASK 0x00000001
4672 #define prli_init_MASK 0x00000001
4675 #define prli_conf_MASK 0x00000001
4678 #define prli_nsler_MASK 0x00000001
4681 #define prli_fb_sz_SHIFT 0
4682 #define prli_fb_sz_MASK 0x0000ffff
4688 uint32_t rsrvd[5]; /* words 0-4 */
4701 #define abort_cmd_ia_SHIFT 0
4702 #define abort_cmd_ia_MASK 0x000000001
4705 #define abort_cmd_criteria_MASK 0x0000000ff
4717 #define cmd_buff_len_MASK 0x00000ffff
4719 #define payload_offset_len_SHIFT 0
4720 #define payload_offset_len_MASK 0x0000ffff
4733 #define cmd_buff_len_MASK 0x00000ffff
4735 #define payload_offset_len_SHIFT 0
4736 #define payload_offset_len_MASK 0x0000ffff
4746 struct ulp_bde64 bde; /* words 0-2 */
4749 #define cmd_buff_len_MASK 0x00000ffff
4751 #define payload_offset_len_SHIFT 0
4752 #define payload_offset_len_MASK 0x0000ffff
4789 #define CMD_SEND_FRAME 0xE1
4792 struct ulp_bde64 bde; /* words 0-2 */
4860 #define MAGIC_NUMBER_G6 0xFEAA0003
4861 #define MAGIC_NUMBER_G7 0xFEAA0005
4868 #define lpfc_grp_hdr_file_type_MASK 0x000000FF
4871 #define lpfc_grp_hdr_id_MASK 0x000000FF
4879 #define FCP_COMMAND 0x0
4880 #define NVME_READ_CMD 0x0
4881 #define FCP_COMMAND_DATA_OUT 0x1
4882 #define NVME_WRITE_CMD 0x1
4883 #define FCP_COMMAND_TRECEIVE 0x2
4884 #define FCP_COMMAND_TRSP 0x3
4885 #define FCP_COMMAND_TSEND 0x7
4886 #define OTHER_COMMAND 0x8
4887 #define ELS_COMMAND_NON_FIP 0xC
4888 #define ELS_COMMAND_FIP 0xD
4890 #define LPFC_NVME_EMBED_CMD 0x0
4891 #define LPFC_NVME_EMBED_WRITE 0x1
4892 #define LPFC_NVME_EMBED_READ 0x2
4895 #define CMD_ABORT_XRI_WQE 0x0F
4896 #define CMD_XMIT_SEQUENCE64_WQE 0x82
4897 #define CMD_XMIT_BCAST64_WQE 0x84
4898 #define CMD_ELS_REQUEST64_WQE 0x8A
4899 #define CMD_XMIT_ELS_RSP64_WQE 0x95
4900 #define CMD_XMIT_BLS_RSP64_WQE 0x97
4901 #define CMD_FCP_IWRITE64_WQE 0x98
4902 #define CMD_FCP_IREAD64_WQE 0x9A
4903 #define CMD_FCP_ICMND64_WQE 0x9C
4904 #define CMD_FCP_TSEND64_WQE 0x9F
4905 #define CMD_FCP_TRECEIVE64_WQE 0xA1
4906 #define CMD_FCP_TRSP64_WQE 0xA3
4907 #define CMD_GEN_REQUEST64_WQE 0xC2
4909 #define CMD_WQE_MASK 0xff