Lines Matching full:transfer
288 #define SCSIXFERDONE 0x0800 /* SCSI SCSI transfer done */
289 #define SCSIXFERCNT_2_ZERO 0x0100 /* SCSI SCSI transfer count to zero */
311 #define DO_CLRFIFO 0x0004 /* Clear SCSI transfer FIFO */
357 /* transfer. */
363 /* are used to transfer data */
368 /* are used to transfer data */
371 /* 02-00 0 PERIOD[2:0]/ Synchronous SCSI Transfer Rate. */
373 /* the Synchronous SCSI Transfer */
419 #define TRM_S1040_SCSI_COUNTER 0x88 /* SCSI Transfer Counter 24bits(R/W) */
451 #define SCMD_FIFO_OUT 0xC0 /* SCSI FIFO transfer out */
452 #define SCMD_DMA_OUT 0xC1 /* SCSI DMA transfer out */
453 #define SCMD_FIFO_IN 0xC2 /* SCSI FIFO transfer in */
454 #define SCMD_DMA_IN 0xC3 /* SCSI DMA transfer in */
466 /* C0 Transfer information out with FIFO */
467 /* C1 Transfer information out with DMA */
468 /* C2 Transfer information in with FIFO */
469 /* C3 Transfer information in with DMA */
471 /* 50 Initiator transfer information out sequence without ATN */
473 /* 70 Initiator transfer information out sequence with ATN */
475 /* 74 Initiator transfer information out sequence with ATN3 */
477 /* 52 Initiator transfer information in sequence without ATN */
479 /* 72 Initiator transfer information in sequence with ATN */
481 /* 76 Initiator transfer information in sequence with ATN3 */
483 /* 90 Initiator transfer information out command complete */
485 /* 92 Initiator transfer information in command complete */
510 #define TCR0_PERIOD_MASK 0x0700 /* Transfer rate */
530 #define XFERDATAIN_SG 0x0103 /* Transfer data in w/ SG */
531 #define XFERDATAOUT_SG 0x0102 /* Transfer data out w/ SG */
532 #define XFERDATAIN 0x0101 /* Transfer data in w/o SG */
533 #define XFERDATAOUT 0x0100 /* Transfer data out w/o SG */
539 #define STOPDMAXFER 0x08 /* Stop DMA transfer */
540 #define ABORTXFER 0x04 /* Abort DMA transfer */
541 #define CLRXFIFO 0x02 /* Clear DMA transfer FIFO */
542 #define STARTDMAXFER 0x01 /* Start DMA transfer */
547 #define XFERPENDING 0x80 /* Transfer pending */
550 #define FORCEDMACOMP 0x10 /* Force DMA transfer complete */
551 #define DMAXFERERROR 0x08 /* DMA transfer error */
552 #define DMAXFERABORT 0x04 /* DMA transfer abort */
557 #define EN_FORCEDMACOMP 0x10 /* Force DMA transfer complete */
558 #define EN_DMAXFERERROR 0x08 /* DMA transfer error */
559 #define EN_DMAXFERABORT 0x04 /* DMA transfer abort */
573 #define TRM_S1040_DMA_XCNT 0xA8 /* DMA Transfer Counter (R/W), 24bits */
574 #define TRM_S1040_DMA_CXCNT 0xAC /* DMA Current Transfer Counter (R) */
575 #define TRM_S1040_DMA_XLOWADDR 0xB0 /* DMA Transfer Physical Low Address */
576 #define TRM_S1040_DMA_XHIGHADDR 0xB4 /* DMA Transfer Physical High Address */