14  * Note that reading the DSR (DryIce Status Register) automatically clears
54 #define DSR       0x14           /* Status Reg */  macro
102  * @dsr: copy of the DSR register
113 	u32 dsr;  member
183 static void di_report_tamper_info(struct imxdi_dev *imxdi,  u32 dsr)  in di_report_tamper_info()  argument
191 	if (dsr & DSR_VTD)  in di_report_tamper_info()
195 	if (dsr & DSR_CTD)  in di_report_tamper_info()
199 	if (dsr & DSR_TTD)  in di_report_tamper_info()
203 	if (dsr & DSR_SAD)  in di_report_tamper_info()
208 	if (dsr & DSR_EBD)  in di_report_tamper_info()
212 	if (dsr & DSR_ETAD)  in di_report_tamper_info()
216 	if (dsr & DSR_ETBD)  in di_report_tamper_info()
220 	if (dsr & DSR_WTD)  in di_report_tamper_info()
224 	if (dsr & DSR_MCO)  in di_report_tamper_info()
229 	if (dsr & DSR_TCO)  in di_report_tamper_info()
241 static int di_handle_failure_state(struct imxdi_dev *imxdi, u32 dsr)  in di_handle_failure_state()  argument
245 	dev_dbg(&imxdi->pdev->dev, "DSR register reports: %08X\n", dsr);  in di_handle_failure_state()
248 	di_report_tamper_info(imxdi, dsr);  in di_handle_failure_state()
266 static int di_handle_valid_state(struct imxdi_dev *imxdi, u32 dsr)  in di_handle_valid_state()  argument
273 	if (dsr & DSR_CAF)  in di_handle_valid_state()
274 		di_write_busy_wait(imxdi, DSR_CAF, DSR);  in di_handle_valid_state()
279 static int di_handle_invalid_state(struct imxdi_dev *imxdi, u32 dsr)  in di_handle_invalid_state()  argument
314 	 *   - its overflow flag is set (TCO in DSR)  in di_handle_invalid_state()
316 	 *   - NVF is set in DSR  in di_handle_invalid_state()
324 	di_write_busy_wait(imxdi, DSR_NVF, DSR);  in di_handle_invalid_state()
326 	di_write_busy_wait(imxdi, DSR_TCO, DSR);  in di_handle_invalid_state()
333 	return di_handle_valid_state(imxdi, __raw_readl(imxdi->ioaddr + DSR));  in di_handle_invalid_state()
336 static int di_handle_invalid_and_failure_state(struct imxdi_dev *imxdi, u32 dsr)  in di_handle_invalid_and_failure_state()  argument
345 	if (dsr & (DSR_WTD | DSR_ETBD | DSR_ETAD | DSR_EBD | DSR_SAD |  in di_handle_invalid_and_failure_state()
374 	di_write_busy_wait(imxdi, dsr & (DSR_WTD | DSR_ETBD | DSR_ETAD |  in di_handle_invalid_and_failure_state()
376 			DSR_MCO | DSR_TCO), DSR);  in di_handle_invalid_and_failure_state()
378 	dsr = readl(imxdi->ioaddr + DSR);  in di_handle_invalid_and_failure_state()
379 	if ((dsr & ~(DSR_NVF | DSR_SVF | DSR_WBF | DSR_WNF |  in di_handle_invalid_and_failure_state()
382 			 "There are still some sources of pain in DSR: %08x!\n",  in di_handle_invalid_and_failure_state()
383 			 dsr & ~(DSR_NVF | DSR_SVF | DSR_WBF | DSR_WNF |  in di_handle_invalid_and_failure_state()
390 	di_write_busy_wait(imxdi, DSR_SVF, DSR);  in di_handle_invalid_and_failure_state()
393 	dsr = readl(imxdi->ioaddr + DSR);  in di_handle_invalid_and_failure_state()
394 	if (dsr & DSR_SVF) {  in di_handle_invalid_and_failure_state()
406 	return di_handle_invalid_state(imxdi, dsr);  in di_handle_invalid_and_failure_state()
412 	u32 dsr;  in di_handle_state()  local
414 	dsr = readl(imxdi->ioaddr + DSR);  in di_handle_state()
416 	switch (dsr & (DSR_NVF | DSR_SVF)) {  in di_handle_state()
419 		rc = di_handle_invalid_state(imxdi, dsr);  in di_handle_state()
423 		rc = di_handle_failure_state(imxdi, dsr);  in di_handle_state()
428 		rc = di_handle_invalid_and_failure_state(imxdi, dsr);  in di_handle_state()
432 		rc = di_handle_valid_state(imxdi, dsr);  in di_handle_state()
478 	writel(DSR_WEF, imxdi->ioaddr + DSR);  in clear_write_error()
482 		if ((readl(imxdi->ioaddr + DSR) & DSR_WEF) == 0)  in clear_write_error()
507 	imxdi->dsr = 0;  in di_write_wait()
514 			imxdi->dsr & (DSR_WCF | DSR_WEF), msecs_to_jiffies(1));  in di_write_wait()
525 	if (imxdi->dsr & DSR_WEF) {  in di_write_wait()
557 	u32 dcr, dsr;  in dryice_rtc_set_time()  local
561 	dsr = readl(imxdi->ioaddr + DSR);  in dryice_rtc_set_time()
563 	if (!(dcr & DCR_TCE) || (dsr & DSR_SVF)) {  in dryice_rtc_set_time()
569 		if ((dcr & DCR_TCSL) || (dsr & DSR_SVF)) {  in dryice_rtc_set_time()
616 	/* don't allow the DSR read to mess up DSR_WCF */  in dryice_rtc_read_alarm()
620 	alarm->pending = (readl(imxdi->ioaddr + DSR) & DSR_CAF) != 0;  in dryice_rtc_read_alarm()
662 	u32 dsr, dier;  in dryice_irq()  local
666 	dsr = readl(imxdi->ioaddr + DSR);  in dryice_irq()
670 		if (dsr & DSR_SVF) {  in dryice_irq()
681 			di_report_tamper_info(imxdi, dsr);  in dryice_irq()
694 		/* DSR_WCF clears itself on DSR read */  in dryice_irq()
695 		if (dsr & (DSR_WCF | DSR_WEF)) {  in dryice_irq()
699 			/* save the dsr value for the wait queue */  in dryice_irq()
700 			imxdi->dsr |= dsr;  in dryice_irq()
709 		/* DSR_WCF clears itself on DSR read */  in dryice_irq()
710 		if (dsr & DSR_CAF) {  in dryice_irq()
732 	di_write_wait(imxdi, DSR_CAF, DSR);  in dryice_work()