Lines Matching +full:0 +full:x14000

15 #define MT8183_SW_RSTN			0x0
16 #define MT8183_SW_RSTN_BIT		BIT(0)
17 #define MT8183_SCP_TO_HOST		0x1C
18 #define MT8183_SCP_IPC_INT_BIT		BIT(0)
20 #define MT8183_HOST_TO_SCP		0x28
21 #define MT8183_HOST_IPC_INT_BIT		BIT(0)
22 #define MT8183_WDT_CFG			0x84
23 #define MT8183_SCP_CLK_SW_SEL		0x4000
24 #define MT8183_SCP_CLK_DIV_SEL		0x4024
25 #define MT8183_SCP_SRAM_PDN		0x402C
26 #define MT8183_SCP_L1_SRAM_PD		0x4080
27 #define MT8183_SCP_TCM_TAIL_SRAM_PD	0x4094
29 #define MT8183_SCP_CACHE_SEL(x)		(0x14000 + (x) * 0x3000)
30 #define MT8183_SCP_CACHE_CON		MT8183_SCP_CACHE_SEL(0)
35 #define MT8192_L2TCM_SRAM_PD_0		0x210C0
36 #define MT8192_L2TCM_SRAM_PD_1		0x210C4
37 #define MT8192_L2TCM_SRAM_PD_2		0x210C8
38 #define MT8192_L1TCM_SRAM_PDN		0x2102C
39 #define MT8192_CPU0_SRAM_PD		0x21080
41 #define MT8192_SCP2APMCU_IPC_SET	0x24080
42 #define MT8192_SCP2APMCU_IPC_CLR	0x24084
43 #define MT8192_SCP_IPC_INT_BIT		BIT(0)
44 #define MT8192_SCP2SPM_IPC_CLR		0x24094
45 #define MT8192_GIPC_IN_SET		0x24098
46 #define MT8192_HOST_IPC_INT_BIT		BIT(0)
48 #define MT8192_CORE0_SW_RSTN_CLR	0x30000
49 #define MT8192_CORE0_SW_RSTN_SET	0x30004
50 #define MT8192_CORE0_WDT_CFG		0x30034