Lines Matching +full:tegra20 +full:- +full:pwm
1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * drivers/pwm/pwm-tegra.c
5 * Tegra pulse-width-modulation controller driver
7 * Copyright (c) 2010-2020, NVIDIA Corporation.
8 * Based on arch/arm/plat-mxc/pwm.c by Sascha Hauer <s.hauer@pengutronix.de>
11 * 1. 13-bit: Frequency division (SCALE)
12 * 2. 8-bit : Pulse division (DUTY)
13 * 3. 1-bit : Enable bit
15 * The PWM clock frequency is divided by 256 before subdividing it based
17 * frequency for PWM output. The maximum output frequency that can be
21 * This 1.6 MHz frequency can further be divided using SCALE value in PWM.
23 * PWM pulse width: 8 bits are usable [23:16] for varying pulse width.
28 * - When PWM is disabled, the output is driven to inactive.
29 * - It does not allow the current PWM period to complete and
32 * - If the register is reconfigured while PWM is running,
35 * - If the user input duty is beyond acceptible limits,
36 * -EINVAL is returned.
45 #include <linux/pwm.h>
86 return readl(chip->regs + (num << 4)); in pwm_readl()
92 writel(val, chip->regs + (num << 4)); in pwm_writel()
95 static int tegra_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, in tegra_pwm_config() argument
117 if (period_ns < pc->min_period_ns) in tegra_pwm_config()
118 return -EINVAL; in tegra_pwm_config()
122 * cycles at the PWM clock rate will take period_ns nanoseconds. in tegra_pwm_config()
124 * num_channels: If single instance of PWM controller has multiple in tegra_pwm_config()
129 * If every PWM controller instance has one channel respectively, i.e. in tegra_pwm_config()
133 if (pc->soc->num_channels == 1) { in tegra_pwm_config()
142 * source clock rate as required_clk_rate, PWM controller will in tegra_pwm_config()
148 err = clk_set_rate(pc->clk, required_clk_rate); in tegra_pwm_config()
150 return -EINVAL; in tegra_pwm_config()
153 pc->clk_rate = clk_get_rate(pc->clk); in tegra_pwm_config()
156 rate = pc->clk_rate >> PWM_DUTY_WIDTH; in tegra_pwm_config()
163 * Since the actual PWM divider is the register's frequency divider in tegra_pwm_config()
168 rate--; in tegra_pwm_config()
175 return -EINVAL; in tegra_pwm_config()
180 * If the PWM channel is disabled, make sure to turn on the clock in tegra_pwm_config()
183 if (!pwm_is_enabled(pwm)) { in tegra_pwm_config()
184 err = clk_prepare_enable(pc->clk); in tegra_pwm_config()
190 pwm_writel(pc, pwm->hwpwm, val); in tegra_pwm_config()
193 * If the PWM is not enabled, turn the clock off again to save power. in tegra_pwm_config()
195 if (!pwm_is_enabled(pwm)) in tegra_pwm_config()
196 clk_disable_unprepare(pc->clk); in tegra_pwm_config()
201 static int tegra_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) in tegra_pwm_enable() argument
207 rc = clk_prepare_enable(pc->clk); in tegra_pwm_enable()
211 val = pwm_readl(pc, pwm->hwpwm); in tegra_pwm_enable()
213 pwm_writel(pc, pwm->hwpwm, val); in tegra_pwm_enable()
218 static void tegra_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm) in tegra_pwm_disable() argument
223 val = pwm_readl(pc, pwm->hwpwm); in tegra_pwm_disable()
225 pwm_writel(pc, pwm->hwpwm, val); in tegra_pwm_disable()
227 clk_disable_unprepare(pc->clk); in tegra_pwm_disable()
239 struct tegra_pwm_chip *pwm; in tegra_pwm_probe() local
243 pwm = devm_kzalloc(&pdev->dev, sizeof(*pwm), GFP_KERNEL); in tegra_pwm_probe()
244 if (!pwm) in tegra_pwm_probe()
245 return -ENOMEM; in tegra_pwm_probe()
247 pwm->soc = of_device_get_match_data(&pdev->dev); in tegra_pwm_probe()
248 pwm->dev = &pdev->dev; in tegra_pwm_probe()
251 pwm->regs = devm_ioremap_resource(&pdev->dev, r); in tegra_pwm_probe()
252 if (IS_ERR(pwm->regs)) in tegra_pwm_probe()
253 return PTR_ERR(pwm->regs); in tegra_pwm_probe()
255 platform_set_drvdata(pdev, pwm); in tegra_pwm_probe()
257 pwm->clk = devm_clk_get(&pdev->dev, NULL); in tegra_pwm_probe()
258 if (IS_ERR(pwm->clk)) in tegra_pwm_probe()
259 return PTR_ERR(pwm->clk); in tegra_pwm_probe()
262 ret = clk_set_rate(pwm->clk, pwm->soc->max_frequency); in tegra_pwm_probe()
264 dev_err(&pdev->dev, "Failed to set max frequency: %d\n", ret); in tegra_pwm_probe()
271 * so that PWM period can be calculated more accurately. in tegra_pwm_probe()
273 pwm->clk_rate = clk_get_rate(pwm->clk); in tegra_pwm_probe()
275 /* Set minimum limit of PWM period for the IP */ in tegra_pwm_probe()
276 pwm->min_period_ns = in tegra_pwm_probe()
277 (NSEC_PER_SEC / (pwm->soc->max_frequency >> PWM_DUTY_WIDTH)) + 1; in tegra_pwm_probe()
279 pwm->rst = devm_reset_control_get_exclusive(&pdev->dev, "pwm"); in tegra_pwm_probe()
280 if (IS_ERR(pwm->rst)) { in tegra_pwm_probe()
281 ret = PTR_ERR(pwm->rst); in tegra_pwm_probe()
282 dev_err(&pdev->dev, "Reset control is not found: %d\n", ret); in tegra_pwm_probe()
286 reset_control_deassert(pwm->rst); in tegra_pwm_probe()
288 pwm->chip.dev = &pdev->dev; in tegra_pwm_probe()
289 pwm->chip.ops = &tegra_pwm_ops; in tegra_pwm_probe()
290 pwm->chip.base = -1; in tegra_pwm_probe()
291 pwm->chip.npwm = pwm->soc->num_channels; in tegra_pwm_probe()
293 ret = pwmchip_add(&pwm->chip); in tegra_pwm_probe()
295 dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret); in tegra_pwm_probe()
296 reset_control_assert(pwm->rst); in tegra_pwm_probe()
310 return -ENODEV; in tegra_pwm_remove()
312 err = clk_prepare_enable(pc->clk); in tegra_pwm_remove()
316 for (i = 0; i < pc->chip.npwm; i++) { in tegra_pwm_remove()
317 struct pwm_device *pwm = &pc->chip.pwms[i]; in tegra_pwm_remove() local
319 if (!pwm_is_enabled(pwm)) in tegra_pwm_remove()
320 if (clk_prepare_enable(pc->clk) < 0) in tegra_pwm_remove()
325 clk_disable_unprepare(pc->clk); in tegra_pwm_remove()
328 reset_control_assert(pc->rst); in tegra_pwm_remove()
329 clk_disable_unprepare(pc->clk); in tegra_pwm_remove()
331 return pwmchip_remove(&pc->chip); in tegra_pwm_remove()
362 { .compatible = "nvidia,tegra20-pwm", .data = &tegra20_pwm_soc },
363 { .compatible = "nvidia,tegra186-pwm", .data = &tegra186_pwm_soc },
364 { .compatible = "nvidia,tegra194-pwm", .data = &tegra194_pwm_soc },
375 .name = "tegra-pwm",
387 MODULE_DESCRIPTION("Tegra PWM controller driver");
388 MODULE_ALIAS("platform:tegra-pwm");