1 // SPDX-License-Identifier: GPL-2.0-only
3  * Intel Low Power Subsystem PWM controller driver
21 #include "pwm-lpss.h"
23 #define PWM				0x00000000  macro
29 /* Size of each PWM register space if multiple */
37 static inline u32 pwm_lpss_read(const struct pwm_device *pwm)  in pwm_lpss_read()  argument
39 	struct pwm_lpss_chip *lpwm = to_lpwm(pwm->chip);  in pwm_lpss_read()
41 	return readl(lpwm->regs + pwm->hwpwm * PWM_SIZE + PWM);  in pwm_lpss_read()
44 static inline void pwm_lpss_write(const struct pwm_device *pwm, u32 value)  in pwm_lpss_write()  argument
46 	struct pwm_lpss_chip *lpwm = to_lpwm(pwm->chip);  in pwm_lpss_write()
48 	writel(value, lpwm->regs + pwm->hwpwm * PWM_SIZE + PWM);  in pwm_lpss_write()
51 static int pwm_lpss_wait_for_update(struct pwm_device *pwm)  in pwm_lpss_wait_for_update()  argument
53 	struct pwm_lpss_chip *lpwm = to_lpwm(pwm->chip);  in pwm_lpss_wait_for_update()
54 	const void __iomem *addr = lpwm->regs + pwm->hwpwm * PWM_SIZE + PWM;  in pwm_lpss_wait_for_update()
60 	 * PWM Configuration register has SW_UPDATE bit that is set when a new  in pwm_lpss_wait_for_update()
65 	 * the bit enabled, PWM may freeze. That is, while one can still write  in pwm_lpss_wait_for_update()
72 		dev_err(pwm->chip->dev, "PWM_SW_UPDATE was not cleared\n");  in pwm_lpss_wait_for_update()
77 static inline int pwm_lpss_is_updating(struct pwm_device *pwm)  in pwm_lpss_is_updating()  argument
79 	return (pwm_lpss_read(pwm) & PWM_SW_UPDATE) ? -EBUSY : 0;  in pwm_lpss_is_updating()
82 static void pwm_lpss_prepare(struct pwm_lpss_chip *lpwm, struct pwm_device *pwm,  in pwm_lpss_prepare()  argument
86 	unsigned long c = lpwm->info->clk_rate, base_unit_range;  in pwm_lpss_prepare()
96 	base_unit_range = BIT(lpwm->info->base_unit_bits);  in pwm_lpss_prepare()
101 	base_unit = clamp_val(base_unit, 1, base_unit_range - 1);  in pwm_lpss_prepare()
105 	on_time_div = 255ULL - on_time_div;  in pwm_lpss_prepare()
107 	ctrl = pwm_lpss_read(pwm);  in pwm_lpss_prepare()
109 	ctrl &= ~((base_unit_range - 1) << PWM_BASE_UNIT_SHIFT);  in pwm_lpss_prepare()
113 	pwm_lpss_write(pwm, ctrl);  in pwm_lpss_prepare()
114 	pwm_lpss_write(pwm, ctrl | PWM_SW_UPDATE);  in pwm_lpss_prepare()
117 static inline void pwm_lpss_cond_enable(struct pwm_device *pwm, bool cond)  in pwm_lpss_cond_enable()  argument
120 		pwm_lpss_write(pwm, pwm_lpss_read(pwm) | PWM_ENABLE);  in pwm_lpss_cond_enable()
124 				   struct pwm_device *pwm,  in pwm_lpss_prepare_enable()  argument
129 	ret = pwm_lpss_is_updating(pwm);  in pwm_lpss_prepare_enable()
133 	pwm_lpss_prepare(lpwm, pwm, state->duty_cycle, state->period);  in pwm_lpss_prepare_enable()
134 	pwm_lpss_cond_enable(pwm, lpwm->info->bypass == false);  in pwm_lpss_prepare_enable()
135 	ret = pwm_lpss_wait_for_update(pwm);  in pwm_lpss_prepare_enable()
139 	pwm_lpss_cond_enable(pwm, lpwm->info->bypass == true);  in pwm_lpss_prepare_enable()
143 static int pwm_lpss_apply(struct pwm_chip *chip, struct pwm_device *pwm,  in pwm_lpss_apply()  argument
149 	if (state->enabled) {  in pwm_lpss_apply()
150 		if (!pwm_is_enabled(pwm)) {  in pwm_lpss_apply()
151 			pm_runtime_get_sync(chip->dev);  in pwm_lpss_apply()
152 			ret = pwm_lpss_prepare_enable(lpwm, pwm, state);  in pwm_lpss_apply()
154 				pm_runtime_put(chip->dev);  in pwm_lpss_apply()
156 			ret = pwm_lpss_prepare_enable(lpwm, pwm, state);  in pwm_lpss_apply()
158 	} else if (pwm_is_enabled(pwm)) {  in pwm_lpss_apply()
159 		pwm_lpss_write(pwm, pwm_lpss_read(pwm) & ~PWM_ENABLE);  in pwm_lpss_apply()
160 		pm_runtime_put(chip->dev);  in pwm_lpss_apply()
166 static void pwm_lpss_get_state(struct pwm_chip *chip, struct pwm_device *pwm,  in pwm_lpss_get_state()  argument
174 	pm_runtime_get_sync(chip->dev);  in pwm_lpss_get_state()
176 	base_unit_range = BIT(lpwm->info->base_unit_bits);  in pwm_lpss_get_state()
178 	ctrl = pwm_lpss_read(pwm);  in pwm_lpss_get_state()
179 	on_time_div = 255 - (ctrl & PWM_ON_TIME_DIV_MASK);  in pwm_lpss_get_state()
180 	base_unit = (ctrl >> PWM_BASE_UNIT_SHIFT) & (base_unit_range - 1);  in pwm_lpss_get_state()
182 	freq = base_unit * lpwm->info->clk_rate;  in pwm_lpss_get_state()
185 		state->period = NSEC_PER_SEC;  in pwm_lpss_get_state()
187 		state->period = NSEC_PER_SEC / (unsigned long)freq;  in pwm_lpss_get_state()
189 	on_time_div *= state->period;  in pwm_lpss_get_state()
191 	state->duty_cycle = on_time_div;  in pwm_lpss_get_state()
193 	state->polarity = PWM_POLARITY_NORMAL;  in pwm_lpss_get_state()
194 	state->enabled = !!(ctrl & PWM_ENABLE);  in pwm_lpss_get_state()
196 	pm_runtime_put(chip->dev);  in pwm_lpss_get_state()
213 	if (WARN_ON(info->npwm > MAX_PWMS))  in pwm_lpss_probe()
214 		return ERR_PTR(-ENODEV);  in pwm_lpss_probe()
218 		return ERR_PTR(-ENOMEM);  in pwm_lpss_probe()
220 	lpwm->regs = devm_ioremap_resource(dev, r);  in pwm_lpss_probe()
221 	if (IS_ERR(lpwm->regs))  in pwm_lpss_probe()
222 		return ERR_CAST(lpwm->regs);  in pwm_lpss_probe()
224 	lpwm->info = info;  in pwm_lpss_probe()
226 	c = lpwm->info->clk_rate;  in pwm_lpss_probe()
228 		return ERR_PTR(-EINVAL);  in pwm_lpss_probe()
230 	lpwm->chip.dev = dev;  in pwm_lpss_probe()
231 	lpwm->chip.ops = &pwm_lpss_ops;  in pwm_lpss_probe()
232 	lpwm->chip.base = -1;  in pwm_lpss_probe()
233 	lpwm->chip.npwm = info->npwm;  in pwm_lpss_probe()
235 	ret = pwmchip_add(&lpwm->chip);  in pwm_lpss_probe()
237 		dev_err(dev, "failed to add PWM chip: %d\n", ret);  in pwm_lpss_probe()
241 	for (i = 0; i < lpwm->info->npwm; i++) {  in pwm_lpss_probe()
242 		ctrl = pwm_lpss_read(&lpwm->chip.pwms[i]);  in pwm_lpss_probe()
255 	for (i = 0; i < lpwm->info->npwm; i++) {  in pwm_lpss_remove()
256 		if (pwm_is_enabled(&lpwm->chip.pwms[i]))  in pwm_lpss_remove()
257 			pm_runtime_put(lpwm->chip.dev);  in pwm_lpss_remove()
259 	return pwmchip_remove(&lpwm->chip);  in pwm_lpss_remove()
263 MODULE_DESCRIPTION("PWM driver for Intel LPSS");