1 // SPDX-License-Identifier: GPL-2.0-only
5  * Copyright (c) 2014-2015, Imagination Technologies
7  * Based on drivers/pwm/pwm-tegra.c, Copyright (c) 2010, NVIDIA Corporation
43  * PWM period is specified with a timebase register,
45  * specified in step periods, in the [0, $timebase] range.
46  * In other words, the timebase imposes the duty cycle
47  * resolution. Therefore, let's constraint the timebase to
49  * Imposing a minimum timebase, will impose a maximum PWM frequency.
83 	writel(val, chip->base + reg);  in img_pwm_writel()
89 	return readl(chip->base + reg);  in img_pwm_readl()
95 	u32 val, div, duty, timebase;  in img_pwm_config()  local
98 	unsigned int max_timebase = pwm_chip->data->max_timebase;  in img_pwm_config()
101 	if (period_ns < pwm_chip->min_period_ns ||  in img_pwm_config()
102 	    period_ns > pwm_chip->max_period_ns) {  in img_pwm_config()
103 		dev_err(chip->dev, "configured period not in range\n");  in img_pwm_config()
104 		return -ERANGE;  in img_pwm_config()
107 	input_clk_hz = clk_get_rate(pwm_chip->pwm_clk);  in img_pwm_config()
113 		timebase = DIV_ROUND_UP(mul, 1);  in img_pwm_config()
116 		timebase = DIV_ROUND_UP(mul, 8);  in img_pwm_config()
119 		timebase = DIV_ROUND_UP(mul, 64);  in img_pwm_config()
122 		timebase = DIV_ROUND_UP(mul, 512);  in img_pwm_config()
124 		dev_err(chip->dev,  in img_pwm_config()
125 			"failed to configure timebase steps/divider value\n");  in img_pwm_config()
126 		return -EINVAL;  in img_pwm_config()
129 	duty = DIV_ROUND_UP(timebase * duty_ns, period_ns);  in img_pwm_config()
131 	ret = pm_runtime_get_sync(chip->dev);  in img_pwm_config()
133 		pm_runtime_put_autosuspend(chip->dev);  in img_pwm_config()
138 	val &= ~(PWM_CTRL_CFG_DIV_MASK << PWM_CTRL_CFG_DIV_SHIFT(pwm->hwpwm));  in img_pwm_config()
140 		PWM_CTRL_CFG_DIV_SHIFT(pwm->hwpwm);  in img_pwm_config()
144 	      (timebase << PWM_CH_CFG_TMBASE_SHIFT);  in img_pwm_config()
145 	img_pwm_writel(pwm_chip, PWM_CH_CFG(pwm->hwpwm), val);  in img_pwm_config()
147 	pm_runtime_mark_last_busy(chip->dev);  in img_pwm_config()
148 	pm_runtime_put_autosuspend(chip->dev);  in img_pwm_config()
159 	ret = pm_runtime_get_sync(chip->dev);  in img_pwm_enable()
164 	val |= BIT(pwm->hwpwm);  in img_pwm_enable()
167 	regmap_update_bits(pwm_chip->periph_regs, PERIP_PWM_PDM_CONTROL,  in img_pwm_enable()
169 			   PERIP_PWM_PDM_CONTROL_CH_SHIFT(pwm->hwpwm), 0);  in img_pwm_enable()
180 	val &= ~BIT(pwm->hwpwm);  in img_pwm_disable()
183 	pm_runtime_mark_last_busy(chip->dev);  in img_pwm_disable()
184 	pm_runtime_put_autosuspend(chip->dev);  in img_pwm_disable()
200 		.compatible = "img,pistachio-pwm",
211 	clk_disable_unprepare(pwm_chip->pwm_clk);  in img_pwm_runtime_suspend()
212 	clk_disable_unprepare(pwm_chip->sys_clk);  in img_pwm_runtime_suspend()
222 	ret = clk_prepare_enable(pwm_chip->sys_clk);  in img_pwm_runtime_resume()
228 	ret = clk_prepare_enable(pwm_chip->pwm_clk);  in img_pwm_runtime_resume()
231 		clk_disable_unprepare(pwm_chip->sys_clk);  in img_pwm_runtime_resume()
247 	pwm = devm_kzalloc(&pdev->dev, sizeof(*pwm), GFP_KERNEL);  in img_pwm_probe()
249 		return -ENOMEM;  in img_pwm_probe()
251 	pwm->dev = &pdev->dev;  in img_pwm_probe()
254 	pwm->base = devm_ioremap_resource(&pdev->dev, res);  in img_pwm_probe()
255 	if (IS_ERR(pwm->base))  in img_pwm_probe()
256 		return PTR_ERR(pwm->base);  in img_pwm_probe()
258 	of_dev_id = of_match_device(img_pwm_of_match, &pdev->dev);  in img_pwm_probe()
260 		return -ENODEV;  in img_pwm_probe()
261 	pwm->data = of_dev_id->data;  in img_pwm_probe()
263 	pwm->periph_regs = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,  in img_pwm_probe()
264 							   "img,cr-periph");  in img_pwm_probe()
265 	if (IS_ERR(pwm->periph_regs))  in img_pwm_probe()
266 		return PTR_ERR(pwm->periph_regs);  in img_pwm_probe()
268 	pwm->sys_clk = devm_clk_get(&pdev->dev, "sys");  in img_pwm_probe()
269 	if (IS_ERR(pwm->sys_clk)) {  in img_pwm_probe()
270 		dev_err(&pdev->dev, "failed to get system clock\n");  in img_pwm_probe()
271 		return PTR_ERR(pwm->sys_clk);  in img_pwm_probe()
274 	pwm->pwm_clk = devm_clk_get(&pdev->dev, "pwm");  in img_pwm_probe()
275 	if (IS_ERR(pwm->pwm_clk)) {  in img_pwm_probe()
276 		dev_err(&pdev->dev, "failed to get pwm clock\n");  in img_pwm_probe()
277 		return PTR_ERR(pwm->pwm_clk);  in img_pwm_probe()
282 	pm_runtime_set_autosuspend_delay(&pdev->dev, IMG_PWM_PM_TIMEOUT);  in img_pwm_probe()
283 	pm_runtime_use_autosuspend(&pdev->dev);  in img_pwm_probe()
284 	pm_runtime_enable(&pdev->dev);  in img_pwm_probe()
285 	if (!pm_runtime_enabled(&pdev->dev)) {  in img_pwm_probe()
286 		ret = img_pwm_runtime_resume(&pdev->dev);  in img_pwm_probe()
291 	clk_rate = clk_get_rate(pwm->pwm_clk);  in img_pwm_probe()
293 		dev_err(&pdev->dev, "pwm clock has no frequency\n");  in img_pwm_probe()
294 		ret = -EINVAL;  in img_pwm_probe()
299 	val = (u64)NSEC_PER_SEC * 512 * pwm->data->max_timebase;  in img_pwm_probe()
301 	pwm->max_period_ns = val;  in img_pwm_probe()
305 	pwm->min_period_ns = val;  in img_pwm_probe()
307 	pwm->chip.dev = &pdev->dev;  in img_pwm_probe()
308 	pwm->chip.ops = &img_pwm_ops;  in img_pwm_probe()
309 	pwm->chip.base = -1;  in img_pwm_probe()
310 	pwm->chip.npwm = IMG_PWM_NPWM;  in img_pwm_probe()
312 	ret = pwmchip_add(&pwm->chip);  in img_pwm_probe()
314 		dev_err(&pdev->dev, "pwmchip_add failed: %d\n", ret);  in img_pwm_probe()
321 	if (!pm_runtime_enabled(&pdev->dev))  in img_pwm_probe()
322 		img_pwm_runtime_suspend(&pdev->dev);  in img_pwm_probe()
324 	pm_runtime_disable(&pdev->dev);  in img_pwm_probe()
325 	pm_runtime_dont_use_autosuspend(&pdev->dev);  in img_pwm_probe()
336 	ret = pm_runtime_get_sync(&pdev->dev);  in img_pwm_remove()
338 		pm_runtime_put(&pdev->dev);  in img_pwm_remove()
342 	for (i = 0; i < pwm_chip->chip.npwm; i++) {  in img_pwm_remove()
348 	pm_runtime_put(&pdev->dev);  in img_pwm_remove()
349 	pm_runtime_disable(&pdev->dev);  in img_pwm_remove()
350 	if (!pm_runtime_status_suspended(&pdev->dev))  in img_pwm_remove()
351 		img_pwm_runtime_suspend(&pdev->dev);  in img_pwm_remove()
353 	return pwmchip_remove(&pwm_chip->chip);  in img_pwm_remove()
368 	for (i = 0; i < pwm_chip->chip.npwm; i++)  in img_pwm_suspend()
369 		pwm_chip->suspend_ch_cfg[i] = img_pwm_readl(pwm_chip,  in img_pwm_suspend()
372 	pwm_chip->suspend_ctrl_cfg = img_pwm_readl(pwm_chip, PWM_CTRL_CFG);  in img_pwm_suspend()
389 	for (i = 0; i < pwm_chip->chip.npwm; i++)  in img_pwm_resume()
391 			       pwm_chip->suspend_ch_cfg[i]);  in img_pwm_resume()
393 	img_pwm_writel(pwm_chip, PWM_CTRL_CFG, pwm_chip->suspend_ctrl_cfg);  in img_pwm_resume()
395 	for (i = 0; i < pwm_chip->chip.npwm; i++)  in img_pwm_resume()
396 		if (pwm_chip->suspend_ctrl_cfg & BIT(i))  in img_pwm_resume()
397 			regmap_update_bits(pwm_chip->periph_regs,  in img_pwm_resume()
419 		.name = "img-pwm",