Lines Matching +full:soc +full:- +full:s
1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (c) 2011-2012, NVIDIA CORPORATION. All rights reserved.
10 * Copyright (C) 2009-2011 ST-Ericsson AB
25 #include "../pinctrl-utils.h"
26 #include "pinctrl-tegra.h"
30 return readl(pmx->regs[bank] + reg); in pmx_readl()
35 writel_relaxed(val, pmx->regs[bank] + reg); in pmx_writel()
44 return pmx->soc->ngroups; in tegra_pinctrl_get_groups_count()
52 return pmx->soc->groups[group].name; in tegra_pinctrl_get_group_name()
62 *pins = pmx->soc->groups[group].pins; in tegra_pinctrl_get_group_pins()
63 *num_pins = pmx->soc->groups[group].npins; in tegra_pinctrl_get_group_pins()
70 struct seq_file *s, in tegra_pinctrl_pin_dbg_show() argument
73 seq_printf(s, " %s", dev_name(pctldev->dev)); in tegra_pinctrl_pin_dbg_show()
83 {"nvidia,enable-input", TEGRA_PINCONF_PARAM_ENABLE_INPUT},
84 {"nvidia,open-drain", TEGRA_PINCONF_PARAM_OPEN_DRAIN},
86 {"nvidia,io-reset", TEGRA_PINCONF_PARAM_IORESET},
87 {"nvidia,rcv-sel", TEGRA_PINCONF_PARAM_RCV_SEL},
88 {"nvidia,io-hv", TEGRA_PINCONF_PARAM_RCV_SEL},
89 {"nvidia,high-speed-mode", TEGRA_PINCONF_PARAM_HIGH_SPEED_MODE},
91 {"nvidia,low-power-mode", TEGRA_PINCONF_PARAM_LOW_POWER_MODE},
92 {"nvidia,pull-down-strength", TEGRA_PINCONF_PARAM_DRIVE_DOWN_STRENGTH},
93 {"nvidia,pull-up-strength", TEGRA_PINCONF_PARAM_DRIVE_UP_STRENGTH},
94 {"nvidia,slew-rate-falling", TEGRA_PINCONF_PARAM_SLEW_RATE_FALLING},
95 {"nvidia,slew-rate-rising", TEGRA_PINCONF_PARAM_SLEW_RATE_RISING},
96 {"nvidia,drive-type", TEGRA_PINCONF_PARAM_DRIVE_TYPE},
105 struct device *dev = pctldev->dev; in tegra_pinctrl_dt_subnode_to_map()
118 /* EINVAL=missing, which is fine since it's optional */ in tegra_pinctrl_dt_subnode_to_map()
119 if (ret != -EINVAL) in tegra_pinctrl_dt_subnode_to_map()
133 /* EINVAL=missing, which is fine since it's optional */ in tegra_pinctrl_dt_subnode_to_map()
134 } else if (ret != -EINVAL) { in tegra_pinctrl_dt_subnode_to_map()
135 dev_err(dev, "could not parse property %s\n", in tegra_pinctrl_dt_subnode_to_map()
225 return pmx->soc->nfunctions; in tegra_pinctrl_get_funcs_count()
233 return pmx->soc->functions[function].name; in tegra_pinctrl_get_func_name()
243 *groups = pmx->soc->functions[function].groups; in tegra_pinctrl_get_func_groups()
244 *num_groups = pmx->soc->functions[function].ngroups; in tegra_pinctrl_get_func_groups()
258 g = &pmx->soc->groups[group]; in tegra_pinctrl_set_mux()
260 if (WARN_ON(g->mux_reg < 0)) in tegra_pinctrl_set_mux()
261 return -EINVAL; in tegra_pinctrl_set_mux()
263 for (i = 0; i < ARRAY_SIZE(g->funcs); i++) { in tegra_pinctrl_set_mux()
264 if (g->funcs[i] == function) in tegra_pinctrl_set_mux()
267 if (WARN_ON(i == ARRAY_SIZE(g->funcs))) in tegra_pinctrl_set_mux()
268 return -EINVAL; in tegra_pinctrl_set_mux()
270 val = pmx_readl(pmx, g->mux_bank, g->mux_reg); in tegra_pinctrl_set_mux()
271 val &= ~(0x3 << g->mux_bit); in tegra_pinctrl_set_mux()
272 val |= i << g->mux_bit; in tegra_pinctrl_set_mux()
273 pmx_writel(pmx, val, g->mux_bank, g->mux_reg); in tegra_pinctrl_set_mux()
286 if (!pmx->soc->sfsel_in_mux) in tegra_pinctrl_gpio_request_enable()
289 group = &pmx->soc->groups[offset]; in tegra_pinctrl_gpio_request_enable()
291 if (group->mux_reg < 0 || group->sfsel_bit < 0) in tegra_pinctrl_gpio_request_enable()
292 return -EINVAL; in tegra_pinctrl_gpio_request_enable()
294 value = pmx_readl(pmx, group->mux_bank, group->mux_reg); in tegra_pinctrl_gpio_request_enable()
295 value &= ~BIT(group->sfsel_bit); in tegra_pinctrl_gpio_request_enable()
296 pmx_writel(pmx, value, group->mux_bank, group->mux_reg); in tegra_pinctrl_gpio_request_enable()
309 if (!pmx->soc->sfsel_in_mux) in tegra_pinctrl_gpio_disable_free()
312 group = &pmx->soc->groups[offset]; in tegra_pinctrl_gpio_disable_free()
314 if (group->mux_reg < 0 || group->sfsel_bit < 0) in tegra_pinctrl_gpio_disable_free()
317 value = pmx_readl(pmx, group->mux_bank, group->mux_reg); in tegra_pinctrl_gpio_disable_free()
318 value |= BIT(group->sfsel_bit); in tegra_pinctrl_gpio_disable_free()
319 pmx_writel(pmx, value, group->mux_bank, group->mux_reg); in tegra_pinctrl_gpio_disable_free()
339 *bank = g->pupd_bank; in tegra_pinconf_reg()
340 *reg = g->pupd_reg; in tegra_pinconf_reg()
341 *bit = g->pupd_bit; in tegra_pinconf_reg()
345 *bank = g->tri_bank; in tegra_pinconf_reg()
346 *reg = g->tri_reg; in tegra_pinconf_reg()
347 *bit = g->tri_bit; in tegra_pinconf_reg()
351 *bank = g->mux_bank; in tegra_pinconf_reg()
352 *reg = g->mux_reg; in tegra_pinconf_reg()
353 *bit = g->einput_bit; in tegra_pinconf_reg()
357 *bank = g->mux_bank; in tegra_pinconf_reg()
358 *reg = g->mux_reg; in tegra_pinconf_reg()
359 *bit = g->odrain_bit; in tegra_pinconf_reg()
363 *bank = g->mux_bank; in tegra_pinconf_reg()
364 *reg = g->mux_reg; in tegra_pinconf_reg()
365 *bit = g->lock_bit; in tegra_pinconf_reg()
369 *bank = g->mux_bank; in tegra_pinconf_reg()
370 *reg = g->mux_reg; in tegra_pinconf_reg()
371 *bit = g->ioreset_bit; in tegra_pinconf_reg()
375 *bank = g->mux_bank; in tegra_pinconf_reg()
376 *reg = g->mux_reg; in tegra_pinconf_reg()
377 *bit = g->rcv_sel_bit; in tegra_pinconf_reg()
381 if (pmx->soc->hsm_in_mux) { in tegra_pinconf_reg()
382 *bank = g->mux_bank; in tegra_pinconf_reg()
383 *reg = g->mux_reg; in tegra_pinconf_reg()
385 *bank = g->drv_bank; in tegra_pinconf_reg()
386 *reg = g->drv_reg; in tegra_pinconf_reg()
388 *bit = g->hsm_bit; in tegra_pinconf_reg()
392 if (pmx->soc->schmitt_in_mux) { in tegra_pinconf_reg()
393 *bank = g->mux_bank; in tegra_pinconf_reg()
394 *reg = g->mux_reg; in tegra_pinconf_reg()
396 *bank = g->drv_bank; in tegra_pinconf_reg()
397 *reg = g->drv_reg; in tegra_pinconf_reg()
399 *bit = g->schmitt_bit; in tegra_pinconf_reg()
403 *bank = g->drv_bank; in tegra_pinconf_reg()
404 *reg = g->drv_reg; in tegra_pinconf_reg()
405 *bit = g->lpmd_bit; in tegra_pinconf_reg()
409 *bank = g->drv_bank; in tegra_pinconf_reg()
410 *reg = g->drv_reg; in tegra_pinconf_reg()
411 *bit = g->drvdn_bit; in tegra_pinconf_reg()
412 *width = g->drvdn_width; in tegra_pinconf_reg()
415 *bank = g->drv_bank; in tegra_pinconf_reg()
416 *reg = g->drv_reg; in tegra_pinconf_reg()
417 *bit = g->drvup_bit; in tegra_pinconf_reg()
418 *width = g->drvup_width; in tegra_pinconf_reg()
421 *bank = g->drv_bank; in tegra_pinconf_reg()
422 *reg = g->drv_reg; in tegra_pinconf_reg()
423 *bit = g->slwf_bit; in tegra_pinconf_reg()
424 *width = g->slwf_width; in tegra_pinconf_reg()
427 *bank = g->drv_bank; in tegra_pinconf_reg()
428 *reg = g->drv_reg; in tegra_pinconf_reg()
429 *bit = g->slwr_bit; in tegra_pinconf_reg()
430 *width = g->slwr_width; in tegra_pinconf_reg()
433 if (pmx->soc->drvtype_in_mux) { in tegra_pinconf_reg()
434 *bank = g->mux_bank; in tegra_pinconf_reg()
435 *reg = g->mux_reg; in tegra_pinconf_reg()
437 *bank = g->drv_bank; in tegra_pinconf_reg()
438 *reg = g->drv_reg; in tegra_pinconf_reg()
440 *bit = g->drvtype_bit; in tegra_pinconf_reg()
444 dev_err(pmx->dev, "Invalid config param %04x\n", param); in tegra_pinconf_reg()
445 return -ENOTSUPP; in tegra_pinconf_reg()
460 dev_err(pmx->dev, in tegra_pinconf_reg()
461 "Config param %04x (%s) not supported on group %s\n", in tegra_pinconf_reg()
462 param, prop, g->name); in tegra_pinconf_reg()
464 return -ENOTSUPP; in tegra_pinconf_reg()
473 dev_err(pctldev->dev, "pin_config_get op not supported\n"); in tegra_pinconf_get()
474 return -ENOTSUPP; in tegra_pinconf_get()
481 dev_err(pctldev->dev, "pin_config_set op not supported\n"); in tegra_pinconf_set()
482 return -ENOTSUPP; in tegra_pinconf_set()
497 g = &pmx->soc->groups[group]; in tegra_pinconf_group_get()
505 mask = (1 << width) - 1; in tegra_pinconf_group_get()
526 g = &pmx->soc->groups[group]; in tegra_pinconf_group_set()
542 dev_err(pctldev->dev, "LOCK bit cannot be cleared\n"); in tegra_pinconf_group_set()
543 return -EINVAL; in tegra_pinconf_group_set()
547 /* Special-case Boolean values; allow any non-zero as true */ in tegra_pinconf_group_set()
551 /* Range-check user-supplied value */ in tegra_pinconf_group_set()
552 mask = (1 << width) - 1; in tegra_pinconf_group_set()
554 dev_err(pctldev->dev, in tegra_pinconf_group_set()
557 return -EINVAL; in tegra_pinconf_group_set()
571 struct seq_file *s, unsigned offset) in tegra_pinconf_dbg_show() argument
575 static const char *strip_prefix(const char *s) in strip_prefix() argument
577 const char *comma = strchr(s, ','); in strip_prefix()
579 return s; in strip_prefix()
585 struct seq_file *s, unsigned group) in tegra_pinconf_group_dbg_show() argument
594 g = &pmx->soc->groups[group]; in tegra_pinconf_group_dbg_show()
604 val &= (1 << width) - 1; in tegra_pinconf_group_dbg_show()
606 seq_printf(s, "\n\t%s=%u", in tegra_pinconf_group_dbg_show()
612 struct seq_file *s, in tegra_pinconf_config_dbg_show() argument
627 seq_printf(s, "%s=%d", strip_prefix(pname), arg); in tegra_pinconf_config_dbg_show()
662 for (i = 0; i < pmx->soc->ngroups; ++i) { in tegra_pinctrl_clear_parked_bits()
663 g = &pmx->soc->groups[i]; in tegra_pinctrl_clear_parked_bits()
664 if (g->parked_bitmask > 0) { in tegra_pinctrl_clear_parked_bits()
667 if (g->mux_reg != -1) { in tegra_pinctrl_clear_parked_bits()
668 bank = g->mux_bank; in tegra_pinctrl_clear_parked_bits()
669 reg = g->mux_reg; in tegra_pinctrl_clear_parked_bits()
671 bank = g->drv_bank; in tegra_pinctrl_clear_parked_bits()
672 reg = g->drv_reg; in tegra_pinctrl_clear_parked_bits()
676 val &= ~g->parked_bitmask; in tegra_pinctrl_clear_parked_bits()
696 u32 *backup_regs = pmx->backup_regs; in tegra_pinctrl_suspend()
701 for (i = 0; i < pmx->nbanks; i++) { in tegra_pinctrl_suspend()
703 regs = pmx->regs[i]; in tegra_pinctrl_suspend()
708 return pinctrl_force_sleep(pmx->pctl); in tegra_pinctrl_suspend()
714 u32 *backup_regs = pmx->backup_regs; in tegra_pinctrl_resume()
719 for (i = 0; i < pmx->nbanks; i++) { in tegra_pinctrl_resume()
721 regs = pmx->regs[i]; in tegra_pinctrl_resume()
727 readl_relaxed(pmx->regs[0]); in tegra_pinctrl_resume()
743 np = of_find_compatible_node(NULL, NULL, pmx->soc->gpio_compatible); in tegra_pinctrl_gpio_node_has_range()
747 has_prop = of_find_property(np, "gpio-ranges", NULL); in tegra_pinctrl_gpio_node_has_range()
764 pmx = devm_kzalloc(&pdev->dev, sizeof(*pmx), GFP_KERNEL); in tegra_pinctrl_probe()
766 return -ENOMEM; in tegra_pinctrl_probe()
768 pmx->dev = &pdev->dev; in tegra_pinctrl_probe()
769 pmx->soc = soc_data; in tegra_pinctrl_probe()
773 * This over-allocates slightly, since not all groups are mux groups. in tegra_pinctrl_probe()
775 pmx->group_pins = devm_kcalloc(&pdev->dev, in tegra_pinctrl_probe()
776 soc_data->ngroups * 4, sizeof(*pmx->group_pins), in tegra_pinctrl_probe()
778 if (!pmx->group_pins) in tegra_pinctrl_probe()
779 return -ENOMEM; in tegra_pinctrl_probe()
781 group_pins = pmx->group_pins; in tegra_pinctrl_probe()
782 for (fn = 0; fn < soc_data->nfunctions; fn++) { in tegra_pinctrl_probe()
783 struct tegra_function *func = &soc_data->functions[fn]; in tegra_pinctrl_probe()
785 func->groups = group_pins; in tegra_pinctrl_probe()
787 for (gn = 0; gn < soc_data->ngroups; gn++) { in tegra_pinctrl_probe()
788 const struct tegra_pingroup *g = &soc_data->groups[gn]; in tegra_pinctrl_probe()
790 if (g->mux_reg == -1) in tegra_pinctrl_probe()
794 if (g->funcs[gfn] == fn) in tegra_pinctrl_probe()
799 BUG_ON(group_pins - pmx->group_pins >= in tegra_pinctrl_probe()
800 soc_data->ngroups * 4); in tegra_pinctrl_probe()
801 *group_pins++ = g->name; in tegra_pinctrl_probe()
802 func->ngroups++; in tegra_pinctrl_probe()
806 tegra_pinctrl_gpio_range.npins = pmx->soc->ngpios; in tegra_pinctrl_probe()
807 tegra_pinctrl_desc.name = dev_name(&pdev->dev); in tegra_pinctrl_probe()
808 tegra_pinctrl_desc.pins = pmx->soc->pins; in tegra_pinctrl_probe()
809 tegra_pinctrl_desc.npins = pmx->soc->npins; in tegra_pinctrl_probe()
817 pmx->nbanks = i; in tegra_pinctrl_probe()
819 pmx->regs = devm_kcalloc(&pdev->dev, pmx->nbanks, sizeof(*pmx->regs), in tegra_pinctrl_probe()
821 if (!pmx->regs) in tegra_pinctrl_probe()
822 return -ENOMEM; in tegra_pinctrl_probe()
824 pmx->backup_regs = devm_kzalloc(&pdev->dev, backup_regs_size, in tegra_pinctrl_probe()
826 if (!pmx->backup_regs) in tegra_pinctrl_probe()
827 return -ENOMEM; in tegra_pinctrl_probe()
829 for (i = 0; i < pmx->nbanks; i++) { in tegra_pinctrl_probe()
830 pmx->regs[i] = devm_platform_ioremap_resource(pdev, i); in tegra_pinctrl_probe()
831 if (IS_ERR(pmx->regs[i])) in tegra_pinctrl_probe()
832 return PTR_ERR(pmx->regs[i]); in tegra_pinctrl_probe()
835 pmx->pctl = devm_pinctrl_register(&pdev->dev, &tegra_pinctrl_desc, pmx); in tegra_pinctrl_probe()
836 if (IS_ERR(pmx->pctl)) { in tegra_pinctrl_probe()
837 dev_err(&pdev->dev, "Couldn't register pinctrl driver\n"); in tegra_pinctrl_probe()
838 return PTR_ERR(pmx->pctl); in tegra_pinctrl_probe()
843 if (pmx->soc->ngpios > 0 && !tegra_pinctrl_gpio_node_has_range(pmx)) in tegra_pinctrl_probe()
844 pinctrl_add_gpio_range(pmx->pctl, &tegra_pinctrl_gpio_range); in tegra_pinctrl_probe()
848 dev_dbg(&pdev->dev, "Probed Tegra pinctrl driver\n"); in tegra_pinctrl_probe()