1 // SPDX-License-Identifier: GPL-2.0-or-later
10  * Copyright (c) 2011 - 2014 Cambridge Silicon Radio Limited, a CSR plc group
32 #include "pinctrl-sirf.h"
34 #define DRIVER_NAME "pinmux-sirf"
39 	spinlock_t lock;  member
45 	spinlock_t lock;  member
73 				struct seq_file *s, unsigned offset)  in sirfsoc_pin_dbg_show()  argument
106 		dev_err(spmx->dev, "No child nodes passed via DT\n");  in sirfsoc_dt_node_to_map()
107 		return -ENODEV;  in sirfsoc_dt_node_to_map()
112 		return -ENOMEM;  in sirfsoc_dt_node_to_map()
153 	const struct sirfsoc_muxmask *mask = mux->muxmask;  in sirfsoc_pinmux_endisable()
155 	for (i = 0; i < mux->muxmask_counts; i++) {  in sirfsoc_pinmux_endisable()
157 		muxval = readl(spmx->gpio_virtbase +  in sirfsoc_pinmux_endisable()
163 		writel(muxval, spmx->gpio_virtbase +  in sirfsoc_pinmux_endisable()
167 	if (mux->funcmask && enable) {  in sirfsoc_pinmux_endisable()
171 			readl(spmx->rsc_virtbase + mux->ctrlreg);  in sirfsoc_pinmux_endisable()
173 			(func_en_val & ~mux->funcmask) | (mux->funcval);  in sirfsoc_pinmux_endisable()
174 		writel(func_en_val, spmx->rsc_virtbase + mux->ctrlreg);  in sirfsoc_pinmux_endisable()
212 	struct pinctrl_gpio_range *range, unsigned offset)  in sirfsoc_pinmux_request_gpio()  argument
216 	int group = range->id;  in sirfsoc_pinmux_request_gpio()
222 	muxval = readl(spmx->gpio_virtbase +  in sirfsoc_pinmux_request_gpio()
224 	muxval = muxval | (1 << (offset - range->pin_base));  in sirfsoc_pinmux_request_gpio()
225 	writel(muxval, spmx->gpio_virtbase +  in sirfsoc_pinmux_request_gpio()
249 		{ .compatible = "sirf,prima2-rsc" },  in sirfsoc_rsc_of_iomap()
265 	if (gpiospec->args[0] > SIRFSOC_GPIO_NO_OF_BANKS * SIRFSOC_GPIO_BANK_SIZE)  in sirfsoc_gpio_of_xlate()
266 		return -EINVAL;  in sirfsoc_gpio_of_xlate()
269 		*flags = gpiospec->args[1];  in sirfsoc_gpio_of_xlate()
271 	return gpiospec->args[0];  in sirfsoc_gpio_of_xlate()
275 	{ .compatible = "sirf,prima2-pinctrl", .data = &prima2_pinctrl_data, },
276 	{ .compatible = "sirf,atlas6-pinctrl", .data = &atlas6_pinctrl_data, },
284 	struct device_node *np = pdev->dev.of_node;  in sirfsoc_pinmux_probe()
288 	spmx = devm_kzalloc(&pdev->dev, sizeof(*spmx), GFP_KERNEL);  in sirfsoc_pinmux_probe()
290 		return -ENOMEM;  in sirfsoc_pinmux_probe()
292 	spmx->dev = &pdev->dev;  in sirfsoc_pinmux_probe()
296 	spmx->gpio_virtbase = of_iomap(np, 0);  in sirfsoc_pinmux_probe()
297 	if (!spmx->gpio_virtbase) {  in sirfsoc_pinmux_probe()
298 		dev_err(&pdev->dev, "can't map gpio registers\n");  in sirfsoc_pinmux_probe()
299 		return -ENOMEM;  in sirfsoc_pinmux_probe()
302 	spmx->rsc_virtbase = sirfsoc_rsc_of_iomap();  in sirfsoc_pinmux_probe()
303 	if (!spmx->rsc_virtbase) {  in sirfsoc_pinmux_probe()
304 		ret = -ENOMEM;  in sirfsoc_pinmux_probe()
305 		dev_err(&pdev->dev, "can't map rsc registers\n");  in sirfsoc_pinmux_probe()
309 	pdata = of_match_node(pinmux_ids, np)->data;  in sirfsoc_pinmux_probe()
310 	sirfsoc_pin_groups = pdata->grps;  in sirfsoc_pinmux_probe()
311 	sirfsoc_pingrp_cnt = pdata->grps_cnt;  in sirfsoc_pinmux_probe()
312 	sirfsoc_pmx_functions = pdata->funcs;  in sirfsoc_pinmux_probe()
313 	sirfsoc_pmxfunc_cnt = pdata->funcs_cnt;  in sirfsoc_pinmux_probe()
314 	sirfsoc_pinmux_desc.pins = pdata->pads;  in sirfsoc_pinmux_probe()
315 	sirfsoc_pinmux_desc.npins = pdata->pads_cnt;  in sirfsoc_pinmux_probe()
319 	spmx->pmx = pinctrl_register(&sirfsoc_pinmux_desc, &pdev->dev, spmx);  in sirfsoc_pinmux_probe()
320 	if (IS_ERR(spmx->pmx)) {  in sirfsoc_pinmux_probe()
321 		dev_err(&pdev->dev, "could not register SIRFSOC pinmux driver\n");  in sirfsoc_pinmux_probe()
322 		ret = PTR_ERR(spmx->pmx);  in sirfsoc_pinmux_probe()
326 	dev_info(&pdev->dev, "initialized SIRFSOC pinmux driver\n");  in sirfsoc_pinmux_probe()
331 	iounmap(spmx->rsc_virtbase);  in sirfsoc_pinmux_probe()
333 	iounmap(spmx->gpio_virtbase);  in sirfsoc_pinmux_probe()
345 			spmx->gpio_regs[i][j] = readl(spmx->gpio_virtbase +  in sirfsoc_pinmux_suspend_noirq()
348 		spmx->ints_regs[i] = readl(spmx->gpio_virtbase +  in sirfsoc_pinmux_suspend_noirq()
350 		spmx->paden_regs[i] = readl(spmx->gpio_virtbase +  in sirfsoc_pinmux_suspend_noirq()
353 	spmx->dspen_regs = readl(spmx->gpio_virtbase + SIRFSOC_GPIO_DSP_EN0);  in sirfsoc_pinmux_suspend_noirq()
356 		spmx->rsc_regs[i] = readl(spmx->rsc_virtbase + 4 * i);  in sirfsoc_pinmux_suspend_noirq()
368 			writel(spmx->gpio_regs[i][j], spmx->gpio_virtbase +  in sirfsoc_pinmux_resume_noirq()
371 		writel(spmx->ints_regs[i], spmx->gpio_virtbase +  in sirfsoc_pinmux_resume_noirq()
373 		writel(spmx->paden_regs[i], spmx->gpio_virtbase +  in sirfsoc_pinmux_resume_noirq()
376 	writel(spmx->dspen_regs, spmx->gpio_virtbase + SIRFSOC_GPIO_DSP_EN0);  in sirfsoc_pinmux_resume_noirq()
379 		writel(spmx->rsc_regs[i], spmx->rsc_virtbase + 4 * i);  in sirfsoc_pinmux_resume_noirq()
410 sirfsoc_gpio_to_bank(struct sirfsoc_gpio_chip *sgpio, unsigned int offset)  in sirfsoc_gpio_to_bank()  argument
412 	return &sgpio->sgpio_bank[offset / SIRFSOC_GPIO_BANK_SIZE];  in sirfsoc_gpio_to_bank()
415 static inline int sirfsoc_gpio_to_bankoff(unsigned int offset)  in sirfsoc_gpio_to_bankoff()  argument
417 	return offset % SIRFSOC_GPIO_BANK_SIZE;  in sirfsoc_gpio_to_bankoff()
424 	struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, d->hwirq);  in sirfsoc_gpio_irq_ack()
425 	int idx = sirfsoc_gpio_to_bankoff(d->hwirq);  in sirfsoc_gpio_irq_ack()
426 	u32 val, offset;  in sirfsoc_gpio_irq_ack()  local
429 	offset = SIRFSOC_GPIO_CTRL(bank->id, idx);  in sirfsoc_gpio_irq_ack()
431 	spin_lock_irqsave(&sgpio->lock, flags);  in sirfsoc_gpio_irq_ack()
433 	val = readl(sgpio->chip.regs + offset);  in sirfsoc_gpio_irq_ack()
435 	writel(val, sgpio->chip.regs + offset);  in sirfsoc_gpio_irq_ack()
437 	spin_unlock_irqrestore(&sgpio->lock, flags);  in sirfsoc_gpio_irq_ack()
444 	u32 val, offset;  in __sirfsoc_gpio_irq_mask()  local
447 	offset = SIRFSOC_GPIO_CTRL(bank->id, idx);  in __sirfsoc_gpio_irq_mask()
449 	spin_lock_irqsave(&sgpio->lock, flags);  in __sirfsoc_gpio_irq_mask()
451 	val = readl(sgpio->chip.regs + offset);  in __sirfsoc_gpio_irq_mask()
454 	writel(val, sgpio->chip.regs + offset);  in __sirfsoc_gpio_irq_mask()
456 	spin_unlock_irqrestore(&sgpio->lock, flags);  in __sirfsoc_gpio_irq_mask()
463 	struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, d->hwirq);  in sirfsoc_gpio_irq_mask()
465 	__sirfsoc_gpio_irq_mask(sgpio, bank, d->hwirq % SIRFSOC_GPIO_BANK_SIZE);  in sirfsoc_gpio_irq_mask()
472 	struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, d->hwirq);  in sirfsoc_gpio_irq_unmask()
473 	int idx = sirfsoc_gpio_to_bankoff(d->hwirq);  in sirfsoc_gpio_irq_unmask()
474 	u32 val, offset;  in sirfsoc_gpio_irq_unmask()  local
477 	offset = SIRFSOC_GPIO_CTRL(bank->id, idx);  in sirfsoc_gpio_irq_unmask()
479 	spin_lock_irqsave(&sgpio->lock, flags);  in sirfsoc_gpio_irq_unmask()
481 	val = readl(sgpio->chip.regs + offset);  in sirfsoc_gpio_irq_unmask()
484 	writel(val, sgpio->chip.regs + offset);  in sirfsoc_gpio_irq_unmask()
486 	spin_unlock_irqrestore(&sgpio->lock, flags);  in sirfsoc_gpio_irq_unmask()
493 	struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, d->hwirq);  in sirfsoc_gpio_irq_type()
494 	int idx = sirfsoc_gpio_to_bankoff(d->hwirq);  in sirfsoc_gpio_irq_type()
495 	u32 val, offset;  in sirfsoc_gpio_irq_type()  local
498 	offset = SIRFSOC_GPIO_CTRL(bank->id, idx);  in sirfsoc_gpio_irq_type()
500 	spin_lock_irqsave(&sgpio->lock, flags);  in sirfsoc_gpio_irq_type()
502 	val = readl(sgpio->chip.regs + offset);  in sirfsoc_gpio_irq_type()
535 	writel(val, sgpio->chip.regs + offset);  in sirfsoc_gpio_irq_type()
537 	spin_unlock_irqrestore(&sgpio->lock, flags);  in sirfsoc_gpio_irq_type()
543 	.name = "sirf-gpio-irq",
562 		bank = &sgpio->sgpio_bank[i];  in sirfsoc_gpio_handle_irq()
563 		if (bank->parent_irq == irq)  in sirfsoc_gpio_handle_irq()
570 	status = readl(sgpio->chip.regs + SIRFSOC_GPIO_INT_STATUS(bank->id));  in sirfsoc_gpio_handle_irq()
574 			__func__, bank->id, status);  in sirfsoc_gpio_handle_irq()
580 		ctrl = readl(sgpio->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, idx));  in sirfsoc_gpio_handle_irq()
588 				__func__, bank->id, idx);  in sirfsoc_gpio_handle_irq()
589 			generic_handle_irq(irq_find_mapping(gc->irq.domain, idx +  in sirfsoc_gpio_handle_irq()
590 					bank->id * SIRFSOC_GPIO_BANK_SIZE));  in sirfsoc_gpio_handle_irq()
605 	val = readl(sgpio->chip.regs + ctrl_offset);  in sirfsoc_gpio_set_input()
607 	writel(val, sgpio->chip.regs + ctrl_offset);  in sirfsoc_gpio_set_input()
610 static int sirfsoc_gpio_request(struct gpio_chip *chip, unsigned offset)  in sirfsoc_gpio_request()  argument
613 	struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, offset);  in sirfsoc_gpio_request()
616 	if (pinctrl_gpio_request(chip->base + offset))  in sirfsoc_gpio_request()
617 		return -ENODEV;  in sirfsoc_gpio_request()
619 	spin_lock_irqsave(&bank->lock, flags);  in sirfsoc_gpio_request()
625 	sirfsoc_gpio_set_input(sgpio, SIRFSOC_GPIO_CTRL(bank->id, offset));  in sirfsoc_gpio_request()
626 	__sirfsoc_gpio_irq_mask(sgpio, bank, offset);  in sirfsoc_gpio_request()
628 	spin_unlock_irqrestore(&bank->lock, flags);  in sirfsoc_gpio_request()
633 static void sirfsoc_gpio_free(struct gpio_chip *chip, unsigned offset)  in sirfsoc_gpio_free()  argument
636 	struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, offset);  in sirfsoc_gpio_free()
639 	spin_lock_irqsave(&bank->lock, flags);  in sirfsoc_gpio_free()
641 	__sirfsoc_gpio_irq_mask(sgpio, bank, offset);  in sirfsoc_gpio_free()
642 	sirfsoc_gpio_set_input(sgpio, SIRFSOC_GPIO_CTRL(bank->id, offset));  in sirfsoc_gpio_free()
644 	spin_unlock_irqrestore(&bank->lock, flags);  in sirfsoc_gpio_free()
646 	pinctrl_gpio_free(chip->base + offset);  in sirfsoc_gpio_free()
655 	unsigned offset;  in sirfsoc_gpio_direction_input()  local
657 	offset = SIRFSOC_GPIO_CTRL(bank->id, idx);  in sirfsoc_gpio_direction_input()
659 	spin_lock_irqsave(&bank->lock, flags);  in sirfsoc_gpio_direction_input()
661 	sirfsoc_gpio_set_input(sgpio, offset);  in sirfsoc_gpio_direction_input()
663 	spin_unlock_irqrestore(&bank->lock, flags);  in sirfsoc_gpio_direction_input()
670 					   unsigned offset,  in sirfsoc_gpio_set_output()  argument
676 	spin_lock_irqsave(&bank->lock, flags);  in sirfsoc_gpio_set_output()
678 	out_ctrl = readl(sgpio->chip.regs + offset);  in sirfsoc_gpio_set_output()
686 	writel(out_ctrl, sgpio->chip.regs + offset);  in sirfsoc_gpio_set_output()
688 	spin_unlock_irqrestore(&bank->lock, flags);  in sirfsoc_gpio_set_output()
697 	u32 offset;  in sirfsoc_gpio_direction_output()  local
700 	offset = SIRFSOC_GPIO_CTRL(bank->id, idx);  in sirfsoc_gpio_direction_output()
702 	spin_lock_irqsave(&sgpio->lock, flags);  in sirfsoc_gpio_direction_output()
704 	sirfsoc_gpio_set_output(sgpio, bank, offset, value);  in sirfsoc_gpio_direction_output()
706 	spin_unlock_irqrestore(&sgpio->lock, flags);  in sirfsoc_gpio_direction_output()
711 static int sirfsoc_gpio_get_value(struct gpio_chip *chip, unsigned offset)  in sirfsoc_gpio_get_value()  argument
714 	struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, offset);  in sirfsoc_gpio_get_value()
718 	spin_lock_irqsave(&bank->lock, flags);  in sirfsoc_gpio_get_value()
720 	val = readl(sgpio->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, offset));  in sirfsoc_gpio_get_value()
722 	spin_unlock_irqrestore(&bank->lock, flags);  in sirfsoc_gpio_get_value()
727 static void sirfsoc_gpio_set_value(struct gpio_chip *chip, unsigned offset,  in sirfsoc_gpio_set_value()  argument
731 	struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, offset);  in sirfsoc_gpio_set_value()
735 	spin_lock_irqsave(&bank->lock, flags);  in sirfsoc_gpio_set_value()
737 	ctrl = readl(sgpio->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, offset));  in sirfsoc_gpio_set_value()
742 	writel(ctrl, sgpio->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, offset));  in sirfsoc_gpio_set_value()
744 	spin_unlock_irqrestore(&bank->lock, flags);  in sirfsoc_gpio_set_value()
755 			u32 offset = SIRFSOC_GPIO_CTRL(i, n);  in sirfsoc_gpio_set_pullup()  local
756 			u32 val = readl(sgpio->chip.regs + offset);  in sirfsoc_gpio_set_pullup()
759 			writel(val, sgpio->chip.regs + offset);  in sirfsoc_gpio_set_pullup()
772 			u32 offset = SIRFSOC_GPIO_CTRL(i, n);  in sirfsoc_gpio_set_pulldown()  local
773 			u32 val = readl(sgpio->chip.regs + offset);  in sirfsoc_gpio_set_pulldown()
776 			writel(val, sgpio->chip.regs + offset);  in sirfsoc_gpio_set_pulldown()
794 		return -ENODEV;  in sirfsoc_gpio_probe()
796 	sgpio = devm_kzalloc(&pdev->dev, sizeof(*sgpio), GFP_KERNEL);  in sirfsoc_gpio_probe()
798 		err = -ENOMEM;  in sirfsoc_gpio_probe()
801 	spin_lock_init(&sgpio->lock);  in sirfsoc_gpio_probe()
805 		err = -ENOMEM;  in sirfsoc_gpio_probe()
809 	sgpio->chip.gc.request = sirfsoc_gpio_request;  in sirfsoc_gpio_probe()
810 	sgpio->chip.gc.free = sirfsoc_gpio_free;  in sirfsoc_gpio_probe()
811 	sgpio->chip.gc.direction_input = sirfsoc_gpio_direction_input;  in sirfsoc_gpio_probe()
812 	sgpio->chip.gc.get = sirfsoc_gpio_get_value;  in sirfsoc_gpio_probe()
813 	sgpio->chip.gc.direction_output = sirfsoc_gpio_direction_output;  in sirfsoc_gpio_probe()
814 	sgpio->chip.gc.set = sirfsoc_gpio_set_value;  in sirfsoc_gpio_probe()
815 	sgpio->chip.gc.base = 0;  in sirfsoc_gpio_probe()
816 	sgpio->chip.gc.ngpio = SIRFSOC_GPIO_BANK_SIZE * SIRFSOC_GPIO_NO_OF_BANKS;  in sirfsoc_gpio_probe()
817 	sgpio->chip.gc.label = kasprintf(GFP_KERNEL, "%pOF", np);  in sirfsoc_gpio_probe()
818 	sgpio->chip.gc.of_node = np;  in sirfsoc_gpio_probe()
819 	sgpio->chip.gc.of_xlate = sirfsoc_gpio_of_xlate;  in sirfsoc_gpio_probe()
820 	sgpio->chip.gc.of_gpio_n_cells = 2;  in sirfsoc_gpio_probe()
821 	sgpio->chip.gc.parent = &pdev->dev;  in sirfsoc_gpio_probe()
822 	sgpio->chip.regs = regs;  in sirfsoc_gpio_probe()
824 	girq = &sgpio->chip.gc.irq;  in sirfsoc_gpio_probe()
825 	girq->chip = &sirfsoc_irq_chip;  in sirfsoc_gpio_probe()
826 	girq->parent_handler = sirfsoc_gpio_handle_irq;  in sirfsoc_gpio_probe()
827 	girq->num_parents = SIRFSOC_GPIO_NO_OF_BANKS;  in sirfsoc_gpio_probe()
828 	girq->parents = devm_kcalloc(&pdev->dev, SIRFSOC_GPIO_NO_OF_BANKS,  in sirfsoc_gpio_probe()
829 				     sizeof(*girq->parents),  in sirfsoc_gpio_probe()
831 	if (!girq->parents) {  in sirfsoc_gpio_probe()
832 		err = -ENOMEM;  in sirfsoc_gpio_probe()
836 		bank = &sgpio->sgpio_bank[i];  in sirfsoc_gpio_probe()
837 		spin_lock_init(&bank->lock);  in sirfsoc_gpio_probe()
838 		bank->parent_irq = platform_get_irq(pdev, i);  in sirfsoc_gpio_probe()
839 		if (bank->parent_irq < 0) {  in sirfsoc_gpio_probe()
840 			err = bank->parent_irq;  in sirfsoc_gpio_probe()
843 		girq->parents[i] = bank->parent_irq;  in sirfsoc_gpio_probe()
845 	girq->default_type = IRQ_TYPE_NONE;  in sirfsoc_gpio_probe()
846 	girq->handler = handle_level_irq;  in sirfsoc_gpio_probe()
848 	err = gpiochip_add_data(&sgpio->chip.gc, sgpio);  in sirfsoc_gpio_probe()
850 		dev_err(&pdev->dev, "%pOF: error in probe function with status %d\n",  in sirfsoc_gpio_probe()
855 	err = gpiochip_add_pin_range(&sgpio->chip.gc, dev_name(&pdev->dev),  in sirfsoc_gpio_probe()
858 		dev_err(&pdev->dev,  in sirfsoc_gpio_probe()
874 	gpiochip_remove(&sgpio->chip.gc);  in sirfsoc_gpio_probe()
878 	put_device(&pdev->dev);  in sirfsoc_gpio_probe()
890 		return -ENODEV;  in sirfsoc_gpio_init()