Lines Matching +full:0 +full:- +full:4
1 // SPDX-License-Identifier: GPL-2.0
3 * R8A77470 processor support - PFC hardware block.
14 PORT_GP_4(0, fn, sfx), \
15 PORT_GP_1(0, 4, fn, sfx), \
16 PORT_GP_CFG_1(0, 5, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
17 PORT_GP_CFG_1(0, 6, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
18 PORT_GP_CFG_1(0, 7, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
19 PORT_GP_CFG_1(0, 8, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
20 PORT_GP_CFG_1(0, 9, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
21 PORT_GP_CFG_1(0, 10, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
22 PORT_GP_1(0, 11, fn, sfx), \
23 PORT_GP_1(0, 12, fn, sfx), \
24 PORT_GP_CFG_1(0, 13, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
25 PORT_GP_CFG_1(0, 14, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
26 PORT_GP_CFG_1(0, 15, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
27 PORT_GP_CFG_1(0, 16, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
28 PORT_GP_CFG_1(0, 17, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
29 PORT_GP_CFG_1(0, 18, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
30 PORT_GP_CFG_1(0, 19, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
31 PORT_GP_CFG_1(0, 20, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
32 PORT_GP_CFG_1(0, 21, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
33 PORT_GP_CFG_1(0, 22, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
40 PORT_GP_14(4, fn, sfx), \
41 PORT_GP_CFG_1(4, 14, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
42 PORT_GP_CFG_1(4, 15, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
43 PORT_GP_CFG_1(4, 16, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
44 PORT_GP_CFG_1(4, 17, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
45 PORT_GP_CFG_1(4, 18, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
46 PORT_GP_CFG_1(4, 19, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
47 PORT_GP_1(4, 20, fn, sfx), \
48 PORT_GP_1(4, 21, fn, sfx), \
49 PORT_GP_1(4, 22, fn, sfx), \
50 PORT_GP_1(4, 23, fn, sfx), \
51 PORT_GP_1(4, 24, fn, sfx), \
52 PORT_GP_1(4, 25, fn, sfx), \
56 PINMUX_RESERVED = 0,
1128 /* - AVB -------------------------------------------------------------------- */
1169 RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
1170 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 1),
1187 RCAR_GP_PIN(4, 1), RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12),
1190 RCAR_GP_PIN(4, 0), RCAR_GP_PIN(5, 22), RCAR_GP_PIN(3, 13),
1193 RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
1194 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 6),
1232 /* - DU --------------------------------------------------------------------- */
1236 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 2),
1251 /* R[7:0], G[7:0], B[7:0] */
1253 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 2),
1254 RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 0),
1321 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 7),
1322 RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 4),
1323 RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 15),
1324 RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 12),
1325 RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 24), RCAR_GP_PIN(4, 23),
1326 RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 20),
1337 /* R[7:0], G[7:0], B[7:0] */
1338 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 7),
1339 RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 4),
1340 RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 2),
1341 RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 15),
1342 RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 12),
1343 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 10),
1344 RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 24), RCAR_GP_PIN(4, 23),
1345 RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 20),
1346 RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 18),
1365 RCAR_GP_PIN(5, 0),
1379 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 4),
1405 /* - I2C0 ------------------------------------------------------------------- */
1408 RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
1441 /* - I2C1 ------------------------------------------------------------------- */
1444 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
1458 RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 23),
1472 RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 17),
1477 /* - I2C2 ------------------------------------------------------------------- */
1480 RCAR_GP_PIN(4, 24), RCAR_GP_PIN(4, 25),
1494 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
1501 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
1506 /* - I2C3 ------------------------------------------------------------------- */
1516 RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
1542 /* - I2C4 ------------------------------------------------------------------- */
1545 RCAR_GP_PIN(4, 10), RCAR_GP_PIN(4, 11),
1559 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 5),
1578 /* - MMC -------------------------------------------------------------------- */
1581 RCAR_GP_PIN(0, 15),
1587 /* D[0:3] */
1588 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 16),
1589 RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 18),
1596 /* D[0:3] */
1597 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 16),
1598 RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 18),
1599 RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 20),
1600 RCAR_GP_PIN(0, 21), RCAR_GP_PIN(0, 22),
1610 RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 14),
1615 /* - QSPI ------------------------------------------------------------------- */
1641 RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 9),
1648 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
1655 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 7),
1656 RCAR_GP_PIN(4, 8),
1662 /* - SCIF0 ------------------------------------------------------------------ */
1665 RCAR_GP_PIN(4, 10), RCAR_GP_PIN(4, 11),
1679 RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
1691 /* - SCIF1 ------------------------------------------------------------------ */
1694 RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 17),
1701 RCAR_GP_PIN(4, 15),
1736 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
1741 /* - SCIF2 ------------------------------------------------------------------ */
1744 RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 19),
1751 RCAR_GP_PIN(4, 20),
1777 /* - SCIF3 ------------------------------------------------------------------ */
1780 RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 23),
1787 RCAR_GP_PIN(4, 21),
1801 RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6),
1806 /* - SCIF4 ------------------------------------------------------------------ */
1809 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
1837 RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 8),
1842 /* - SCIF5 ------------------------------------------------------------------ */
1845 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
1852 RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
1859 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
1873 RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10),
1885 /* - SCIF Clock ------------------------------------------------------------- */
1900 /* - SDHI0 ------------------------------------------------------------------ */
1903 RCAR_GP_PIN(0, 7),
1909 /* D[0:3] */
1910 RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 8),
1911 RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10),
1918 RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6),
1925 RCAR_GP_PIN(0, 11),
1932 RCAR_GP_PIN(0, 12),
1937 /* - SDHI1 ------------------------------------------------------------------ */
1940 RCAR_GP_PIN(0, 15),
1946 /* D[0:3] */
1947 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 16),
1948 RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 18),
1956 RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 14),
1963 RCAR_GP_PIN(0, 19),
1970 RCAR_GP_PIN(0, 20),
1975 /* - SDHI2 ------------------------------------------------------------------ */
1978 RCAR_GP_PIN(4, 16),
1984 /* D[0:3] */
1985 RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 17),
1986 RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 19),
1993 RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 15),
2000 RCAR_GP_PIN(4, 20),
2007 RCAR_GP_PIN(4, 21),
2012 /* - USB0 ------------------------------------------------------------------- */
2014 RCAR_GP_PIN(0, 0), /* PWEN */
2015 RCAR_GP_PIN(0, 1), /* OVC */
2021 /* - USB1 ------------------------------------------------------------------- */
2023 RCAR_GP_PIN(0, 2), /* PWEN */
2024 RCAR_GP_PIN(0, 3), /* OVC */
2030 /* - VIN0 ------------------------------------------------------------------- */
2039 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
2040 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
2041 RCAR_GP_PIN(4, 6), RCAR_GP_PIN(5, 8),
2075 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
2076 RCAR_GP_PIN(4, 6), RCAR_GP_PIN(5, 8),
2123 /* - VIN1 ------------------------------------------------------------------- */
2127 RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4),
2165 RCAR_GP_PIN(3, 0),
2544 { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1, GROUP(
2545 0, 0,
2546 0, 0,
2547 0, 0,
2548 0, 0,
2549 0, 0,
2550 0, 0,
2551 0, 0,
2552 0, 0,
2553 0, 0,
2578 { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1, GROUP(
2579 0, 0,
2580 0, 0,
2581 0, 0,
2582 0, 0,
2583 0, 0,
2584 0, 0,
2585 0, 0,
2586 0, 0,
2587 0, 0,
2612 { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1, GROUP(
2646 { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1, GROUP(
2647 0, 0,
2648 0, 0,
2652 0, 0,
2653 0, 0,
2654 0, 0,
2655 0, 0,
2656 0, 0,
2657 0, 0,
2658 0, 0,
2659 0, 0,
2660 0, 0,
2661 0, 0,
2680 { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1, GROUP(
2681 0, 0,
2682 0, 0,
2683 0, 0,
2684 0, 0,
2685 0, 0,
2686 0, 0,
2714 { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1, GROUP(
2748 { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060040, 32,
2749 GROUP(4, 4, 4, 4, 4, 4, 4, 4),
2751 /* IP0_31_28 [4] */
2752 FN_SD0_WP, FN_IRQ7, FN_CAN0_TX_A, 0, 0, 0, 0, 0,
2753 0, 0, 0, 0, 0, 0, 0, 0,
2754 /* IP0_27_24 [4] */
2755 FN_SD0_CD, 0, FN_CAN0_RX_A, 0, 0, 0, 0, 0,
2756 0, 0, 0, 0, 0, 0, 0, 0,
2757 /* IP0_23_20 [4] */
2758 FN_SD0_DAT3, 0, 0, FN_SSI_SDATA0_B, FN_TX5_E, 0, 0, 0,
2759 0, 0, 0, 0, 0, 0, 0, 0,
2760 /* IP0_19_16 [4] */
2761 FN_SD0_DAT2, 0, 0, FN_SSI_WS0129_B, FN_RX5_E, 0, 0, 0,
2762 0, 0, 0, 0, 0, 0, 0, 0,
2763 /* IP0_15_12 [4] */
2764 FN_SD0_DAT1, 0, 0, FN_SSI_SCK0129_B, FN_TX4_E, 0, 0, 0,
2765 0, 0, 0, 0, 0, 0, 0, 0,
2766 /* IP0_11_8 [4] */
2767 FN_SD0_DAT0, 0, 0, FN_SSI_SDATA1_C, FN_RX4_E, 0, 0, 0,
2768 0, 0, 0, 0, 0, 0, 0, 0,
2769 /* IP0_7_4 [4] */
2770 FN_SD0_CMD, 0, 0, FN_SSI_WS1_C, FN_TX3_C, 0, 0, 0,
2771 0, 0, 0, 0, 0, 0, 0, 0,
2772 /* IP0_3_0 [4] */
2773 FN_SD0_CLK, 0, 0, FN_SSI_SCK1_C, FN_RX3_C, 0, 0, 0,
2774 0, 0, 0, 0, 0, 0, 0, 0, ))
2776 { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060044, 32,
2777 GROUP(4, 4, 4, 4, 4, 4, 4, 4),
2779 /* IP1_31_28 [4] */
2780 FN_D5, FN_HRX2, FN_SCL1_B, FN_PWM2_C, FN_TCLK2_B, 0, 0, 0,
2781 0, 0, 0, 0, 0, 0, 0, 0,
2782 /* IP1_27_24 [4] */
2783 FN_D4, 0, FN_IRQ3, FN_TCLK1_A, FN_PWM6_C, 0, 0, 0,
2784 0, 0, 0, 0, 0, 0, 0, 0,
2785 /* IP1_23_20 [4] */
2786 FN_D3, 0, FN_TX4_B, FN_SDA0_D, FN_PWM0_A,
2787 FN_MSIOF2_SYNC_C, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2788 /* IP1_19_16 [4] */
2789 FN_D2, 0, FN_RX4_B, FN_SCL0_D, FN_PWM1_C,
2790 FN_MSIOF2_SCK_C, FN_SSI_SCK5_B, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2791 /* IP1_15_12 [4] */
2792 FN_D1, 0, FN_SDA3_B, FN_TX5_B, 0, FN_MSIOF2_TXD_C,
2793 FN_SSI_WS5_B, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2794 /* IP1_11_8 [4] */
2795 FN_D0, 0, FN_SCL3_B, FN_RX5_B, FN_IRQ4,
2796 FN_MSIOF2_RXD_C, FN_SSI_SDATA5_B, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2797 /* IP1_7_4 [4] */
2798 FN_MMC0_D5, FN_SD1_WP, 0, 0, 0, 0, 0, 0,
2799 0, 0, 0, 0, 0, 0, 0, 0,
2800 /* IP1_3_0 [4] */
2801 FN_MMC0_D4, FN_SD1_CD, 0, 0, 0, 0, 0, 0,
2802 0, 0, 0, 0, 0, 0, 0, 0, ))
2804 { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060048, 32,
2805 GROUP(4, 4, 4, 4, 4, 4, 4, 4),
2807 /* IP2_31_28 [4] */
2808 FN_D13, FN_MSIOF2_SYNC_A, 0, FN_RX4_C, 0, 0, 0, 0, 0,
2809 0, 0, 0, 0, 0, 0, 0,
2810 /* IP2_27_24 [4] */
2811 FN_D12, FN_MSIOF2_SCK_A, FN_HSCK0, 0, FN_CAN_CLK_C,
2812 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2813 /* IP2_23_20 [4] */
2814 FN_D11, FN_MSIOF2_TXD_A, FN_HTX0_B, 0, 0, 0, 0, 0, 0,
2815 0, 0, 0, 0, 0, 0, 0,
2816 /* IP2_19_16 [4] */
2817 FN_D10, FN_MSIOF2_RXD_A, FN_HRX0_B, 0, 0, 0, 0, 0, 0,
2818 0, 0, 0, 0, 0, 0, 0,
2819 /* IP2_15_12 [4] */
2820 FN_D9, FN_HRTS2_N, FN_TX1_C, FN_SDA1_D, 0, 0, 0,
2821 0, 0, 0, 0, 0, 0, 0, 0, 0,
2822 /* IP2_11_8 [4] */
2823 FN_D8, FN_HCTS2_N, FN_RX1_C, FN_SCL1_D, FN_PWM3_C, 0,
2824 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2825 /* IP2_7_4 [4] */
2827 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2828 /* IP2_3_0 [4] */
2829 FN_D6, FN_HTX2, FN_SDA1_B, FN_PWM4_C, 0, 0, 0, 0,
2830 0, 0, 0, 0, 0, 0, 0, 0, ))
2832 { PINMUX_CFG_REG_VAR("IPSR3", 0xE606004C, 32,
2833 GROUP(4, 4, 4, 4, 4, 4, 4, 4),
2835 /* IP3_31_28 [4] */
2836 FN_QSPI0_SSL, FN_WE1_N, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2837 0, 0,
2838 /* IP3_27_24 [4] */
2839 FN_QSPI0_IO3, FN_RD_N, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2840 0, 0,
2841 /* IP3_23_20 [4] */
2842 FN_QSPI0_IO2, FN_CS0_N, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2843 0, 0,
2844 /* IP3_19_16 [4] */
2845 FN_QSPI0_MISO_QSPI0_IO1, FN_RD_WR_N, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2846 0, 0, 0, 0,
2847 /* IP3_15_12 [4] */
2848 FN_QSPI0_MOSI_QSPI0_IO0, FN_BS_N, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2849 0, 0, 0,
2850 /* IP3_11_8 [4] */
2851 FN_QSPI0_SPCLK, FN_WE0_N, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2852 0, 0,
2853 /* IP3_7_4 [4] */
2854 FN_D15, FN_MSIOF2_SS2, FN_PWM4_A, 0, FN_CAN1_TX_B, FN_IRQ2,
2855 FN_AVB_AVTP_MATCH_A, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2856 /* IP3_3_0 [4] */
2857 FN_D14, FN_MSIOF2_SS1, 0, FN_TX4_C, FN_CAN1_RX_B,
2858 0, FN_AVB_AVTP_CAPTURE_A,
2859 0, 0, 0, 0, 0, 0, 0, 0, 0, ))
2861 { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060050, 32,
2862 GROUP(4, 4, 4, 4, 4, 4, 4, 4),
2864 /* IP4_31_28 [4] */
2865 FN_DU0_DR6, 0, FN_RX2_C, 0, 0, 0, FN_A6, 0,
2866 0, 0, 0, 0, 0, 0, 0, 0,
2867 /* IP4_27_24 [4] */
2868 FN_DU0_DR5, 0, FN_TX1_D, 0, FN_PWM1_B, 0, FN_A5, 0,
2869 0, 0, 0, 0, 0, 0, 0, 0,
2870 /* IP4_23_20 [4] */
2871 FN_DU0_DR4, 0, FN_RX1_D, 0, 0, 0, FN_A4, 0, 0, 0, 0,
2872 0, 0, 0, 0, 0,
2873 /* IP4_19_16 [4] */
2874 FN_DU0_DR3, 0, FN_TX0_D, FN_SDA0_E, FN_PWM0_B, 0,
2875 FN_A3, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2876 /* IP4_15_12 [4] */
2877 FN_DU0_DR2, 0, FN_RX0_D, FN_SCL0_E, 0, 0, FN_A2, 0,
2878 0, 0, 0, 0, 0, 0, 0, 0,
2879 /* IP4_11_8 [4] */
2880 FN_DU0_DR1, 0, FN_TX5_C, FN_SDA2_D, 0, 0, FN_A1, 0,
2881 0, 0, 0, 0, 0, 0, 0, 0,
2882 /* IP4_7_4 [4] */
2883 FN_DU0_DR0, 0, FN_RX5_C, FN_SCL2_D, 0, 0, FN_A0, 0,
2884 0, 0, 0, 0, 0, 0, 0, 0,
2885 /* IP4_3_0 [4] */
2886 FN_EX_WAIT0, FN_CAN_CLK_B, FN_SCIF_CLK_A, 0, 0, 0, 0,
2887 0, 0, 0, 0, 0, 0, 0, 0, 0, ))
2889 { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060054, 32,
2890 GROUP(4, 4, 4, 4, 4, 4, 4, 4),
2892 /* IP5_31_28 [4] */
2893 FN_DU0_DG6, 0, FN_HRX1_C, 0, 0, 0, FN_A14, 0, 0, 0,
2894 0, 0, 0, 0, 0, 0,
2895 /* IP5_27_24 [4] */
2896 FN_DU0_DG5, 0, FN_HTX0_A, 0, FN_PWM5_B, 0, FN_A13,
2897 0, 0, 0, 0, 0, 0, 0, 0, 0,
2898 /* IP5_23_20 [4] */
2899 FN_DU0_DG4, 0, FN_HRX0_A, 0, 0, 0, FN_A12, 0, 0, 0,
2900 0, 0, 0, 0, 0, 0,
2901 /* IP5_19_16 [4] */
2902 FN_DU0_DG3, 0, FN_TX4_D, 0, FN_PWM4_B, 0, FN_A11, 0,
2903 0, 0, 0, 0, 0, 0, 0, 0,
2904 /* IP5_15_12 [4] */
2905 FN_DU0_DG2, 0, FN_RX4_D, 0, 0, 0, FN_A10, 0, 0, 0,
2906 0, 0, 0, 0, 0, 0,
2907 /* IP5_11_8 [4] */
2908 FN_DU0_DG1, 0, FN_TX3_B, FN_SDA3_D, FN_PWM3_B, 0,
2909 FN_A9, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2910 /* IP5_7_4 [4] */
2911 FN_DU0_DG0, 0, FN_RX3_B, FN_SCL3_D, 0, 0, FN_A8, 0,
2912 0, 0, 0, 0, 0, 0, 0, 0,
2913 /* IP5_3_0 [4] */
2914 FN_DU0_DR7, 0, FN_TX2_C, 0, FN_PWM2_B, 0, FN_A7, 0,
2915 0, 0, 0, 0, 0, 0, 0, 0, ))
2917 { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060058, 32,
2918 GROUP(4, 4, 4, 4, 4, 4, 4, 4),
2920 /* IP6_31_28 [4] */
2921 FN_DU0_DB6, 0, 0, 0, 0, 0, FN_A22, 0, 0,
2922 0, 0, 0, 0, 0, 0, 0,
2923 /* IP6_27_24 [4] */
2924 FN_DU0_DB5, 0, FN_HRTS1_N_C, 0, 0, 0,
2925 FN_A21, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2926 /* IP6_23_20 [4] */
2927 FN_DU0_DB4, 0, FN_HCTS1_N_C, 0, 0, 0,
2928 FN_A20, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2929 /* IP6_19_16 [4] */
2930 FN_DU0_DB3, 0, FN_HRTS0_N, 0, 0, 0, FN_A19, 0, 0, 0,
2931 0, 0, 0, 0, 0, 0,
2932 /* IP6_15_12 [4] */
2933 FN_DU0_DB2, 0, FN_HCTS0_N, 0, 0, 0, FN_A18, 0, 0, 0,
2934 0, 0, 0, 0, 0, 0,
2935 /* IP6_11_8 [4] */
2936 FN_DU0_DB1, 0, 0, FN_SDA4_D, FN_CAN0_TX_C, 0, FN_A17,
2937 0, 0, 0, 0, 0, 0, 0, 0, 0,
2938 /* IP6_7_4 [4] */
2939 FN_DU0_DB0, 0, 0, FN_SCL4_D, FN_CAN0_RX_C, 0, FN_A16,
2940 0, 0, 0, 0, 0, 0, 0, 0, 0,
2941 /* IP6_3_0 [4] */
2942 FN_DU0_DG7, 0, FN_HTX1_C, 0, FN_PWM6_B, 0, FN_A15,
2943 0, 0, 0, 0, 0, 0, 0, 0, 0, ))
2945 { PINMUX_CFG_REG_VAR("IPSR7", 0xE606005C, 32,
2946 GROUP(4, 4, 4, 4, 4, 4, 4, 4),
2948 /* IP7_31_28 [4] */
2949 FN_DU0_DISP, 0, 0, 0, FN_CAN1_RX_C, 0, 0, 0, 0, 0, 0,
2950 0, 0, 0, 0, 0,
2951 /* IP7_27_24 [4] */
2952 FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, 0, FN_MSIOF2_SCK_B,
2953 0, 0, 0, FN_DRACK0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2954 /* IP7_23_20 [4] */
2955 FN_DU0_EXVSYNC_DU0_VSYNC, 0, FN_MSIOF2_SYNC_B, 0,
2956 0, 0, FN_DACK0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2957 /* IP7_19_16 [4] */
2958 FN_DU0_EXHSYNC_DU0_HSYNC, 0, FN_MSIOF2_TXD_B, 0,
2959 0, 0, FN_DREQ0_N, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2960 /* IP7_15_12 [4] */
2961 FN_DU0_DOTCLKOUT1, 0, FN_MSIOF2_RXD_B, 0, 0, 0,
2962 FN_CS1_N_A26, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2963 /* IP7_11_8 [4] */
2964 FN_DU0_DOTCLKOUT0, 0, 0, 0, 0, 0, FN_A25, 0, 0, 0, 0,
2965 0, 0, 0, 0, 0,
2966 /* IP7_7_4 [4] */
2967 FN_DU0_DOTCLKIN, 0, 0, 0, 0, 0, FN_A24, 0, 0, 0,
2968 0, 0, 0, 0, 0, 0,
2969 /* IP7_3_0 [4] */
2970 FN_DU0_DB7, 0, 0, 0, 0, 0, FN_A23, 0, 0,
2971 0, 0, 0, 0, 0, 0, 0, ))
2973 { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060060, 32,
2974 GROUP(4, 4, 4, 4, 4, 4, 4, 4),
2976 /* IP8_31_28 [4] */
2977 FN_VI1_DATA5, 0, 0, 0, FN_AVB_RXD4, FN_ETH_LINK, 0, 0, 0, 0,
2978 0, 0, 0, 0, 0, 0,
2979 /* IP8_27_24 [4] */
2980 FN_VI1_DATA4, 0, 0, 0, FN_AVB_RXD3, FN_ETH_RX_ER, 0, 0, 0, 0,
2981 0, 0, 0, 0, 0, 0,
2982 /* IP8_23_20 [4] */
2983 FN_VI1_DATA3, 0, 0, 0, FN_AVB_RXD2, FN_ETH_MDIO, 0, 0, 0, 0,
2984 0, 0, 0, 0, 0, 0,
2985 /* IP8_19_16 [4] */
2986 FN_VI1_DATA2, 0, 0, 0, FN_AVB_RXD1, FN_ETH_RXD1, 0, 0, 0, 0,
2987 0, 0, 0, 0, 0, 0,
2988 /* IP8_15_12 [4] */
2989 FN_VI1_DATA1, 0, 0, 0, FN_AVB_RXD0, FN_ETH_RXD0, 0, 0, 0, 0,
2990 0, 0, 0, 0, 0, 0,
2991 /* IP8_11_8 [4] */
2992 FN_VI1_DATA0, 0, 0, 0, FN_AVB_RX_DV, FN_ETH_CRS_DV, 0, 0, 0,
2993 0, 0, 0, 0, 0, 0, 0,
2994 /* IP8_7_4 [4] */
2995 FN_VI1_CLK, 0, 0, 0, FN_AVB_RX_CLK, FN_ETH_REF_CLK, 0, 0, 0,
2996 0, 0, 0, 0, 0, 0, 0,
2997 /* IP8_3_0 [4] */
2998 FN_DU0_CDE, 0, 0, 0, FN_CAN1_TX_C, 0, 0, 0, 0, 0, 0, 0,
2999 0, 0, 0, 0, ))
3001 { PINMUX_CFG_REG_VAR("IPSR9", 0xE6060064, 32,
3002 GROUP(4, 4, 4, 4, 4, 4, 4, 4),
3004 /* IP9_31_28 [4] */
3005 FN_VI1_DATA9, 0, 0, FN_SDA2_B, FN_AVB_TXD0, 0, 0, 0, 0, 0, 0,
3006 0, 0, 0, 0, 0,
3007 /* IP9_27_24 [4] */
3008 FN_VI1_DATA8, 0, 0, FN_SCL2_B, FN_AVB_TX_EN, 0, 0, 0, 0, 0, 0,
3009 0, 0, 0, 0, 0,
3010 /* IP9_23_20 [4] */
3012 FN_AVB_TX_CLK, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3013 /* IP9_19_16 [4] */
3014 FN_VI1_HSYNC_N, FN_RX0_B, FN_SCL0_C, 0, FN_AVB_GTXREFCLK,
3015 FN_ETH_MDC, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3016 /* IP9_15_12 [4] */
3017 FN_VI1_FIELD, FN_SDA3_A, 0, 0, FN_AVB_RX_ER, FN_ETH_TXD0, 0,
3018 0, 0, 0, 0, 0, 0, 0, 0, 0,
3019 /* IP9_11_8 [4] */
3020 FN_VI1_CLKENB, FN_SCL3_A, 0, 0, FN_AVB_RXD7, FN_ETH_MAGIC, 0,
3021 0, 0, 0, 0, 0, 0, 0, 0, 0,
3022 /* IP9_7_4 [4] */
3023 FN_VI1_DATA7, 0, 0, 0, FN_AVB_RXD6, FN_ETH_TX_EN, 0, 0, 0, 0,
3024 0, 0, 0, 0, 0, 0,
3025 /* IP9_3_0 [4] */
3026 FN_VI1_DATA6, 0, 0, 0, FN_AVB_RXD5, FN_ETH_TXD1, 0, 0, 0, 0,
3027 0, 0, 0, 0, 0, 0, ))
3029 { PINMUX_CFG_REG_VAR("IPSR10", 0xE6060068, 32,
3030 GROUP(4, 4, 4, 4, 4, 4, 4, 4),
3032 /* IP10_31_28 [4] */
3033 FN_SCL1_A, FN_RX4_A, FN_PWM5_D, FN_DU1_DR0, 0, 0,
3034 FN_SSI_SCK6_B, FN_VI0_G0, 0, 0, 0, 0, 0, 0, 0, 0,
3035 /* IP10_27_24 [4] */
3037 FN_CAN1_TX_D, FN_DVC_MUTE, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3038 /* IP10_23_20 [4] */
3040 FN_CAN1_RX_D, FN_MSIOF0_SYNC_B, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3041 /* IP10_19_16 [4] */
3042 FN_AVB_TXD5, FN_SCIF_CLK_B, FN_AUDIO_CLKC_B, 0,
3043 FN_SSI_SDATA1_D, 0, FN_MSIOF0_SCK_B, 0, 0, 0, 0, 0, 0, 0,
3044 0, 0,
3045 /* IP10_15_12 [4] */
3046 FN_AVB_TXD4, 0, FN_AUDIO_CLKB_B, 0, FN_SSI_WS1_D, FN_TX5_F,
3047 FN_MSIOF0_TXD_B, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3048 /* IP10_11_8 [4] */
3049 FN_AVB_TXD3, 0, FN_AUDIO_CLKA_B, 0, FN_SSI_SCK1_D, FN_RX5_F,
3050 FN_MSIOF0_RXD_B, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3051 /* IP10_7_4 [4] */
3052 FN_VI1_DATA11, 0, 0, FN_CAN0_TX_B, FN_AVB_TXD2, 0, 0, 0, 0,
3053 0, 0, 0, 0, 0, 0, 0,
3054 /* IP10_3_0 [4] */
3055 FN_VI1_DATA10, 0, 0, FN_CAN0_RX_B, FN_AVB_TXD1, 0, 0, 0, 0,
3056 0, 0, 0, 0, 0, 0, 0, ))
3058 { PINMUX_CFG_REG_VAR("IPSR11", 0xE606006C, 32,
3059 GROUP(4, 4, 4, 4, 4, 4, 4, 4),
3061 /* IP11_31_28 [4] */
3062 FN_HRX1_A, FN_SCL4_A, FN_PWM6_A, FN_DU1_DG0, FN_RX0_A, 0, 0,
3063 0, 0, 0, 0, 0, 0, 0, 0, 0,
3064 /* IP11_27_24 [4] */
3065 FN_MSIOF0_SS2_A, 0, 0, FN_DU1_DR7, 0,
3066 FN_QSPI1_SSL, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3067 /* IP11_23_20 [4] */
3068 FN_MSIOF0_SS1_A, 0, 0, FN_DU1_DR6, 0,
3069 FN_QSPI1_IO3, FN_SSI_SDATA8_B, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3070 /* IP11_19_16 [4] */
3071 FN_MSIOF0_SYNC_A, FN_PWM1_A, 0, FN_DU1_DR5,
3072 0, FN_QSPI1_IO2, FN_SSI_SDATA7_B, 0, 0, 0, 0, 0,
3073 0, 0, 0, 0,
3074 /* IP11_15_12 [4] */
3075 FN_MSIOF0_SCK_A, FN_IRQ0, 0, FN_DU1_DR4,
3076 0, FN_QSPI1_SPCLK, FN_SSI_SCK78_B, FN_VI0_G4,
3077 0, 0, 0, 0, 0, 0, 0, 0,
3078 /* IP11_11_8 [4] */
3079 FN_MSIOF0_TXD_A, FN_TX5_A, FN_SDA2_C, FN_DU1_DR3, 0,
3081 0, 0, 0, 0, 0, 0, 0, 0,
3082 /* IP11_7_4 [4] */
3083 FN_MSIOF0_RXD_A, FN_RX5_A, FN_SCL2_C, FN_DU1_DR2, 0,
3085 0, 0, 0, 0, 0, 0, 0, 0,
3086 /* IP11_3_0 [4] */
3087 FN_SDA1_A, FN_TX4_A, 0, FN_DU1_DR1, 0, 0, FN_SSI_WS6_B,
3088 FN_VI0_G1, 0, 0, 0, 0, 0, 0, 0, 0, ))
3090 { PINMUX_CFG_REG_VAR("IPSR12", 0xE6060070, 32,
3091 GROUP(4, 4, 4, 4, 4, 4, 4, 4),
3093 /* IP12_31_28 [4] */
3094 FN_SD2_DAT2, FN_RX2_A, 0, FN_DU1_DB0, FN_SSI_SDATA2_B, 0, 0,
3095 0, 0, 0, 0, 0, 0, 0, 0, 0,
3096 /* IP12_27_24 [4] */
3098 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3099 /* IP12_23_20 [4] */
3101 FN_SSI_SDATA1_B, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3102 /* IP12_19_16 [4] */
3104 FN_SSI_SCK2_B, FN_PWM3_A, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3105 /* IP12_15_12 [4] */
3106 FN_SD2_CLK, FN_HSCK1, 0, FN_DU1_DG4, FN_SSI_SCK1_B, 0, 0, 0,
3107 0, 0, 0, 0, 0, 0, 0, 0,
3108 /* IP12_11_8 [4] */
3109 FN_HRTS1_N_A, 0, 0, FN_DU1_DG3, FN_SSI_WS1_B, FN_IRQ1, 0, 0,
3110 0, 0, 0, 0, 0, 0, 0, 0,
3111 /* IP12_7_4 [4] */
3112 FN_HCTS1_N_A, FN_PWM2_A, 0, FN_DU1_DG2, FN_REMOCON_B,
3113 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3114 /* IP12_3_0 [4] */
3115 FN_HTX1_A, FN_SDA4_A, 0, FN_DU1_DG1, FN_TX0_A, 0, 0, 0, 0, 0,
3116 0, 0, 0, 0, 0, 0, ))
3118 { PINMUX_CFG_REG_VAR("IPSR13", 0xE6060074, 32,
3119 GROUP(4, 4, 4, 4, 4, 4, 4, 4),
3121 /* IP13_31_28 [4] */
3122 FN_SSI_SCK5_A, 0, 0, FN_DU1_DOTCLKOUT1, 0, 0, 0, 0, 0, 0, 0,
3123 0, 0, 0, 0, 0,
3124 /* IP13_27_24 [4] */
3125 FN_SDA2_A, 0, FN_MSIOF1_SYNC_B, FN_DU1_DB7, FN_AUDIO_CLKOUT_C,
3126 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3127 /* IP13_23_20 [4] */
3128 FN_SCL2_A, 0, FN_MSIOF1_SCK_B, FN_DU1_DB6, FN_AUDIO_CLKC_C,
3129 FN_SSI_SCK4_B, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3130 /* IP13_19_16 [4] */
3132 FN_AUDIO_CLKB_C, FN_SSI_WS4_B, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3133 /* IP13_15_12 [4] */
3135 FN_AUDIO_CLKA_C, FN_SSI_SDATA4_B, 0, 0, 0, 0, 0, 0, 0, 0,
3136 0, 0,
3137 /* IP13_11_8 [4] */
3138 FN_SD2_WP, FN_SCIF3_SCK, 0, FN_DU1_DB3, FN_SSI_SDATA9_B, 0,
3139 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3140 /* IP13_7_4 [4] */
3141 FN_SD2_CD, FN_SCIF2_SCK_A, 0, FN_DU1_DB2, FN_SSI_SCK9_B, 0, 0,
3142 0, 0, 0, 0, 0, 0, 0, 0, 0,
3143 /* IP13_3_0 [4] */
3144 FN_SD2_DAT3, FN_TX2_A, 0, FN_DU1_DB1, FN_SSI_WS9_B, 0, 0, 0,
3145 0, 0, 0, 0, 0, 0, 0, 0, ))
3147 { PINMUX_CFG_REG_VAR("IPSR14", 0xE6060078, 32,
3148 GROUP(4, 4, 4, 4, 4, 4, 4, 4),
3150 /* IP14_31_28 [4] */
3151 FN_SSI_SDATA7_A, 0, 0, FN_IRQ8, FN_AUDIO_CLKA_D, FN_CAN_CLK_D,
3152 FN_VI0_G5, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3153 /* IP14_27_24 [4] */
3154 FN_SSI_WS78_A, 0, FN_SCL4_E, FN_DU1_CDE, 0, 0, 0, 0, 0, 0, 0,
3155 0, 0, 0, 0, 0,
3156 /* IP14_23_20 [4] */
3157 FN_SSI_SCK78_A, 0, FN_SDA4_E, FN_DU1_DISP, 0, 0, 0, 0, 0, 0,
3158 0, 0, 0, 0, 0, 0,
3159 /* IP14_19_16 [4] */
3160 FN_SSI_SDATA6_A, 0, FN_SDA4_C, FN_DU1_EXVSYNC_DU1_VSYNC, 0, 0,
3161 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3162 /* IP14_15_12 [4] */
3163 FN_SSI_WS6_A, 0, FN_SCL4_C, FN_DU1_EXHSYNC_DU1_HSYNC, 0, 0, 0,
3164 0, 0, 0, 0, 0, 0, 0, 0, 0,
3165 /* IP14_11_8 [4] */
3166 FN_SSI_SCK6_A, 0, 0, FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, 0, 0,
3167 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3168 /* IP14_7_4 [4] */
3169 FN_SSI_SDATA5_A, 0, FN_SDA3_C, FN_DU1_DOTCLKOUT0, 0, 0, 0,
3170 0, 0, 0, 0, 0, 0, 0, 0, 0,
3171 /* IP14_3_0 [4] */
3172 FN_SSI_WS5_A, 0, FN_SCL3_C, FN_DU1_DOTCLKIN, 0, 0, 0, 0, 0, 0,
3173 0, 0, 0, 0, 0, 0, ))
3175 { PINMUX_CFG_REG_VAR("IPSR15", 0xE606007C, 32,
3176 GROUP(4, 4, 4, 4, 4, 4, 4, 4),
3178 /* IP15_31_28 [4] */
3179 FN_SSI_WS4_A, 0, FN_AVB_PHY_INT, 0, 0, 0, FN_VI0_R5, 0, 0, 0,
3180 0, 0, 0, 0, 0, 0,
3181 /* IP15_27_24 [4] */
3182 FN_SSI_SCK4_A, 0, FN_AVB_MAGIC, 0, 0, 0, FN_VI0_R4, 0, 0, 0,
3183 0, 0, 0, 0, 0, 0,
3184 /* IP15_23_20 [4] */
3185 FN_SSI_SDATA3, FN_MSIOF1_SS2_A, FN_AVB_LINK, 0, FN_CAN1_TX_A,
3186 FN_DREQ2_N, FN_VI0_R3, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3187 /* IP15_19_16 [4] */
3188 FN_SSI_WS34, FN_MSIOF1_SS1_A, FN_AVB_MDIO, 0, FN_CAN1_RX_A,
3189 FN_DREQ1_N, FN_VI0_R2, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3190 /* IP15_15_12 [4] */
3191 FN_SSI_SCK34, FN_MSIOF1_SCK_A, FN_AVB_MDC, 0, 0, FN_DACK1,
3192 FN_VI0_R1, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3193 /* IP15_11_8 [4] */
3194 FN_SSI_SDATA0_A, FN_MSIOF1_SYNC_A, FN_PWM0_C, 0, 0, 0,
3195 FN_VI0_R0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3196 /* IP15_7_4 [4] */
3197 FN_SSI_WS0129_A, FN_MSIOF1_TXD_A, FN_TX5_D, 0, 0, 0,
3198 FN_VI0_G7, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3199 /* IP15_3_0 [4] */
3200 FN_SSI_SCK0129_A, FN_MSIOF1_RXD_A, FN_RX5_D, 0, 0, 0,
3201 FN_VI0_G6, 0, 0, 0, 0, 0, 0, 0, 0, 0, ))
3203 { PINMUX_CFG_REG_VAR("IPSR16", 0xE6060080, 32,
3204 GROUP(4, 4, 4, 4, 4, 4, 4, 4),
3206 /* IP16_31_28 [4] */
3207 FN_SSI_SDATA2_A, FN_HRTS1_N_B, 0, 0, 0, 0,
3208 FN_VI0_DATA4_VI0_B4, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3209 /* IP16_27_24 [4] */
3210 FN_SSI_WS2_A, FN_HCTS1_N_B, 0, 0, 0, FN_AVB_TX_ER,
3211 FN_VI0_DATA3_VI0_B3, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3212 /* IP16_23_20 [4] */
3213 FN_SSI_SCK2_A, FN_HTX1_B, 0, 0, 0, FN_AVB_TXD7,
3214 FN_VI0_DATA2_VI0_B2, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3215 /* IP16_19_16 [4] */
3216 FN_SSI_SDATA1_A, FN_HRX1_B, 0, 0, 0, 0, FN_VI0_DATA1_VI0_B1,
3217 0, 0, 0, 0, 0, 0, 0, 0, 0,
3218 /* IP16_15_12 [4] */
3219 FN_SSI_WS1_A, FN_TX1_B, 0, 0, FN_CAN0_TX_D,
3220 FN_AVB_AVTP_MATCH_B, FN_VI0_DATA0_VI0_B0, 0, 0, 0, 0, 0, 0,
3221 0, 0, 0,
3222 /* IP16_11_8 [4] */
3223 FN_SSI_SDATA8_A, FN_RX1_B, 0, 0, FN_CAN0_RX_D,
3224 FN_AVB_AVTP_CAPTURE_B, FN_VI0_R7, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3225 /* IP16_7_4 [4] */
3227 FN_DACK2, FN_VI0_CLK, FN_AVB_COL, 0, 0, 0, 0, 0, 0, 0, 0,
3228 /* IP16_3_0 [4] */
3229 FN_SSI_SDATA4_A, 0, FN_AVB_CRS, 0, 0, 0, FN_VI0_R6, 0, 0, 0,
3230 0, 0, 0, 0, 0, 0, ))
3232 { PINMUX_CFG_REG_VAR("IPSR17", 0xE6060084, 32,
3233 GROUP(4, 4, 4, 4, 4, 4, 4, 4),
3235 /* IP17_31_28 [4] */
3236 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3237 /* IP17_27_24 [4] */
3238 FN_AUDIO_CLKOUT_A, FN_SDA4_B, 0, 0, 0, 0,
3239 FN_VI0_VSYNC_N, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3240 /* IP17_23_20 [4] */
3241 FN_AUDIO_CLKC_A, FN_SCL4_B, 0, 0, 0, 0,
3242 FN_VI0_HSYNC_N, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3243 /* IP17_19_16 [4] */
3244 FN_AUDIO_CLKB_A, FN_SDA0_B, 0, 0, 0, 0,
3245 FN_VI0_FIELD, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3246 /* IP17_15_12 [4] */
3247 FN_AUDIO_CLKA_A, FN_SCL0_B, 0, 0, 0, 0,
3248 FN_VI0_CLKENB, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3249 /* IP17_11_8 [4] */
3250 FN_SSI_SDATA9_A, FN_SCIF2_SCK_B, FN_PWM2_D, 0, 0, 0,
3251 FN_VI0_DATA7_VI0_B7, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3252 /* IP17_7_4 [4] */
3253 FN_SSI_WS9_A, FN_TX2_B, FN_SDA3_E, 0, 0, 0,
3254 FN_VI0_DATA6_VI0_B6, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3255 /* IP17_3_0 [4] */
3256 FN_SSI_SCK9_A, FN_RX2_B, FN_SCL3_E, 0, 0, FN_EX_WAIT1,
3257 FN_VI0_DATA5_VI0_B5, 0, 0, 0, 0, 0, 0, 0, 0, 0, ))
3259 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xE60600C0, 32,
3264 0, 0,
3266 0, 0,
3268 0, 0,
3270 0, 0,
3272 0, 0,
3276 0, 0,
3278 0, 0,
3287 0, 0,
3290 FN_SEL_I2C04_4, 0, 0, 0,
3293 FN_SEL_I2C03_4, 0, 0, 0,
3295 0, 0,
3300 FN_SEL_I2C01_4, 0, 0, 0,
3303 FN_SEL_I2C00_4, 0, 0, 0,
3307 { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xE60600C4, 32,
3315 FN_SEL_SCIF5_4, FN_SEL_SCIF5_5, 0, 0,
3318 FN_SEL_SCIF4_4, 0, 0, 0,
3320 FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, FN_SEL_SCIF3_2, 0,
3322 FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2, 0,
3330 FN_SEL_MSIOF2_0, FN_SEL_MSIOF2_1, FN_SEL_MSIOF2_2, 0,
3332 0, 0,
3336 0, 0,
3342 0, 0, 0, 0,
3348 0, 0, 0, 0,
3350 FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, FN_SEL_HSCIF1_2, 0,
3354 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE60600C8, 32,
3359 0, 0,
3361 0, 0,
3363 0, 0,
3365 0, 0,
3367 0, 0,
3369 0, 0,
3371 0, 0,
3373 0, 0,
3375 0, 0,
3377 0, 0,
3379 FN_SEL_ADGB_0, FN_SEL_ADGB_1, FN_SEL_ADGB_2, 0,
3381 FN_SEL_ADGC_0, FN_SEL_ADGC_1, FN_SEL_ADGC_2, 0,
3383 FN_SEL_SSI9_0, FN_SEL_SSI9_1, 0, 0,
3385 FN_SEL_SSI8_0, FN_SEL_SSI8_1, 0, 0,
3387 FN_SEL_SSI7_0, FN_SEL_SSI7_1, 0, 0,
3389 FN_SEL_SSI6_0, FN_SEL_SSI6_1, 0, 0,
3391 FN_SEL_SSI5_0, FN_SEL_SSI5_1, 0, 0,
3393 FN_SEL_SSI4_0, FN_SEL_SSI4_1, 0, 0,
3395 FN_SEL_SSI2_0, FN_SEL_SSI2_1, 0, 0,
3399 FN_SEL_SSI0_0, FN_SEL_SSI0_1, 0, 0, ))
3407 int bit = -EINVAL; in r8a77470_pin_to_pocctrl()
3409 *pocctrl = 0xe60600b0; in r8a77470_pin_to_pocctrl()
3411 if (pin >= RCAR_GP_PIN(0, 5) && pin <= RCAR_GP_PIN(0, 10)) in r8a77470_pin_to_pocctrl()
3412 bit = 0; in r8a77470_pin_to_pocctrl()
3414 if (pin >= RCAR_GP_PIN(0, 13) && pin <= RCAR_GP_PIN(0, 22)) in r8a77470_pin_to_pocctrl()
3417 if (pin >= RCAR_GP_PIN(4, 14) && pin <= RCAR_GP_PIN(4, 19)) in r8a77470_pin_to_pocctrl()
3431 .unlock_reg = 0xe6060000, /* PMMR */